1 /* 2 * OpenRISC simulator for use as an IIS. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Feng Gao <gf91597@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "hw/irq.h" 26 #include "hw/boards.h" 27 #include "elf.h" 28 #include "hw/char/serial.h" 29 #include "net/net.h" 30 #include "hw/loader.h" 31 #include "hw/qdev-properties.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/sysbus.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "hw/core/split-irq.h" 37 38 #define KERNEL_LOAD_ADDR 0x100 39 40 #define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim") 41 #define OR1KSIM_MACHINE(obj) \ 42 OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE) 43 44 typedef struct Or1ksimState { 45 /*< private >*/ 46 MachineState parent_obj; 47 48 /*< public >*/ 49 50 } Or1ksimState; 51 52 enum { 53 OR1KSIM_DRAM, 54 OR1KSIM_UART, 55 OR1KSIM_ETHOC, 56 OR1KSIM_OMPIC, 57 }; 58 59 enum { 60 OR1KSIM_OMPIC_IRQ = 1, 61 OR1KSIM_UART_IRQ = 2, 62 OR1KSIM_ETHOC_IRQ = 4, 63 }; 64 65 static const struct MemmapEntry { 66 hwaddr base; 67 hwaddr size; 68 } or1ksim_memmap[] = { 69 [OR1KSIM_DRAM] = { 0x00000000, 0 }, 70 [OR1KSIM_UART] = { 0x90000000, 0x100 }, 71 [OR1KSIM_ETHOC] = { 0x92000000, 0x800 }, 72 [OR1KSIM_OMPIC] = { 0x98000000, 16 }, 73 }; 74 75 static struct openrisc_boot_info { 76 uint32_t bootstrap_pc; 77 } boot_info; 78 79 static void main_cpu_reset(void *opaque) 80 { 81 OpenRISCCPU *cpu = opaque; 82 CPUState *cs = CPU(cpu); 83 84 cpu_reset(CPU(cpu)); 85 86 cpu_set_pc(cs, boot_info.bootstrap_pc); 87 } 88 89 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) 90 { 91 return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin); 92 } 93 94 static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, 95 int num_cpus, OpenRISCCPU *cpus[], 96 int irq_pin, NICInfo *nd) 97 { 98 DeviceState *dev; 99 SysBusDevice *s; 100 int i; 101 102 dev = qdev_new("open_eth"); 103 qdev_set_nic_properties(dev, nd); 104 105 s = SYS_BUS_DEVICE(dev); 106 sysbus_realize_and_unref(s, &error_fatal); 107 if (num_cpus > 1) { 108 DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); 109 qdev_prop_set_uint32(splitter, "num-lines", num_cpus); 110 qdev_realize_and_unref(splitter, NULL, &error_fatal); 111 for (i = 0; i < num_cpus; i++) { 112 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); 113 } 114 sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0)); 115 } else { 116 sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin)); 117 } 118 sysbus_mmio_map(s, 0, base); 119 sysbus_mmio_map(s, 1, descriptors); 120 } 121 122 static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, 123 OpenRISCCPU *cpus[], int irq_pin) 124 { 125 DeviceState *dev; 126 SysBusDevice *s; 127 int i; 128 129 dev = qdev_new("or1k-ompic"); 130 qdev_prop_set_uint32(dev, "num-cpus", num_cpus); 131 132 s = SYS_BUS_DEVICE(dev); 133 sysbus_realize_and_unref(s, &error_fatal); 134 for (i = 0; i < num_cpus; i++) { 135 sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin)); 136 } 137 sysbus_mmio_map(s, 0, base); 138 } 139 140 static void openrisc_sim_serial_init(hwaddr base, int num_cpus, 141 OpenRISCCPU *cpus[], int irq_pin) 142 { 143 qemu_irq serial_irq; 144 int i; 145 146 if (num_cpus > 1) { 147 DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); 148 qdev_prop_set_uint32(splitter, "num-lines", num_cpus); 149 qdev_realize_and_unref(splitter, NULL, &error_fatal); 150 for (i = 0; i < num_cpus; i++) { 151 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); 152 } 153 serial_irq = qdev_get_gpio_in(splitter, 0); 154 } else { 155 serial_irq = get_cpu_irq(cpus, 0, irq_pin); 156 } 157 serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, 158 serial_hd(0), DEVICE_NATIVE_ENDIAN); 159 } 160 161 162 static void openrisc_load_kernel(ram_addr_t ram_size, 163 const char *kernel_filename) 164 { 165 long kernel_size; 166 uint64_t elf_entry; 167 hwaddr entry; 168 169 if (kernel_filename && !qtest_enabled()) { 170 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 171 &elf_entry, NULL, NULL, NULL, 1, EM_OPENRISC, 172 1, 0); 173 entry = elf_entry; 174 if (kernel_size < 0) { 175 kernel_size = load_uimage(kernel_filename, 176 &entry, NULL, NULL, NULL, NULL); 177 } 178 if (kernel_size < 0) { 179 kernel_size = load_image_targphys(kernel_filename, 180 KERNEL_LOAD_ADDR, 181 ram_size - KERNEL_LOAD_ADDR); 182 } 183 184 if (entry <= 0) { 185 entry = KERNEL_LOAD_ADDR; 186 } 187 188 if (kernel_size < 0) { 189 error_report("couldn't load the kernel '%s'", kernel_filename); 190 exit(1); 191 } 192 boot_info.bootstrap_pc = entry; 193 } 194 } 195 196 static void openrisc_sim_init(MachineState *machine) 197 { 198 ram_addr_t ram_size = machine->ram_size; 199 const char *kernel_filename = machine->kernel_filename; 200 OpenRISCCPU *cpus[2] = {}; 201 MemoryRegion *ram; 202 int n; 203 unsigned int smp_cpus = machine->smp.cpus; 204 205 assert(smp_cpus >= 1 && smp_cpus <= 2); 206 for (n = 0; n < smp_cpus; n++) { 207 cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type)); 208 if (cpus[n] == NULL) { 209 fprintf(stderr, "Unable to find CPU definition!\n"); 210 exit(1); 211 } 212 213 cpu_openrisc_clock_init(cpus[n]); 214 215 qemu_register_reset(main_cpu_reset, cpus[n]); 216 } 217 218 ram = g_malloc(sizeof(*ram)); 219 memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); 220 memory_region_add_subregion(get_system_memory(), 0, ram); 221 222 if (nd_table[0].used) { 223 openrisc_sim_net_init(or1ksim_memmap[OR1KSIM_ETHOC].base, 224 or1ksim_memmap[OR1KSIM_ETHOC].base + 0x400, 225 smp_cpus, cpus, 226 OR1KSIM_ETHOC_IRQ, nd_table); 227 } 228 229 if (smp_cpus > 1) { 230 openrisc_sim_ompic_init(or1ksim_memmap[OR1KSIM_OMPIC].base, smp_cpus, 231 cpus, OR1KSIM_OMPIC_IRQ); 232 } 233 234 openrisc_sim_serial_init(or1ksim_memmap[OR1KSIM_UART].base, smp_cpus, cpus, 235 OR1KSIM_UART_IRQ); 236 237 openrisc_load_kernel(ram_size, kernel_filename); 238 } 239 240 static void openrisc_sim_machine_init(ObjectClass *oc, void *data) 241 { 242 MachineClass *mc = MACHINE_CLASS(oc); 243 244 mc->desc = "or1k simulation"; 245 mc->init = openrisc_sim_init; 246 mc->max_cpus = 2; 247 mc->is_default = true; 248 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200"); 249 } 250 251 static const TypeInfo or1ksim_machine_typeinfo = { 252 .name = TYPE_OR1KSIM_MACHINE, 253 .parent = TYPE_MACHINE, 254 .class_init = openrisc_sim_machine_init, 255 .instance_size = sizeof(Or1ksimState), 256 }; 257 258 static void or1ksim_machine_init_register_types(void) 259 { 260 type_register_static(&or1ksim_machine_typeinfo); 261 } 262 263 type_init(or1ksim_machine_init_register_types) 264