153018216SPaolo Bonzini /* 253018216SPaolo Bonzini * QEMU OpenRISC timer support 353018216SPaolo Bonzini * 453018216SPaolo Bonzini * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 553018216SPaolo Bonzini * Zhizhou Zhang <etouzh@gmail.com> 653018216SPaolo Bonzini * 753018216SPaolo Bonzini * This library is free software; you can redistribute it and/or 853018216SPaolo Bonzini * modify it under the terms of the GNU Lesser General Public 953018216SPaolo Bonzini * License as published by the Free Software Foundation; either 10*198a2d21SThomas Huth * version 2.1 of the License, or (at your option) any later version. 1153018216SPaolo Bonzini * 1253018216SPaolo Bonzini * This library is distributed in the hope that it will be useful, 1353018216SPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 1453018216SPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1553018216SPaolo Bonzini * Lesser General Public License for more details. 1653018216SPaolo Bonzini * 1753018216SPaolo Bonzini * You should have received a copy of the GNU Lesser General Public 1853018216SPaolo Bonzini * License along with this library; if not, see <http://www.gnu.org/licenses/>. 1953018216SPaolo Bonzini */ 2053018216SPaolo Bonzini 21ed2decc6SPeter Maydell #include "qemu/osdep.h" 2253018216SPaolo Bonzini #include "cpu.h" 2353018216SPaolo Bonzini #include "hw/hw.h" 2453018216SPaolo Bonzini #include "qemu/timer.h" 2553018216SPaolo Bonzini 26ccaf1749SLaurent Vivier #define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */ 2753018216SPaolo Bonzini 286b4bbd6aSStafford Horne /* Tick Timer global state to allow all cores to be in sync */ 296b4bbd6aSStafford Horne typedef struct OR1KTimerState { 306b4bbd6aSStafford Horne uint32_t ttcr; 316b4bbd6aSStafford Horne uint64_t last_clk; 326b4bbd6aSStafford Horne } OR1KTimerState; 3353018216SPaolo Bonzini 346b4bbd6aSStafford Horne static OR1KTimerState *or1k_timer; 356b4bbd6aSStafford Horne 366b4bbd6aSStafford Horne void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) 376b4bbd6aSStafford Horne { 386b4bbd6aSStafford Horne or1k_timer->ttcr = val; 396b4bbd6aSStafford Horne } 406b4bbd6aSStafford Horne 416b4bbd6aSStafford Horne uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) 426b4bbd6aSStafford Horne { 436b4bbd6aSStafford Horne return or1k_timer->ttcr; 446b4bbd6aSStafford Horne } 456b4bbd6aSStafford Horne 466b4bbd6aSStafford Horne /* Add elapsed ticks to ttcr */ 4753018216SPaolo Bonzini void cpu_openrisc_count_update(OpenRISCCPU *cpu) 4853018216SPaolo Bonzini { 49d5155217SSebastian Macke uint64_t now; 5053018216SPaolo Bonzini 516b4bbd6aSStafford Horne if (!cpu->env.is_counting) { 5253018216SPaolo Bonzini return; 5353018216SPaolo Bonzini } 54d5155217SSebastian Macke now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 556b4bbd6aSStafford Horne or1k_timer->ttcr += (uint32_t)((now - or1k_timer->last_clk) 566b4bbd6aSStafford Horne / TIMER_PERIOD); 576b4bbd6aSStafford Horne or1k_timer->last_clk = now; 58d5155217SSebastian Macke } 59d5155217SSebastian Macke 606b4bbd6aSStafford Horne /* Update the next timeout time as difference between ttmr and ttcr */ 61d5155217SSebastian Macke void cpu_openrisc_timer_update(OpenRISCCPU *cpu) 62d5155217SSebastian Macke { 63d5155217SSebastian Macke uint32_t wait; 64d5155217SSebastian Macke uint64_t now, next; 65d5155217SSebastian Macke 666b4bbd6aSStafford Horne if (!cpu->env.is_counting) { 67d5155217SSebastian Macke return; 68d5155217SSebastian Macke } 69d5155217SSebastian Macke 70d5155217SSebastian Macke cpu_openrisc_count_update(cpu); 716b4bbd6aSStafford Horne now = or1k_timer->last_clk; 7253018216SPaolo Bonzini 736b4bbd6aSStafford Horne if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) { 746b4bbd6aSStafford Horne wait = TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1; 7553018216SPaolo Bonzini wait += cpu->env.ttmr & TTMR_TP; 7653018216SPaolo Bonzini } else { 776b4bbd6aSStafford Horne wait = (cpu->env.ttmr & TTMR_TP) - (or1k_timer->ttcr & TTMR_TP); 7853018216SPaolo Bonzini } 79ccaf1749SLaurent Vivier next = now + (uint64_t)wait * TIMER_PERIOD; 80bc72ad67SAlex Bligh timer_mod(cpu->env.timer, next); 8153018216SPaolo Bonzini } 8253018216SPaolo Bonzini 8353018216SPaolo Bonzini void cpu_openrisc_count_start(OpenRISCCPU *cpu) 8453018216SPaolo Bonzini { 856b4bbd6aSStafford Horne cpu->env.is_counting = 1; 8653018216SPaolo Bonzini cpu_openrisc_count_update(cpu); 8753018216SPaolo Bonzini } 8853018216SPaolo Bonzini 8953018216SPaolo Bonzini void cpu_openrisc_count_stop(OpenRISCCPU *cpu) 9053018216SPaolo Bonzini { 91d5155217SSebastian Macke timer_del(cpu->env.timer); 9253018216SPaolo Bonzini cpu_openrisc_count_update(cpu); 936b4bbd6aSStafford Horne cpu->env.is_counting = 0; 9453018216SPaolo Bonzini } 9553018216SPaolo Bonzini 9653018216SPaolo Bonzini static void openrisc_timer_cb(void *opaque) 9753018216SPaolo Bonzini { 9853018216SPaolo Bonzini OpenRISCCPU *cpu = opaque; 9953018216SPaolo Bonzini 10053018216SPaolo Bonzini if ((cpu->env.ttmr & TTMR_IE) && 101bc72ad67SAlex Bligh timer_expired(cpu->env.timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL))) { 102259186a7SAndreas Färber CPUState *cs = CPU(cpu); 103259186a7SAndreas Färber 10453018216SPaolo Bonzini cpu->env.ttmr |= TTMR_IP; 105259186a7SAndreas Färber cs->interrupt_request |= CPU_INTERRUPT_TIMER; 10653018216SPaolo Bonzini } 10753018216SPaolo Bonzini 10853018216SPaolo Bonzini switch (cpu->env.ttmr & TTMR_M) { 10953018216SPaolo Bonzini case TIMER_NONE: 11053018216SPaolo Bonzini break; 11153018216SPaolo Bonzini case TIMER_INTR: 1126b4bbd6aSStafford Horne or1k_timer->ttcr = 0; 11353018216SPaolo Bonzini break; 11453018216SPaolo Bonzini case TIMER_SHOT: 11553018216SPaolo Bonzini cpu_openrisc_count_stop(cpu); 11653018216SPaolo Bonzini break; 11753018216SPaolo Bonzini case TIMER_CONT: 11853018216SPaolo Bonzini break; 11953018216SPaolo Bonzini } 120d5155217SSebastian Macke 121d5155217SSebastian Macke cpu_openrisc_timer_update(cpu); 122373b259bSStafford Horne qemu_cpu_kick(CPU(cpu)); 12353018216SPaolo Bonzini } 12453018216SPaolo Bonzini 1256b4bbd6aSStafford Horne static const VMStateDescription vmstate_or1k_timer = { 1266b4bbd6aSStafford Horne .name = "or1k_timer", 1276b4bbd6aSStafford Horne .version_id = 1, 1286b4bbd6aSStafford Horne .minimum_version_id = 1, 1296b4bbd6aSStafford Horne .fields = (VMStateField[]) { 1306b4bbd6aSStafford Horne VMSTATE_UINT32(ttcr, OR1KTimerState), 1316b4bbd6aSStafford Horne VMSTATE_UINT64(last_clk, OR1KTimerState), 1326b4bbd6aSStafford Horne VMSTATE_END_OF_LIST() 1336b4bbd6aSStafford Horne } 1346b4bbd6aSStafford Horne }; 1356b4bbd6aSStafford Horne 13653018216SPaolo Bonzini void cpu_openrisc_clock_init(OpenRISCCPU *cpu) 13753018216SPaolo Bonzini { 138bc72ad67SAlex Bligh cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu); 13953018216SPaolo Bonzini cpu->env.ttmr = 0x00000000; 1406b4bbd6aSStafford Horne 1416b4bbd6aSStafford Horne if (or1k_timer == NULL) { 1426b4bbd6aSStafford Horne or1k_timer = g_new0(OR1KTimerState, 1); 1436b4bbd6aSStafford Horne vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer); 1446b4bbd6aSStafford Horne } 14553018216SPaolo Bonzini } 146