xref: /openbmc/qemu/hw/nvram/spapr_nvram.c (revision cf83f140059f21d4629ae4b61d468c3baef2bb4c)
1 /*
2  * QEMU sPAPR NVRAM emulation
3  *
4  * Copyright (C) 2012 David Gibson, IBM Corporation.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include <libfdt.h>
30 
31 #include "sysemu/block-backend.h"
32 #include "sysemu/device_tree.h"
33 #include "hw/sysbus.h"
34 #include "hw/nvram/chrp_nvram.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/ppc/spapr_vio.h"
37 
38 typedef struct sPAPRNVRAM {
39     VIOsPAPRDevice sdev;
40     uint32_t size;
41     uint8_t *buf;
42     BlockBackend *blk;
43     VMChangeStateEntry *vmstate;
44 } sPAPRNVRAM;
45 
46 #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram"
47 #define VIO_SPAPR_NVRAM(obj) \
48      OBJECT_CHECK(sPAPRNVRAM, (obj), TYPE_VIO_SPAPR_NVRAM)
49 
50 #define MIN_NVRAM_SIZE 8192
51 #define DEFAULT_NVRAM_SIZE 65536
52 #define MAX_NVRAM_SIZE 1048576
53 
54 static void rtas_nvram_fetch(PowerPCCPU *cpu, sPAPRMachineState *spapr,
55                              uint32_t token, uint32_t nargs,
56                              target_ulong args,
57                              uint32_t nret, target_ulong rets)
58 {
59     sPAPRNVRAM *nvram = spapr->nvram;
60     hwaddr offset, buffer, len;
61     void *membuf;
62 
63     if ((nargs != 3) || (nret != 2)) {
64         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
65         return;
66     }
67 
68     if (!nvram) {
69         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
70         rtas_st(rets, 1, 0);
71         return;
72     }
73 
74     offset = rtas_ld(args, 0);
75     buffer = rtas_ld(args, 1);
76     len = rtas_ld(args, 2);
77 
78     if (((offset + len) < offset)
79         || ((offset + len) > nvram->size)) {
80         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
81         rtas_st(rets, 1, 0);
82         return;
83     }
84 
85     assert(nvram->buf);
86 
87     membuf = cpu_physical_memory_map(buffer, &len, 1);
88     memcpy(membuf, nvram->buf + offset, len);
89     cpu_physical_memory_unmap(membuf, len, 1, len);
90 
91     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
92     rtas_st(rets, 1, len);
93 }
94 
95 static void rtas_nvram_store(PowerPCCPU *cpu, sPAPRMachineState *spapr,
96                              uint32_t token, uint32_t nargs,
97                              target_ulong args,
98                              uint32_t nret, target_ulong rets)
99 {
100     sPAPRNVRAM *nvram = spapr->nvram;
101     hwaddr offset, buffer, len;
102     int alen;
103     void *membuf;
104 
105     if ((nargs != 3) || (nret != 2)) {
106         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
107         return;
108     }
109 
110     if (!nvram) {
111         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
112         return;
113     }
114 
115     offset = rtas_ld(args, 0);
116     buffer = rtas_ld(args, 1);
117     len = rtas_ld(args, 2);
118 
119     if (((offset + len) < offset)
120         || ((offset + len) > nvram->size)) {
121         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
122         return;
123     }
124 
125     membuf = cpu_physical_memory_map(buffer, &len, 0);
126 
127     alen = len;
128     if (nvram->blk) {
129         alen = blk_pwrite(nvram->blk, offset, membuf, len, 0);
130     }
131 
132     assert(nvram->buf);
133     memcpy(nvram->buf + offset, membuf, len);
134 
135     cpu_physical_memory_unmap(membuf, len, 0, len);
136 
137     rtas_st(rets, 0, (alen < len) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS);
138     rtas_st(rets, 1, (alen < 0) ? 0 : alen);
139 }
140 
141 static void spapr_nvram_realize(VIOsPAPRDevice *dev, Error **errp)
142 {
143     sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
144     int ret;
145 
146     if (nvram->blk) {
147         nvram->size = blk_getlength(nvram->blk);
148 
149         ret = blk_set_perm(nvram->blk,
150                            BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
151                            BLK_PERM_ALL, errp);
152         if (ret < 0) {
153             return;
154         }
155     } else {
156         nvram->size = DEFAULT_NVRAM_SIZE;
157     }
158 
159     nvram->buf = g_malloc0(nvram->size);
160 
161     if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) {
162         error_setg(errp, "spapr-nvram must be between %d and %d bytes in size",
163                    MIN_NVRAM_SIZE, MAX_NVRAM_SIZE);
164         return;
165     }
166 
167     if (nvram->blk) {
168         int alen = blk_pread(nvram->blk, 0, nvram->buf, nvram->size);
169 
170         if (alen != nvram->size) {
171             error_setg(errp, "can't read spapr-nvram contents");
172             return;
173         }
174     } else if (nb_prom_envs > 0) {
175         /* Create a system partition to pass the -prom-env variables */
176         chrp_nvram_create_system_partition(nvram->buf, MIN_NVRAM_SIZE / 4);
177         chrp_nvram_create_free_partition(&nvram->buf[MIN_NVRAM_SIZE / 4],
178                                          nvram->size - MIN_NVRAM_SIZE / 4);
179     }
180 
181     spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch);
182     spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store);
183 }
184 
185 static int spapr_nvram_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
186 {
187     sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
188 
189     return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size);
190 }
191 
192 static int spapr_nvram_pre_load(void *opaque)
193 {
194     sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque);
195 
196     g_free(nvram->buf);
197     nvram->buf = NULL;
198     nvram->size = 0;
199 
200     return 0;
201 }
202 
203 static void postload_update_cb(void *opaque, int running, RunState state)
204 {
205     sPAPRNVRAM *nvram = opaque;
206 
207     /* This is called after bdrv_invalidate_cache_all.  */
208 
209     qemu_del_vm_change_state_handler(nvram->vmstate);
210     nvram->vmstate = NULL;
211 
212     blk_pwrite(nvram->blk, 0, nvram->buf, nvram->size, 0);
213 }
214 
215 static int spapr_nvram_post_load(void *opaque, int version_id)
216 {
217     sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque);
218 
219     if (nvram->blk) {
220         nvram->vmstate = qemu_add_vm_change_state_handler(postload_update_cb,
221                                                           nvram);
222     }
223 
224     return 0;
225 }
226 
227 static const VMStateDescription vmstate_spapr_nvram = {
228     .name = "spapr_nvram",
229     .version_id = 1,
230     .minimum_version_id = 1,
231     .pre_load = spapr_nvram_pre_load,
232     .post_load = spapr_nvram_post_load,
233     .fields = (VMStateField[]) {
234         VMSTATE_UINT32(size, sPAPRNVRAM),
235         VMSTATE_VBUFFER_ALLOC_UINT32(buf, sPAPRNVRAM, 1, NULL, size),
236         VMSTATE_END_OF_LIST()
237     },
238 };
239 
240 static Property spapr_nvram_properties[] = {
241     DEFINE_SPAPR_PROPERTIES(sPAPRNVRAM, sdev),
242     DEFINE_PROP_DRIVE("drive", sPAPRNVRAM, blk),
243     DEFINE_PROP_END_OF_LIST(),
244 };
245 
246 static void spapr_nvram_class_init(ObjectClass *klass, void *data)
247 {
248     DeviceClass *dc = DEVICE_CLASS(klass);
249     VIOsPAPRDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass);
250 
251     k->realize = spapr_nvram_realize;
252     k->devnode = spapr_nvram_devnode;
253     k->dt_name = "nvram";
254     k->dt_type = "nvram";
255     k->dt_compatible = "qemu,spapr-nvram";
256     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
257     dc->props = spapr_nvram_properties;
258     dc->vmsd = &vmstate_spapr_nvram;
259 }
260 
261 static const TypeInfo spapr_nvram_type_info = {
262     .name          = TYPE_VIO_SPAPR_NVRAM,
263     .parent        = TYPE_VIO_SPAPR_DEVICE,
264     .instance_size = sizeof(sPAPRNVRAM),
265     .class_init    = spapr_nvram_class_init,
266 };
267 
268 static void spapr_nvram_register_types(void)
269 {
270     type_register_static(&spapr_nvram_type_info);
271 }
272 
273 type_init(spapr_nvram_register_types)
274