xref: /openbmc/qemu/hw/nvram/spapr_nvram.c (revision ad30c0b0)
1 /*
2  * QEMU sPAPR NVRAM emulation
3  *
4  * Copyright (C) 2012 David Gibson, IBM Corporation.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include <libfdt.h>
26 
27 #include "sysemu/block-backend.h"
28 #include "sysemu/device_tree.h"
29 #include "hw/sysbus.h"
30 #include "hw/ppc/spapr.h"
31 #include "hw/ppc/spapr_vio.h"
32 
33 typedef struct sPAPRNVRAM {
34     VIOsPAPRDevice sdev;
35     uint32_t size;
36     uint8_t *buf;
37     BlockBackend *blk;
38 } sPAPRNVRAM;
39 
40 #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram"
41 #define VIO_SPAPR_NVRAM(obj) \
42      OBJECT_CHECK(sPAPRNVRAM, (obj), TYPE_VIO_SPAPR_NVRAM)
43 
44 #define MIN_NVRAM_SIZE 8192
45 #define DEFAULT_NVRAM_SIZE 65536
46 #define MAX_NVRAM_SIZE 1048576
47 
48 static void rtas_nvram_fetch(PowerPCCPU *cpu, sPAPRMachineState *spapr,
49                              uint32_t token, uint32_t nargs,
50                              target_ulong args,
51                              uint32_t nret, target_ulong rets)
52 {
53     sPAPRNVRAM *nvram = spapr->nvram;
54     hwaddr offset, buffer, len;
55     void *membuf;
56 
57     if ((nargs != 3) || (nret != 2)) {
58         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
59         return;
60     }
61 
62     if (!nvram) {
63         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
64         rtas_st(rets, 1, 0);
65         return;
66     }
67 
68     offset = rtas_ld(args, 0);
69     buffer = rtas_ld(args, 1);
70     len = rtas_ld(args, 2);
71 
72     if (((offset + len) < offset)
73         || ((offset + len) > nvram->size)) {
74         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
75         rtas_st(rets, 1, 0);
76         return;
77     }
78 
79     assert(nvram->buf);
80 
81     membuf = cpu_physical_memory_map(buffer, &len, 1);
82     memcpy(membuf, nvram->buf + offset, len);
83     cpu_physical_memory_unmap(membuf, len, 1, len);
84 
85     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
86     rtas_st(rets, 1, len);
87 }
88 
89 static void rtas_nvram_store(PowerPCCPU *cpu, sPAPRMachineState *spapr,
90                              uint32_t token, uint32_t nargs,
91                              target_ulong args,
92                              uint32_t nret, target_ulong rets)
93 {
94     sPAPRNVRAM *nvram = spapr->nvram;
95     hwaddr offset, buffer, len;
96     int alen;
97     void *membuf;
98 
99     if ((nargs != 3) || (nret != 2)) {
100         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
101         return;
102     }
103 
104     if (!nvram) {
105         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
106         return;
107     }
108 
109     offset = rtas_ld(args, 0);
110     buffer = rtas_ld(args, 1);
111     len = rtas_ld(args, 2);
112 
113     if (((offset + len) < offset)
114         || ((offset + len) > nvram->size)) {
115         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
116         return;
117     }
118 
119     membuf = cpu_physical_memory_map(buffer, &len, 0);
120 
121     alen = len;
122     if (nvram->blk) {
123         alen = blk_pwrite(nvram->blk, offset, membuf, len);
124     }
125 
126     assert(nvram->buf);
127     memcpy(nvram->buf + offset, membuf, len);
128 
129     cpu_physical_memory_unmap(membuf, len, 0, len);
130 
131     rtas_st(rets, 0, (alen < len) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS);
132     rtas_st(rets, 1, (alen < 0) ? 0 : alen);
133 }
134 
135 static void spapr_nvram_realize(VIOsPAPRDevice *dev, Error **errp)
136 {
137     sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
138 
139     if (nvram->blk) {
140         nvram->size = blk_getlength(nvram->blk);
141     } else {
142         nvram->size = DEFAULT_NVRAM_SIZE;
143     }
144 
145     nvram->buf = g_malloc0(nvram->size);
146 
147     if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) {
148         error_setg(errp, "spapr-nvram must be between %d and %d bytes in size",
149                    MIN_NVRAM_SIZE, MAX_NVRAM_SIZE);
150         return;
151     }
152 
153     if (nvram->blk) {
154         int alen = blk_pread(nvram->blk, 0, nvram->buf, nvram->size);
155 
156         if (alen != nvram->size) {
157             error_setg(errp, "can't read spapr-nvram contents");
158             return;
159         }
160     }
161 
162     spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch);
163     spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store);
164 }
165 
166 static int spapr_nvram_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
167 {
168     sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
169 
170     return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size);
171 }
172 
173 static int spapr_nvram_pre_load(void *opaque)
174 {
175     sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque);
176 
177     g_free(nvram->buf);
178     nvram->buf = NULL;
179     nvram->size = 0;
180 
181     return 0;
182 }
183 
184 static int spapr_nvram_post_load(void *opaque, int version_id)
185 {
186     sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque);
187 
188     if (nvram->blk) {
189         int alen = blk_pwrite(nvram->blk, 0, nvram->buf, nvram->size);
190 
191         if (alen < 0) {
192             return alen;
193         }
194         if (alen != nvram->size) {
195             return -1;
196         }
197     }
198 
199     return 0;
200 }
201 
202 static const VMStateDescription vmstate_spapr_nvram = {
203     .name = "spapr_nvram",
204     .version_id = 1,
205     .minimum_version_id = 1,
206     .pre_load = spapr_nvram_pre_load,
207     .post_load = spapr_nvram_post_load,
208     .fields = (VMStateField[]) {
209         VMSTATE_UINT32(size, sPAPRNVRAM),
210         VMSTATE_VBUFFER_ALLOC_UINT32(buf, sPAPRNVRAM, 1, NULL, 0, size),
211         VMSTATE_END_OF_LIST()
212     },
213 };
214 
215 static Property spapr_nvram_properties[] = {
216     DEFINE_SPAPR_PROPERTIES(sPAPRNVRAM, sdev),
217     DEFINE_PROP_DRIVE("drive", sPAPRNVRAM, blk),
218     DEFINE_PROP_END_OF_LIST(),
219 };
220 
221 static void spapr_nvram_class_init(ObjectClass *klass, void *data)
222 {
223     DeviceClass *dc = DEVICE_CLASS(klass);
224     VIOsPAPRDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass);
225 
226     k->realize = spapr_nvram_realize;
227     k->devnode = spapr_nvram_devnode;
228     k->dt_name = "nvram";
229     k->dt_type = "nvram";
230     k->dt_compatible = "qemu,spapr-nvram";
231     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
232     dc->props = spapr_nvram_properties;
233     dc->vmsd = &vmstate_spapr_nvram;
234 }
235 
236 static const TypeInfo spapr_nvram_type_info = {
237     .name          = TYPE_VIO_SPAPR_NVRAM,
238     .parent        = TYPE_VIO_SPAPR_DEVICE,
239     .instance_size = sizeof(sPAPRNVRAM),
240     .class_init    = spapr_nvram_class_init,
241 };
242 
243 static void spapr_nvram_register_types(void)
244 {
245     type_register_static(&spapr_nvram_type_info);
246 }
247 
248 type_init(spapr_nvram_register_types)
249