1 /* 2 * QEMU sPAPR NVRAM emulation 3 * 4 * Copyright (C) 2012 David Gibson, IBM Corporation. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/module.h" 27 #include "qemu/units.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #include <libfdt.h> 31 32 #include "sysemu/block-backend.h" 33 #include "sysemu/device_tree.h" 34 #include "hw/sysbus.h" 35 #include "migration/vmstate.h" 36 #include "hw/nvram/chrp_nvram.h" 37 #include "hw/ppc/spapr.h" 38 #include "hw/ppc/spapr_vio.h" 39 40 typedef struct SpaprNvram { 41 SpaprVioDevice sdev; 42 uint32_t size; 43 uint8_t *buf; 44 BlockBackend *blk; 45 VMChangeStateEntry *vmstate; 46 } SpaprNvram; 47 48 #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram" 49 #define VIO_SPAPR_NVRAM(obj) \ 50 OBJECT_CHECK(SpaprNvram, (obj), TYPE_VIO_SPAPR_NVRAM) 51 52 #define MIN_NVRAM_SIZE (8 * KiB) 53 #define DEFAULT_NVRAM_SIZE (64 * KiB) 54 #define MAX_NVRAM_SIZE (1 * MiB) 55 56 static void rtas_nvram_fetch(PowerPCCPU *cpu, SpaprMachineState *spapr, 57 uint32_t token, uint32_t nargs, 58 target_ulong args, 59 uint32_t nret, target_ulong rets) 60 { 61 SpaprNvram *nvram = spapr->nvram; 62 hwaddr offset, buffer, len; 63 void *membuf; 64 65 if ((nargs != 3) || (nret != 2)) { 66 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 67 return; 68 } 69 70 if (!nvram) { 71 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 72 rtas_st(rets, 1, 0); 73 return; 74 } 75 76 offset = rtas_ld(args, 0); 77 buffer = rtas_ld(args, 1); 78 len = rtas_ld(args, 2); 79 80 if (((offset + len) < offset) 81 || ((offset + len) > nvram->size)) { 82 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 83 rtas_st(rets, 1, 0); 84 return; 85 } 86 87 assert(nvram->buf); 88 89 membuf = cpu_physical_memory_map(buffer, &len, 1); 90 memcpy(membuf, nvram->buf + offset, len); 91 cpu_physical_memory_unmap(membuf, len, 1, len); 92 93 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 94 rtas_st(rets, 1, len); 95 } 96 97 static void rtas_nvram_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 98 uint32_t token, uint32_t nargs, 99 target_ulong args, 100 uint32_t nret, target_ulong rets) 101 { 102 SpaprNvram *nvram = spapr->nvram; 103 hwaddr offset, buffer, len; 104 int alen; 105 void *membuf; 106 107 if ((nargs != 3) || (nret != 2)) { 108 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 109 return; 110 } 111 112 if (!nvram) { 113 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 114 return; 115 } 116 117 offset = rtas_ld(args, 0); 118 buffer = rtas_ld(args, 1); 119 len = rtas_ld(args, 2); 120 121 if (((offset + len) < offset) 122 || ((offset + len) > nvram->size)) { 123 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 124 return; 125 } 126 127 membuf = cpu_physical_memory_map(buffer, &len, 0); 128 129 alen = len; 130 if (nvram->blk) { 131 alen = blk_pwrite(nvram->blk, offset, membuf, len, 0); 132 } 133 134 assert(nvram->buf); 135 memcpy(nvram->buf + offset, membuf, len); 136 137 cpu_physical_memory_unmap(membuf, len, 0, len); 138 139 rtas_st(rets, 0, (alen < len) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS); 140 rtas_st(rets, 1, (alen < 0) ? 0 : alen); 141 } 142 143 static void spapr_nvram_realize(SpaprVioDevice *dev, Error **errp) 144 { 145 SpaprNvram *nvram = VIO_SPAPR_NVRAM(dev); 146 int ret; 147 148 if (nvram->blk) { 149 int64_t len = blk_getlength(nvram->blk); 150 151 if (len < 0) { 152 error_setg_errno(errp, -len, 153 "could not get length of backing image"); 154 return; 155 } 156 157 nvram->size = len; 158 159 ret = blk_set_perm(nvram->blk, 160 BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 161 BLK_PERM_ALL, errp); 162 if (ret < 0) { 163 return; 164 } 165 } else { 166 nvram->size = DEFAULT_NVRAM_SIZE; 167 } 168 169 nvram->buf = g_malloc0(nvram->size); 170 171 if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) { 172 error_setg(errp, 173 "spapr-nvram must be between %" PRId64 174 " and %" PRId64 " bytes in size", 175 MIN_NVRAM_SIZE, MAX_NVRAM_SIZE); 176 return; 177 } 178 179 if (nvram->blk) { 180 int alen = blk_pread(nvram->blk, 0, nvram->buf, nvram->size); 181 182 if (alen != nvram->size) { 183 error_setg(errp, "can't read spapr-nvram contents"); 184 return; 185 } 186 } else if (nb_prom_envs > 0) { 187 /* Create a system partition to pass the -prom-env variables */ 188 chrp_nvram_create_system_partition(nvram->buf, MIN_NVRAM_SIZE / 4); 189 chrp_nvram_create_free_partition(&nvram->buf[MIN_NVRAM_SIZE / 4], 190 nvram->size - MIN_NVRAM_SIZE / 4); 191 } 192 193 spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch); 194 spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store); 195 } 196 197 static int spapr_nvram_devnode(SpaprVioDevice *dev, void *fdt, int node_off) 198 { 199 SpaprNvram *nvram = VIO_SPAPR_NVRAM(dev); 200 201 return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size); 202 } 203 204 static int spapr_nvram_pre_load(void *opaque) 205 { 206 SpaprNvram *nvram = VIO_SPAPR_NVRAM(opaque); 207 208 g_free(nvram->buf); 209 nvram->buf = NULL; 210 nvram->size = 0; 211 212 return 0; 213 } 214 215 static void postload_update_cb(void *opaque, int running, RunState state) 216 { 217 SpaprNvram *nvram = opaque; 218 219 /* This is called after bdrv_invalidate_cache_all. */ 220 221 qemu_del_vm_change_state_handler(nvram->vmstate); 222 nvram->vmstate = NULL; 223 224 blk_pwrite(nvram->blk, 0, nvram->buf, nvram->size, 0); 225 } 226 227 static int spapr_nvram_post_load(void *opaque, int version_id) 228 { 229 SpaprNvram *nvram = VIO_SPAPR_NVRAM(opaque); 230 231 if (nvram->blk) { 232 nvram->vmstate = qemu_add_vm_change_state_handler(postload_update_cb, 233 nvram); 234 } 235 236 return 0; 237 } 238 239 static const VMStateDescription vmstate_spapr_nvram = { 240 .name = "spapr_nvram", 241 .version_id = 1, 242 .minimum_version_id = 1, 243 .pre_load = spapr_nvram_pre_load, 244 .post_load = spapr_nvram_post_load, 245 .fields = (VMStateField[]) { 246 VMSTATE_UINT32(size, SpaprNvram), 247 VMSTATE_VBUFFER_ALLOC_UINT32(buf, SpaprNvram, 1, NULL, size), 248 VMSTATE_END_OF_LIST() 249 }, 250 }; 251 252 static Property spapr_nvram_properties[] = { 253 DEFINE_SPAPR_PROPERTIES(SpaprNvram, sdev), 254 DEFINE_PROP_DRIVE("drive", SpaprNvram, blk), 255 DEFINE_PROP_END_OF_LIST(), 256 }; 257 258 static void spapr_nvram_class_init(ObjectClass *klass, void *data) 259 { 260 DeviceClass *dc = DEVICE_CLASS(klass); 261 SpaprVioDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass); 262 263 k->realize = spapr_nvram_realize; 264 k->devnode = spapr_nvram_devnode; 265 k->dt_name = "nvram"; 266 k->dt_type = "nvram"; 267 k->dt_compatible = "qemu,spapr-nvram"; 268 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 269 dc->props = spapr_nvram_properties; 270 dc->vmsd = &vmstate_spapr_nvram; 271 /* Reason: Internal device only, uses spapr_rtas_register() in realize() */ 272 dc->user_creatable = false; 273 } 274 275 static const TypeInfo spapr_nvram_type_info = { 276 .name = TYPE_VIO_SPAPR_NVRAM, 277 .parent = TYPE_VIO_SPAPR_DEVICE, 278 .instance_size = sizeof(SpaprNvram), 279 .class_init = spapr_nvram_class_init, 280 }; 281 282 static void spapr_nvram_register_types(void) 283 { 284 type_register_static(&spapr_nvram_type_info); 285 } 286 287 type_init(spapr_nvram_register_types) 288