1 /* 2 * QEMU Firmware configuration device emulation 3 * 4 * Copyright (c) 2008 Gleb Natapov 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/datadir.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/dma.h" 29 #include "sysemu/reset.h" 30 #include "hw/boards.h" 31 #include "hw/nvram/fw_cfg.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/sysbus.h" 34 #include "migration/qemu-file-types.h" 35 #include "migration/vmstate.h" 36 #include "trace.h" 37 #include "qemu/error-report.h" 38 #include "qemu/option.h" 39 #include "qemu/config-file.h" 40 #include "qemu/cutils.h" 41 #include "qapi/error.h" 42 #include "hw/acpi/aml-build.h" 43 #include "hw/pci/pci_bus.h" 44 45 #define FW_CFG_FILE_SLOTS_DFLT 0x20 46 47 /* FW_CFG_VERSION bits */ 48 #define FW_CFG_VERSION 0x01 49 #define FW_CFG_VERSION_DMA 0x02 50 51 /* FW_CFG_DMA_CONTROL bits */ 52 #define FW_CFG_DMA_CTL_ERROR 0x01 53 #define FW_CFG_DMA_CTL_READ 0x02 54 #define FW_CFG_DMA_CTL_SKIP 0x04 55 #define FW_CFG_DMA_CTL_SELECT 0x08 56 #define FW_CFG_DMA_CTL_WRITE 0x10 57 58 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */ 59 60 struct FWCfgEntry { 61 uint32_t len; 62 bool allow_write; 63 uint8_t *data; 64 void *callback_opaque; 65 FWCfgCallback select_cb; 66 FWCfgWriteCallback write_cb; 67 }; 68 69 /** 70 * key_name: 71 * 72 * @key: The uint16 selector key. 73 * 74 * Returns: The stringified name if the selector refers to a well-known 75 * numerically defined item, or NULL on key lookup failure. 76 */ 77 static const char *key_name(uint16_t key) 78 { 79 static const char *fw_cfg_wellknown_keys[FW_CFG_FILE_FIRST] = { 80 [FW_CFG_SIGNATURE] = "signature", 81 [FW_CFG_ID] = "id", 82 [FW_CFG_UUID] = "uuid", 83 [FW_CFG_RAM_SIZE] = "ram_size", 84 [FW_CFG_NOGRAPHIC] = "nographic", 85 [FW_CFG_NB_CPUS] = "nb_cpus", 86 [FW_CFG_MACHINE_ID] = "machine_id", 87 [FW_CFG_KERNEL_ADDR] = "kernel_addr", 88 [FW_CFG_KERNEL_SIZE] = "kernel_size", 89 [FW_CFG_KERNEL_CMDLINE] = "kernel_cmdline", 90 [FW_CFG_INITRD_ADDR] = "initrd_addr", 91 [FW_CFG_INITRD_SIZE] = "initdr_size", 92 [FW_CFG_BOOT_DEVICE] = "boot_device", 93 [FW_CFG_NUMA] = "numa", 94 [FW_CFG_BOOT_MENU] = "boot_menu", 95 [FW_CFG_MAX_CPUS] = "max_cpus", 96 [FW_CFG_KERNEL_ENTRY] = "kernel_entry", 97 [FW_CFG_KERNEL_DATA] = "kernel_data", 98 [FW_CFG_INITRD_DATA] = "initrd_data", 99 [FW_CFG_CMDLINE_ADDR] = "cmdline_addr", 100 [FW_CFG_CMDLINE_SIZE] = "cmdline_size", 101 [FW_CFG_CMDLINE_DATA] = "cmdline_data", 102 [FW_CFG_SETUP_ADDR] = "setup_addr", 103 [FW_CFG_SETUP_SIZE] = "setup_size", 104 [FW_CFG_SETUP_DATA] = "setup_data", 105 [FW_CFG_FILE_DIR] = "file_dir", 106 }; 107 108 if (key & FW_CFG_ARCH_LOCAL) { 109 return fw_cfg_arch_key_name(key); 110 } 111 if (key < FW_CFG_FILE_FIRST) { 112 return fw_cfg_wellknown_keys[key]; 113 } 114 115 return NULL; 116 } 117 118 static inline const char *trace_key_name(uint16_t key) 119 { 120 const char *name = key_name(key); 121 122 return name ? name : "unknown"; 123 } 124 125 #define JPG_FILE 0 126 #define BMP_FILE 1 127 128 static char *read_splashfile(char *filename, gsize *file_sizep, 129 int *file_typep) 130 { 131 GError *err = NULL; 132 gchar *content; 133 int file_type; 134 unsigned int filehead; 135 int bmp_bpp; 136 137 if (!g_file_get_contents(filename, &content, file_sizep, &err)) { 138 error_report("failed to read splash file '%s': %s", 139 filename, err->message); 140 g_error_free(err); 141 return NULL; 142 } 143 144 /* check file size */ 145 if (*file_sizep < 30) { 146 goto error; 147 } 148 149 /* check magic ID */ 150 filehead = lduw_le_p(content); 151 if (filehead == 0xd8ff) { 152 file_type = JPG_FILE; 153 } else if (filehead == 0x4d42) { 154 file_type = BMP_FILE; 155 } else { 156 goto error; 157 } 158 159 /* check BMP bpp */ 160 if (file_type == BMP_FILE) { 161 bmp_bpp = lduw_le_p(&content[28]); 162 if (bmp_bpp != 24) { 163 goto error; 164 } 165 } 166 167 /* return values */ 168 *file_typep = file_type; 169 170 return content; 171 172 error: 173 error_report("splash file '%s' format not recognized; must be JPEG " 174 "or 24 bit BMP", filename); 175 g_free(content); 176 return NULL; 177 } 178 179 static void fw_cfg_bootsplash(FWCfgState *s) 180 { 181 const char *boot_splash_filename = NULL; 182 const char *boot_splash_time = NULL; 183 char *filename, *file_data; 184 gsize file_size; 185 int file_type; 186 187 /* get user configuration */ 188 QemuOptsList *plist = qemu_find_opts("boot-opts"); 189 QemuOpts *opts = QTAILQ_FIRST(&plist->head); 190 boot_splash_filename = qemu_opt_get(opts, "splash"); 191 boot_splash_time = qemu_opt_get(opts, "splash-time"); 192 193 /* insert splash time if user configurated */ 194 if (boot_splash_time) { 195 int64_t bst_val = qemu_opt_get_number(opts, "splash-time", -1); 196 uint16_t bst_le16; 197 198 /* validate the input */ 199 if (bst_val < 0 || bst_val > 0xffff) { 200 error_report("splash-time is invalid," 201 "it should be a value between 0 and 65535"); 202 exit(1); 203 } 204 /* use little endian format */ 205 bst_le16 = cpu_to_le16(bst_val); 206 fw_cfg_add_file(s, "etc/boot-menu-wait", 207 g_memdup(&bst_le16, sizeof bst_le16), sizeof bst_le16); 208 } 209 210 /* insert splash file if user configurated */ 211 if (boot_splash_filename) { 212 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename); 213 if (filename == NULL) { 214 error_report("failed to find file '%s'", boot_splash_filename); 215 return; 216 } 217 218 /* loading file data */ 219 file_data = read_splashfile(filename, &file_size, &file_type); 220 if (file_data == NULL) { 221 g_free(filename); 222 return; 223 } 224 g_free(boot_splash_filedata); 225 boot_splash_filedata = (uint8_t *)file_data; 226 227 /* insert data */ 228 if (file_type == JPG_FILE) { 229 fw_cfg_add_file(s, "bootsplash.jpg", 230 boot_splash_filedata, file_size); 231 } else { 232 fw_cfg_add_file(s, "bootsplash.bmp", 233 boot_splash_filedata, file_size); 234 } 235 g_free(filename); 236 } 237 } 238 239 static void fw_cfg_reboot(FWCfgState *s) 240 { 241 const char *reboot_timeout = NULL; 242 uint64_t rt_val = -1; 243 uint32_t rt_le32; 244 245 /* get user configuration */ 246 QemuOptsList *plist = qemu_find_opts("boot-opts"); 247 QemuOpts *opts = QTAILQ_FIRST(&plist->head); 248 reboot_timeout = qemu_opt_get(opts, "reboot-timeout"); 249 250 if (reboot_timeout) { 251 rt_val = qemu_opt_get_number(opts, "reboot-timeout", -1); 252 253 /* validate the input */ 254 if (rt_val > 0xffff && rt_val != (uint64_t)-1) { 255 error_report("reboot timeout is invalid," 256 "it should be a value between -1 and 65535"); 257 exit(1); 258 } 259 } 260 261 rt_le32 = cpu_to_le32(rt_val); 262 fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&rt_le32, 4), 4); 263 } 264 265 static void fw_cfg_write(FWCfgState *s, uint8_t value) 266 { 267 /* nothing, write support removed in QEMU v2.4+ */ 268 } 269 270 static inline uint16_t fw_cfg_file_slots(const FWCfgState *s) 271 { 272 return s->file_slots; 273 } 274 275 /* Note: this function returns an exclusive limit. */ 276 static inline uint32_t fw_cfg_max_entry(const FWCfgState *s) 277 { 278 return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s); 279 } 280 281 static int fw_cfg_select(FWCfgState *s, uint16_t key) 282 { 283 int arch, ret; 284 FWCfgEntry *e; 285 286 s->cur_offset = 0; 287 if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) { 288 s->cur_entry = FW_CFG_INVALID; 289 ret = 0; 290 } else { 291 s->cur_entry = key; 292 ret = 1; 293 /* entry successfully selected, now run callback if present */ 294 arch = !!(key & FW_CFG_ARCH_LOCAL); 295 e = &s->entries[arch][key & FW_CFG_ENTRY_MASK]; 296 if (e->select_cb) { 297 e->select_cb(e->callback_opaque); 298 } 299 } 300 301 trace_fw_cfg_select(s, key, trace_key_name(key), ret); 302 return ret; 303 } 304 305 static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size) 306 { 307 FWCfgState *s = opaque; 308 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); 309 FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL : 310 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; 311 uint64_t value = 0; 312 313 assert(size > 0 && size <= sizeof(value)); 314 if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) { 315 /* The least significant 'size' bytes of the return value are 316 * expected to contain a string preserving portion of the item 317 * data, padded with zeros on the right in case we run out early. 318 * In technical terms, we're composing the host-endian representation 319 * of the big endian interpretation of the fw_cfg string. 320 */ 321 do { 322 value = (value << 8) | e->data[s->cur_offset++]; 323 } while (--size && s->cur_offset < e->len); 324 /* If size is still not zero, we *did* run out early, so continue 325 * left-shifting, to add the appropriate number of padding zeros 326 * on the right. 327 */ 328 value <<= 8 * size; 329 } 330 331 trace_fw_cfg_read(s, value); 332 return value; 333 } 334 335 static void fw_cfg_data_mem_write(void *opaque, hwaddr addr, 336 uint64_t value, unsigned size) 337 { 338 FWCfgState *s = opaque; 339 unsigned i = size; 340 341 do { 342 fw_cfg_write(s, value >> (8 * --i)); 343 } while (i); 344 } 345 346 static void fw_cfg_dma_transfer(FWCfgState *s) 347 { 348 dma_addr_t len; 349 FWCfgDmaAccess dma; 350 int arch; 351 FWCfgEntry *e; 352 int read = 0, write = 0; 353 dma_addr_t dma_addr; 354 355 /* Reset the address before the next access */ 356 dma_addr = s->dma_addr; 357 s->dma_addr = 0; 358 359 if (dma_memory_read(s->dma_as, dma_addr, 360 &dma, sizeof(dma), MEMTXATTRS_UNSPECIFIED)) { 361 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), 362 FW_CFG_DMA_CTL_ERROR, MEMTXATTRS_UNSPECIFIED); 363 return; 364 } 365 366 dma.address = be64_to_cpu(dma.address); 367 dma.length = be32_to_cpu(dma.length); 368 dma.control = be32_to_cpu(dma.control); 369 370 if (dma.control & FW_CFG_DMA_CTL_SELECT) { 371 fw_cfg_select(s, dma.control >> 16); 372 } 373 374 arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); 375 e = (s->cur_entry == FW_CFG_INVALID) ? NULL : 376 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; 377 378 if (dma.control & FW_CFG_DMA_CTL_READ) { 379 read = 1; 380 write = 0; 381 } else if (dma.control & FW_CFG_DMA_CTL_WRITE) { 382 read = 0; 383 write = 1; 384 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) { 385 read = 0; 386 write = 0; 387 } else { 388 dma.length = 0; 389 } 390 391 dma.control = 0; 392 393 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) { 394 if (s->cur_entry == FW_CFG_INVALID || !e->data || 395 s->cur_offset >= e->len) { 396 len = dma.length; 397 398 /* If the access is not a read access, it will be a skip access, 399 * tested before. 400 */ 401 if (read) { 402 if (dma_memory_set(s->dma_as, dma.address, 0, len, 403 MEMTXATTRS_UNSPECIFIED)) { 404 dma.control |= FW_CFG_DMA_CTL_ERROR; 405 } 406 } 407 if (write) { 408 dma.control |= FW_CFG_DMA_CTL_ERROR; 409 } 410 } else { 411 if (dma.length <= (e->len - s->cur_offset)) { 412 len = dma.length; 413 } else { 414 len = (e->len - s->cur_offset); 415 } 416 417 /* If the access is not a read access, it will be a skip access, 418 * tested before. 419 */ 420 if (read) { 421 if (dma_memory_write(s->dma_as, dma.address, 422 &e->data[s->cur_offset], len, 423 MEMTXATTRS_UNSPECIFIED)) { 424 dma.control |= FW_CFG_DMA_CTL_ERROR; 425 } 426 } 427 if (write) { 428 if (!e->allow_write || 429 len != dma.length || 430 dma_memory_read(s->dma_as, dma.address, 431 &e->data[s->cur_offset], len, 432 MEMTXATTRS_UNSPECIFIED)) { 433 dma.control |= FW_CFG_DMA_CTL_ERROR; 434 } else if (e->write_cb) { 435 e->write_cb(e->callback_opaque, s->cur_offset, len); 436 } 437 } 438 439 s->cur_offset += len; 440 } 441 442 dma.address += len; 443 dma.length -= len; 444 445 } 446 447 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), 448 dma.control, MEMTXATTRS_UNSPECIFIED); 449 450 trace_fw_cfg_read(s, 0); 451 } 452 453 static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr, 454 unsigned size) 455 { 456 /* Return a signature value (and handle various read sizes) */ 457 return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8); 458 } 459 460 static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr, 461 uint64_t value, unsigned size) 462 { 463 FWCfgState *s = opaque; 464 465 if (size == 4) { 466 if (addr == 0) { 467 /* FWCfgDmaAccess high address */ 468 s->dma_addr = value << 32; 469 } else if (addr == 4) { 470 /* FWCfgDmaAccess low address */ 471 s->dma_addr |= value; 472 fw_cfg_dma_transfer(s); 473 } 474 } else if (size == 8 && addr == 0) { 475 s->dma_addr = value; 476 fw_cfg_dma_transfer(s); 477 } 478 } 479 480 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr, 481 unsigned size, bool is_write, 482 MemTxAttrs attrs) 483 { 484 return !is_write || ((size == 4 && (addr == 0 || addr == 4)) || 485 (size == 8 && addr == 0)); 486 } 487 488 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr, 489 unsigned size, bool is_write, 490 MemTxAttrs attrs) 491 { 492 return addr == 0; 493 } 494 495 static uint64_t fw_cfg_ctl_mem_read(void *opaque, hwaddr addr, unsigned size) 496 { 497 return 0; 498 } 499 500 static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr, 501 uint64_t value, unsigned size) 502 { 503 fw_cfg_select(opaque, (uint16_t)value); 504 } 505 506 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr, 507 unsigned size, bool is_write, 508 MemTxAttrs attrs) 509 { 510 return is_write && size == 2; 511 } 512 513 static void fw_cfg_comb_write(void *opaque, hwaddr addr, 514 uint64_t value, unsigned size) 515 { 516 switch (size) { 517 case 1: 518 fw_cfg_write(opaque, (uint8_t)value); 519 break; 520 case 2: 521 fw_cfg_select(opaque, (uint16_t)value); 522 break; 523 } 524 } 525 526 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr, 527 unsigned size, bool is_write, 528 MemTxAttrs attrs) 529 { 530 return (size == 1) || (is_write && size == 2); 531 } 532 533 static const MemoryRegionOps fw_cfg_ctl_mem_ops = { 534 .read = fw_cfg_ctl_mem_read, 535 .write = fw_cfg_ctl_mem_write, 536 .endianness = DEVICE_BIG_ENDIAN, 537 .valid.accepts = fw_cfg_ctl_mem_valid, 538 }; 539 540 static const MemoryRegionOps fw_cfg_data_mem_ops = { 541 .read = fw_cfg_data_read, 542 .write = fw_cfg_data_mem_write, 543 .endianness = DEVICE_BIG_ENDIAN, 544 .valid = { 545 .min_access_size = 1, 546 .max_access_size = 1, 547 .accepts = fw_cfg_data_mem_valid, 548 }, 549 }; 550 551 static const MemoryRegionOps fw_cfg_comb_mem_ops = { 552 .read = fw_cfg_data_read, 553 .write = fw_cfg_comb_write, 554 .endianness = DEVICE_LITTLE_ENDIAN, 555 .valid.accepts = fw_cfg_comb_valid, 556 }; 557 558 static const MemoryRegionOps fw_cfg_dma_mem_ops = { 559 .read = fw_cfg_dma_mem_read, 560 .write = fw_cfg_dma_mem_write, 561 .endianness = DEVICE_BIG_ENDIAN, 562 .valid.accepts = fw_cfg_dma_mem_valid, 563 .valid.max_access_size = 8, 564 .impl.max_access_size = 8, 565 }; 566 567 static void fw_cfg_reset(DeviceState *d) 568 { 569 FWCfgState *s = FW_CFG(d); 570 571 /* we never register a read callback for FW_CFG_SIGNATURE */ 572 fw_cfg_select(s, FW_CFG_SIGNATURE); 573 } 574 575 /* Save restore 32 bit int as uint16_t 576 This is a Big hack, but it is how the old state did it. 577 Or we broke compatibility in the state, or we can't use struct tm 578 */ 579 580 static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size, 581 const VMStateField *field) 582 { 583 uint32_t *v = pv; 584 *v = qemu_get_be16(f); 585 return 0; 586 } 587 588 static int put_unused(QEMUFile *f, void *pv, size_t size, 589 const VMStateField *field, JSONWriter *vmdesc) 590 { 591 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n"); 592 fprintf(stderr, "This functions shouldn't be called.\n"); 593 594 return 0; 595 } 596 597 static const VMStateInfo vmstate_hack_uint32_as_uint16 = { 598 .name = "int32_as_uint16", 599 .get = get_uint32_as_uint16, 600 .put = put_unused, 601 }; 602 603 #define VMSTATE_UINT16_HACK(_f, _s, _t) \ 604 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t) 605 606 607 static bool is_version_1(void *opaque, int version_id) 608 { 609 return version_id == 1; 610 } 611 612 bool fw_cfg_dma_enabled(void *opaque) 613 { 614 FWCfgState *s = opaque; 615 616 return s->dma_enabled; 617 } 618 619 static bool fw_cfg_acpi_mr_restore(void *opaque) 620 { 621 FWCfgState *s = opaque; 622 bool mr_aligned; 623 624 mr_aligned = QEMU_IS_ALIGNED(s->table_mr_size, qemu_real_host_page_size()) && 625 QEMU_IS_ALIGNED(s->linker_mr_size, qemu_real_host_page_size()) && 626 QEMU_IS_ALIGNED(s->rsdp_mr_size, qemu_real_host_page_size()); 627 return s->acpi_mr_restore && !mr_aligned; 628 } 629 630 static void fw_cfg_update_mr(FWCfgState *s, uint16_t key, size_t size) 631 { 632 MemoryRegion *mr; 633 ram_addr_t offset; 634 int arch = !!(key & FW_CFG_ARCH_LOCAL); 635 void *ptr; 636 637 key &= FW_CFG_ENTRY_MASK; 638 assert(key < fw_cfg_max_entry(s)); 639 640 ptr = s->entries[arch][key].data; 641 mr = memory_region_from_host(ptr, &offset); 642 643 memory_region_ram_resize(mr, size, &error_abort); 644 } 645 646 static int fw_cfg_acpi_mr_restore_post_load(void *opaque, int version_id) 647 { 648 FWCfgState *s = opaque; 649 int i, index; 650 651 assert(s->files); 652 653 index = be32_to_cpu(s->files->count); 654 655 for (i = 0; i < index; i++) { 656 if (!strcmp(s->files->f[i].name, ACPI_BUILD_TABLE_FILE)) { 657 fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->table_mr_size); 658 } else if (!strcmp(s->files->f[i].name, ACPI_BUILD_LOADER_FILE)) { 659 fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->linker_mr_size); 660 } else if (!strcmp(s->files->f[i].name, ACPI_BUILD_RSDP_FILE)) { 661 fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->rsdp_mr_size); 662 } 663 } 664 665 return 0; 666 } 667 668 static const VMStateDescription vmstate_fw_cfg_dma = { 669 .name = "fw_cfg/dma", 670 .needed = fw_cfg_dma_enabled, 671 .fields = (VMStateField[]) { 672 VMSTATE_UINT64(dma_addr, FWCfgState), 673 VMSTATE_END_OF_LIST() 674 }, 675 }; 676 677 static const VMStateDescription vmstate_fw_cfg_acpi_mr = { 678 .name = "fw_cfg/acpi_mr", 679 .version_id = 1, 680 .minimum_version_id = 1, 681 .needed = fw_cfg_acpi_mr_restore, 682 .post_load = fw_cfg_acpi_mr_restore_post_load, 683 .fields = (VMStateField[]) { 684 VMSTATE_UINT64(table_mr_size, FWCfgState), 685 VMSTATE_UINT64(linker_mr_size, FWCfgState), 686 VMSTATE_UINT64(rsdp_mr_size, FWCfgState), 687 VMSTATE_END_OF_LIST() 688 }, 689 }; 690 691 static const VMStateDescription vmstate_fw_cfg = { 692 .name = "fw_cfg", 693 .version_id = 2, 694 .minimum_version_id = 1, 695 .fields = (VMStateField[]) { 696 VMSTATE_UINT16(cur_entry, FWCfgState), 697 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1), 698 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2), 699 VMSTATE_END_OF_LIST() 700 }, 701 .subsections = (const VMStateDescription*[]) { 702 &vmstate_fw_cfg_dma, 703 &vmstate_fw_cfg_acpi_mr, 704 NULL, 705 } 706 }; 707 708 static void fw_cfg_add_bytes_callback(FWCfgState *s, uint16_t key, 709 FWCfgCallback select_cb, 710 FWCfgWriteCallback write_cb, 711 void *callback_opaque, 712 void *data, size_t len, 713 bool read_only) 714 { 715 int arch = !!(key & FW_CFG_ARCH_LOCAL); 716 717 key &= FW_CFG_ENTRY_MASK; 718 719 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX); 720 assert(s->entries[arch][key].data == NULL); /* avoid key conflict */ 721 722 s->entries[arch][key].data = data; 723 s->entries[arch][key].len = (uint32_t)len; 724 s->entries[arch][key].select_cb = select_cb; 725 s->entries[arch][key].write_cb = write_cb; 726 s->entries[arch][key].callback_opaque = callback_opaque; 727 s->entries[arch][key].allow_write = !read_only; 728 } 729 730 static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key, 731 void *data, size_t len) 732 { 733 void *ptr; 734 int arch = !!(key & FW_CFG_ARCH_LOCAL); 735 736 key &= FW_CFG_ENTRY_MASK; 737 738 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX); 739 740 /* return the old data to the function caller, avoid memory leak */ 741 ptr = s->entries[arch][key].data; 742 s->entries[arch][key].data = data; 743 s->entries[arch][key].len = len; 744 s->entries[arch][key].callback_opaque = NULL; 745 s->entries[arch][key].allow_write = false; 746 747 return ptr; 748 } 749 750 void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len) 751 { 752 trace_fw_cfg_add_bytes(key, trace_key_name(key), len); 753 fw_cfg_add_bytes_callback(s, key, NULL, NULL, NULL, data, len, true); 754 } 755 756 void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value) 757 { 758 size_t sz = strlen(value) + 1; 759 760 trace_fw_cfg_add_string(key, trace_key_name(key), value); 761 fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz); 762 } 763 764 void fw_cfg_modify_string(FWCfgState *s, uint16_t key, const char *value) 765 { 766 size_t sz = strlen(value) + 1; 767 char *old; 768 769 old = fw_cfg_modify_bytes_read(s, key, g_memdup(value, sz), sz); 770 g_free(old); 771 } 772 773 void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value) 774 { 775 uint16_t *copy; 776 777 copy = g_malloc(sizeof(value)); 778 *copy = cpu_to_le16(value); 779 trace_fw_cfg_add_i16(key, trace_key_name(key), value); 780 fw_cfg_add_bytes(s, key, copy, sizeof(value)); 781 } 782 783 void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value) 784 { 785 uint16_t *copy, *old; 786 787 copy = g_malloc(sizeof(value)); 788 *copy = cpu_to_le16(value); 789 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); 790 g_free(old); 791 } 792 793 void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value) 794 { 795 uint32_t *copy; 796 797 copy = g_malloc(sizeof(value)); 798 *copy = cpu_to_le32(value); 799 trace_fw_cfg_add_i32(key, trace_key_name(key), value); 800 fw_cfg_add_bytes(s, key, copy, sizeof(value)); 801 } 802 803 void fw_cfg_modify_i32(FWCfgState *s, uint16_t key, uint32_t value) 804 { 805 uint32_t *copy, *old; 806 807 copy = g_malloc(sizeof(value)); 808 *copy = cpu_to_le32(value); 809 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); 810 g_free(old); 811 } 812 813 void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value) 814 { 815 uint64_t *copy; 816 817 copy = g_malloc(sizeof(value)); 818 *copy = cpu_to_le64(value); 819 trace_fw_cfg_add_i64(key, trace_key_name(key), value); 820 fw_cfg_add_bytes(s, key, copy, sizeof(value)); 821 } 822 823 void fw_cfg_modify_i64(FWCfgState *s, uint16_t key, uint64_t value) 824 { 825 uint64_t *copy, *old; 826 827 copy = g_malloc(sizeof(value)); 828 *copy = cpu_to_le64(value); 829 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); 830 g_free(old); 831 } 832 833 void fw_cfg_set_order_override(FWCfgState *s, int order) 834 { 835 assert(s->fw_cfg_order_override == 0); 836 s->fw_cfg_order_override = order; 837 } 838 839 void fw_cfg_reset_order_override(FWCfgState *s) 840 { 841 assert(s->fw_cfg_order_override != 0); 842 s->fw_cfg_order_override = 0; 843 } 844 845 /* 846 * This is the legacy order list. For legacy systems, files are in 847 * the fw_cfg in the order defined below, by the "order" value. Note 848 * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a 849 * specific area, but there may be more than one and they occur in the 850 * order that the user specifies them on the command line. Those are 851 * handled in a special manner, using the order override above. 852 * 853 * For non-legacy, the files are sorted by filename to avoid this kind 854 * of complexity in the future. 855 * 856 * This is only for x86, other arches don't implement versioning so 857 * they won't set legacy mode. 858 */ 859 static struct { 860 const char *name; 861 int order; 862 } fw_cfg_order[] = { 863 { "etc/boot-menu-wait", 10 }, 864 { "bootsplash.jpg", 11 }, 865 { "bootsplash.bmp", 12 }, 866 { "etc/boot-fail-wait", 15 }, 867 { "etc/smbios/smbios-tables", 20 }, 868 { "etc/smbios/smbios-anchor", 30 }, 869 { "etc/e820", 40 }, 870 { "etc/reserved-memory-end", 50 }, 871 { "genroms/kvmvapic.bin", 55 }, 872 { "genroms/linuxboot.bin", 60 }, 873 { }, /* VGA ROMs from pc_vga_init come here, 70. */ 874 { }, /* NIC option ROMs from pc_nic_init come here, 80. */ 875 { "etc/system-states", 90 }, 876 { }, /* User ROMs come here, 100. */ 877 { }, /* Device FW comes here, 110. */ 878 { "etc/extra-pci-roots", 120 }, 879 { "etc/acpi/tables", 130 }, 880 { "etc/table-loader", 140 }, 881 { "etc/tpm/log", 150 }, 882 { "etc/acpi/rsdp", 160 }, 883 { "bootorder", 170 }, 884 { "etc/msr_feature_control", 180 }, 885 886 #define FW_CFG_ORDER_OVERRIDE_LAST 200 887 }; 888 889 /* 890 * Any sub-page size update to these table MRs will be lost during migration, 891 * as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path. 892 * In order to avoid the inconsistency in sizes save them seperately and 893 * migrate over in vmstate post_load(). 894 */ 895 static void fw_cfg_acpi_mr_save(FWCfgState *s, const char *filename, size_t len) 896 { 897 if (!strcmp(filename, ACPI_BUILD_TABLE_FILE)) { 898 s->table_mr_size = len; 899 } else if (!strcmp(filename, ACPI_BUILD_LOADER_FILE)) { 900 s->linker_mr_size = len; 901 } else if (!strcmp(filename, ACPI_BUILD_RSDP_FILE)) { 902 s->rsdp_mr_size = len; 903 } 904 } 905 906 static int get_fw_cfg_order(FWCfgState *s, const char *name) 907 { 908 int i; 909 910 if (s->fw_cfg_order_override > 0) { 911 return s->fw_cfg_order_override; 912 } 913 914 for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) { 915 if (fw_cfg_order[i].name == NULL) { 916 continue; 917 } 918 919 if (strcmp(name, fw_cfg_order[i].name) == 0) { 920 return fw_cfg_order[i].order; 921 } 922 } 923 924 /* Stick unknown stuff at the end. */ 925 warn_report("Unknown firmware file in legacy mode: %s", name); 926 return FW_CFG_ORDER_OVERRIDE_LAST; 927 } 928 929 void fw_cfg_add_file_callback(FWCfgState *s, const char *filename, 930 FWCfgCallback select_cb, 931 FWCfgWriteCallback write_cb, 932 void *callback_opaque, 933 void *data, size_t len, bool read_only) 934 { 935 int i, index, count; 936 size_t dsize; 937 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 938 int order = 0; 939 940 if (!s->files) { 941 dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s); 942 s->files = g_malloc0(dsize); 943 fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize); 944 } 945 946 count = be32_to_cpu(s->files->count); 947 assert(count < fw_cfg_file_slots(s)); 948 949 /* Find the insertion point. */ 950 if (mc->legacy_fw_cfg_order) { 951 /* 952 * Sort by order. For files with the same order, we keep them 953 * in the sequence in which they were added. 954 */ 955 order = get_fw_cfg_order(s, filename); 956 for (index = count; 957 index > 0 && order < s->entry_order[index - 1]; 958 index--); 959 } else { 960 /* Sort by file name. */ 961 for (index = count; 962 index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0; 963 index--); 964 } 965 966 /* 967 * Move all the entries from the index point and after down one 968 * to create a slot for the new entry. Because calculations are 969 * being done with the index, make it so that "i" is the current 970 * index and "i - 1" is the one being copied from, thus the 971 * unusual start and end in the for statement. 972 */ 973 for (i = count; i > index; i--) { 974 s->files->f[i] = s->files->f[i - 1]; 975 s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i); 976 s->entries[0][FW_CFG_FILE_FIRST + i] = 977 s->entries[0][FW_CFG_FILE_FIRST + i - 1]; 978 s->entry_order[i] = s->entry_order[i - 1]; 979 } 980 981 memset(&s->files->f[index], 0, sizeof(FWCfgFile)); 982 memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry)); 983 984 pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename); 985 for (i = 0; i <= count; i++) { 986 if (i != index && 987 strcmp(s->files->f[index].name, s->files->f[i].name) == 0) { 988 error_report("duplicate fw_cfg file name: %s", 989 s->files->f[index].name); 990 exit(1); 991 } 992 } 993 994 fw_cfg_add_bytes_callback(s, FW_CFG_FILE_FIRST + index, 995 select_cb, write_cb, 996 callback_opaque, data, len, 997 read_only); 998 999 s->files->f[index].size = cpu_to_be32(len); 1000 s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index); 1001 s->entry_order[index] = order; 1002 trace_fw_cfg_add_file(s, index, s->files->f[index].name, len); 1003 1004 s->files->count = cpu_to_be32(count+1); 1005 fw_cfg_acpi_mr_save(s, filename, len); 1006 } 1007 1008 void fw_cfg_add_file(FWCfgState *s, const char *filename, 1009 void *data, size_t len) 1010 { 1011 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true); 1012 } 1013 1014 void *fw_cfg_modify_file(FWCfgState *s, const char *filename, 1015 void *data, size_t len) 1016 { 1017 int i, index; 1018 void *ptr = NULL; 1019 1020 assert(s->files); 1021 1022 index = be32_to_cpu(s->files->count); 1023 1024 for (i = 0; i < index; i++) { 1025 if (strcmp(filename, s->files->f[i].name) == 0) { 1026 ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i, 1027 data, len); 1028 s->files->f[i].size = cpu_to_be32(len); 1029 fw_cfg_acpi_mr_save(s, filename, len); 1030 return ptr; 1031 } 1032 } 1033 1034 assert(index < fw_cfg_file_slots(s)); 1035 1036 /* add new one */ 1037 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true); 1038 return NULL; 1039 } 1040 1041 bool fw_cfg_add_from_generator(FWCfgState *s, const char *filename, 1042 const char *gen_id, Error **errp) 1043 { 1044 FWCfgDataGeneratorClass *klass; 1045 GByteArray *array; 1046 Object *obj; 1047 gsize size; 1048 1049 obj = object_resolve_path_component(object_get_objects_root(), gen_id); 1050 if (!obj) { 1051 error_setg(errp, "Cannot find object ID '%s'", gen_id); 1052 return false; 1053 } 1054 if (!object_dynamic_cast(obj, TYPE_FW_CFG_DATA_GENERATOR_INTERFACE)) { 1055 error_setg(errp, "Object ID '%s' is not a '%s' subclass", 1056 gen_id, TYPE_FW_CFG_DATA_GENERATOR_INTERFACE); 1057 return false; 1058 } 1059 klass = FW_CFG_DATA_GENERATOR_GET_CLASS(obj); 1060 array = klass->get_data(obj, errp); 1061 if (!array) { 1062 return false; 1063 } 1064 size = array->len; 1065 fw_cfg_add_file(s, filename, g_byte_array_free(array, FALSE), size); 1066 1067 return true; 1068 } 1069 1070 void fw_cfg_add_extra_pci_roots(PCIBus *bus, FWCfgState *s) 1071 { 1072 int extra_hosts = 0; 1073 1074 if (!bus) { 1075 return; 1076 } 1077 1078 QLIST_FOREACH(bus, &bus->child, sibling) { 1079 /* look for expander root buses */ 1080 if (pci_bus_is_root(bus)) { 1081 extra_hosts++; 1082 } 1083 } 1084 1085 if (extra_hosts && s) { 1086 uint64_t *val = g_malloc(sizeof(*val)); 1087 *val = cpu_to_le64(extra_hosts); 1088 fw_cfg_add_file(s, "etc/extra-pci-roots", val, sizeof(*val)); 1089 } 1090 } 1091 1092 static void fw_cfg_machine_reset(void *opaque) 1093 { 1094 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 1095 FWCfgState *s = opaque; 1096 void *ptr; 1097 size_t len; 1098 char *buf; 1099 1100 buf = get_boot_devices_list(&len); 1101 ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)buf, len); 1102 g_free(ptr); 1103 1104 if (!mc->legacy_fw_cfg_order) { 1105 buf = get_boot_devices_lchs_list(&len); 1106 ptr = fw_cfg_modify_file(s, "bios-geometry", (uint8_t *)buf, len); 1107 g_free(ptr); 1108 } 1109 } 1110 1111 static void fw_cfg_machine_ready(struct Notifier *n, void *data) 1112 { 1113 FWCfgState *s = container_of(n, FWCfgState, machine_ready); 1114 qemu_register_reset(fw_cfg_machine_reset, s); 1115 } 1116 1117 static Property fw_cfg_properties[] = { 1118 DEFINE_PROP_BOOL("acpi-mr-restore", FWCfgState, acpi_mr_restore, true), 1119 DEFINE_PROP_END_OF_LIST(), 1120 }; 1121 1122 static void fw_cfg_common_realize(DeviceState *dev, Error **errp) 1123 { 1124 FWCfgState *s = FW_CFG(dev); 1125 MachineState *machine = MACHINE(qdev_get_machine()); 1126 uint32_t version = FW_CFG_VERSION; 1127 1128 if (!fw_cfg_find()) { 1129 error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG); 1130 return; 1131 } 1132 1133 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4); 1134 fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16); 1135 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics); 1136 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu); 1137 fw_cfg_bootsplash(s); 1138 fw_cfg_reboot(s); 1139 1140 if (s->dma_enabled) { 1141 version |= FW_CFG_VERSION_DMA; 1142 } 1143 1144 fw_cfg_add_i32(s, FW_CFG_ID, version); 1145 1146 s->machine_ready.notify = fw_cfg_machine_ready; 1147 qemu_add_machine_init_done_notifier(&s->machine_ready); 1148 } 1149 1150 FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, 1151 AddressSpace *dma_as) 1152 { 1153 DeviceState *dev; 1154 SysBusDevice *sbd; 1155 FWCfgIoState *ios; 1156 FWCfgState *s; 1157 bool dma_requested = dma_iobase && dma_as; 1158 1159 dev = qdev_new(TYPE_FW_CFG_IO); 1160 if (!dma_requested) { 1161 qdev_prop_set_bit(dev, "dma_enabled", false); 1162 } 1163 1164 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1165 OBJECT(dev)); 1166 1167 sbd = SYS_BUS_DEVICE(dev); 1168 sysbus_realize_and_unref(sbd, &error_fatal); 1169 ios = FW_CFG_IO(dev); 1170 sysbus_add_io(sbd, iobase, &ios->comb_iomem); 1171 1172 s = FW_CFG(dev); 1173 1174 if (s->dma_enabled) { 1175 /* 64 bits for the address field */ 1176 s->dma_as = dma_as; 1177 s->dma_addr = 0; 1178 sysbus_add_io(sbd, dma_iobase, &s->dma_iomem); 1179 } 1180 1181 return s; 1182 } 1183 1184 FWCfgState *fw_cfg_init_io(uint32_t iobase) 1185 { 1186 return fw_cfg_init_io_dma(iobase, 0, NULL); 1187 } 1188 1189 FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, 1190 hwaddr data_addr, uint32_t data_width, 1191 hwaddr dma_addr, AddressSpace *dma_as) 1192 { 1193 DeviceState *dev; 1194 SysBusDevice *sbd; 1195 FWCfgState *s; 1196 bool dma_requested = dma_addr && dma_as; 1197 1198 dev = qdev_new(TYPE_FW_CFG_MEM); 1199 qdev_prop_set_uint32(dev, "data_width", data_width); 1200 if (!dma_requested) { 1201 qdev_prop_set_bit(dev, "dma_enabled", false); 1202 } 1203 1204 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1205 OBJECT(dev)); 1206 1207 sbd = SYS_BUS_DEVICE(dev); 1208 sysbus_realize_and_unref(sbd, &error_fatal); 1209 sysbus_mmio_map(sbd, 0, ctl_addr); 1210 sysbus_mmio_map(sbd, 1, data_addr); 1211 1212 s = FW_CFG(dev); 1213 1214 if (s->dma_enabled) { 1215 s->dma_as = dma_as; 1216 s->dma_addr = 0; 1217 sysbus_mmio_map(sbd, 2, dma_addr); 1218 } 1219 1220 return s; 1221 } 1222 1223 FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr) 1224 { 1225 return fw_cfg_init_mem_wide(ctl_addr, data_addr, 1226 fw_cfg_data_mem_ops.valid.max_access_size, 1227 0, NULL); 1228 } 1229 1230 1231 FWCfgState *fw_cfg_find(void) 1232 { 1233 /* Returns NULL unless there is exactly one fw_cfg device */ 1234 return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL)); 1235 } 1236 1237 1238 static void fw_cfg_class_init(ObjectClass *klass, void *data) 1239 { 1240 DeviceClass *dc = DEVICE_CLASS(klass); 1241 1242 dc->reset = fw_cfg_reset; 1243 dc->vmsd = &vmstate_fw_cfg; 1244 1245 device_class_set_props(dc, fw_cfg_properties); 1246 } 1247 1248 static const TypeInfo fw_cfg_info = { 1249 .name = TYPE_FW_CFG, 1250 .parent = TYPE_SYS_BUS_DEVICE, 1251 .abstract = true, 1252 .instance_size = sizeof(FWCfgState), 1253 .class_init = fw_cfg_class_init, 1254 }; 1255 1256 static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp) 1257 { 1258 uint16_t file_slots_max; 1259 1260 if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) { 1261 error_setg(errp, "\"file_slots\" must be at least 0x%x", 1262 FW_CFG_FILE_SLOTS_MIN); 1263 return; 1264 } 1265 1266 /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value 1267 * that we permit. The actual (exclusive) value coming from the 1268 * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */ 1269 file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1; 1270 if (fw_cfg_file_slots(s) > file_slots_max) { 1271 error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16, 1272 file_slots_max); 1273 return; 1274 } 1275 1276 s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s)); 1277 s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s)); 1278 s->entry_order = g_new0(int, fw_cfg_max_entry(s)); 1279 } 1280 1281 static Property fw_cfg_io_properties[] = { 1282 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled, 1283 true), 1284 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots, 1285 FW_CFG_FILE_SLOTS_DFLT), 1286 DEFINE_PROP_END_OF_LIST(), 1287 }; 1288 1289 static void fw_cfg_io_realize(DeviceState *dev, Error **errp) 1290 { 1291 ERRP_GUARD(); 1292 FWCfgIoState *s = FW_CFG_IO(dev); 1293 1294 fw_cfg_file_slots_allocate(FW_CFG(s), errp); 1295 if (*errp) { 1296 return; 1297 } 1298 1299 /* when using port i/o, the 8-bit data register ALWAYS overlaps 1300 * with half of the 16-bit control register. Hence, the total size 1301 * of the i/o region used is FW_CFG_CTL_SIZE */ 1302 memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops, 1303 FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE); 1304 1305 if (FW_CFG(s)->dma_enabled) { 1306 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), 1307 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", 1308 sizeof(dma_addr_t)); 1309 } 1310 1311 fw_cfg_common_realize(dev, errp); 1312 } 1313 1314 static void fw_cfg_io_class_init(ObjectClass *klass, void *data) 1315 { 1316 DeviceClass *dc = DEVICE_CLASS(klass); 1317 1318 dc->realize = fw_cfg_io_realize; 1319 device_class_set_props(dc, fw_cfg_io_properties); 1320 } 1321 1322 static const TypeInfo fw_cfg_io_info = { 1323 .name = TYPE_FW_CFG_IO, 1324 .parent = TYPE_FW_CFG, 1325 .instance_size = sizeof(FWCfgIoState), 1326 .class_init = fw_cfg_io_class_init, 1327 }; 1328 1329 1330 static Property fw_cfg_mem_properties[] = { 1331 DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1), 1332 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled, 1333 true), 1334 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots, 1335 FW_CFG_FILE_SLOTS_DFLT), 1336 DEFINE_PROP_END_OF_LIST(), 1337 }; 1338 1339 static void fw_cfg_mem_realize(DeviceState *dev, Error **errp) 1340 { 1341 ERRP_GUARD(); 1342 FWCfgMemState *s = FW_CFG_MEM(dev); 1343 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1344 const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops; 1345 1346 fw_cfg_file_slots_allocate(FW_CFG(s), errp); 1347 if (*errp) { 1348 return; 1349 } 1350 1351 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops, 1352 FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE); 1353 sysbus_init_mmio(sbd, &s->ctl_iomem); 1354 1355 if (s->data_width > data_ops->valid.max_access_size) { 1356 s->wide_data_ops = *data_ops; 1357 1358 s->wide_data_ops.valid.max_access_size = s->data_width; 1359 s->wide_data_ops.impl.max_access_size = s->data_width; 1360 data_ops = &s->wide_data_ops; 1361 } 1362 memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s), 1363 "fwcfg.data", data_ops->valid.max_access_size); 1364 sysbus_init_mmio(sbd, &s->data_iomem); 1365 1366 if (FW_CFG(s)->dma_enabled) { 1367 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), 1368 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", 1369 sizeof(dma_addr_t)); 1370 sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem); 1371 } 1372 1373 fw_cfg_common_realize(dev, errp); 1374 } 1375 1376 static void fw_cfg_mem_class_init(ObjectClass *klass, void *data) 1377 { 1378 DeviceClass *dc = DEVICE_CLASS(klass); 1379 1380 dc->realize = fw_cfg_mem_realize; 1381 device_class_set_props(dc, fw_cfg_mem_properties); 1382 } 1383 1384 static const TypeInfo fw_cfg_mem_info = { 1385 .name = TYPE_FW_CFG_MEM, 1386 .parent = TYPE_FW_CFG, 1387 .instance_size = sizeof(FWCfgMemState), 1388 .class_init = fw_cfg_mem_class_init, 1389 }; 1390 1391 static void fw_cfg_register_types(void) 1392 { 1393 type_register_static(&fw_cfg_info); 1394 type_register_static(&fw_cfg_io_info); 1395 type_register_static(&fw_cfg_mem_info); 1396 } 1397 1398 type_init(fw_cfg_register_types) 1399