1 /* 2 * QEMU Firmware configuration device emulation 3 * 4 * Copyright (c) 2008 Gleb Natapov 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/dma.h" 29 #include "sysemu/reset.h" 30 #include "hw/boards.h" 31 #include "hw/nvram/fw_cfg.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/sysbus.h" 34 #include "migration/qemu-file-types.h" 35 #include "migration/vmstate.h" 36 #include "trace.h" 37 #include "qemu/error-report.h" 38 #include "qemu/option.h" 39 #include "qemu/config-file.h" 40 #include "qemu/cutils.h" 41 #include "qapi/error.h" 42 43 #define FW_CFG_FILE_SLOTS_DFLT 0x20 44 45 /* FW_CFG_VERSION bits */ 46 #define FW_CFG_VERSION 0x01 47 #define FW_CFG_VERSION_DMA 0x02 48 49 /* FW_CFG_DMA_CONTROL bits */ 50 #define FW_CFG_DMA_CTL_ERROR 0x01 51 #define FW_CFG_DMA_CTL_READ 0x02 52 #define FW_CFG_DMA_CTL_SKIP 0x04 53 #define FW_CFG_DMA_CTL_SELECT 0x08 54 #define FW_CFG_DMA_CTL_WRITE 0x10 55 56 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */ 57 58 struct FWCfgEntry { 59 uint32_t len; 60 bool allow_write; 61 uint8_t *data; 62 void *callback_opaque; 63 FWCfgCallback select_cb; 64 FWCfgWriteCallback write_cb; 65 }; 66 67 /** 68 * key_name: 69 * 70 * @key: The uint16 selector key. 71 * 72 * Returns: The stringified name if the selector refers to a well-known 73 * numerically defined item, or NULL on key lookup failure. 74 */ 75 static const char *key_name(uint16_t key) 76 { 77 static const char *fw_cfg_wellknown_keys[FW_CFG_FILE_FIRST] = { 78 [FW_CFG_SIGNATURE] = "signature", 79 [FW_CFG_ID] = "id", 80 [FW_CFG_UUID] = "uuid", 81 [FW_CFG_RAM_SIZE] = "ram_size", 82 [FW_CFG_NOGRAPHIC] = "nographic", 83 [FW_CFG_NB_CPUS] = "nb_cpus", 84 [FW_CFG_MACHINE_ID] = "machine_id", 85 [FW_CFG_KERNEL_ADDR] = "kernel_addr", 86 [FW_CFG_KERNEL_SIZE] = "kernel_size", 87 [FW_CFG_KERNEL_CMDLINE] = "kernel_cmdline", 88 [FW_CFG_INITRD_ADDR] = "initrd_addr", 89 [FW_CFG_INITRD_SIZE] = "initdr_size", 90 [FW_CFG_BOOT_DEVICE] = "boot_device", 91 [FW_CFG_NUMA] = "numa", 92 [FW_CFG_BOOT_MENU] = "boot_menu", 93 [FW_CFG_MAX_CPUS] = "max_cpus", 94 [FW_CFG_KERNEL_ENTRY] = "kernel_entry", 95 [FW_CFG_KERNEL_DATA] = "kernel_data", 96 [FW_CFG_INITRD_DATA] = "initrd_data", 97 [FW_CFG_CMDLINE_ADDR] = "cmdline_addr", 98 [FW_CFG_CMDLINE_SIZE] = "cmdline_size", 99 [FW_CFG_CMDLINE_DATA] = "cmdline_data", 100 [FW_CFG_SETUP_ADDR] = "setup_addr", 101 [FW_CFG_SETUP_SIZE] = "setup_size", 102 [FW_CFG_SETUP_DATA] = "setup_data", 103 [FW_CFG_FILE_DIR] = "file_dir", 104 }; 105 106 if (key & FW_CFG_ARCH_LOCAL) { 107 return fw_cfg_arch_key_name(key); 108 } 109 if (key < FW_CFG_FILE_FIRST) { 110 return fw_cfg_wellknown_keys[key]; 111 } 112 113 return NULL; 114 } 115 116 static inline const char *trace_key_name(uint16_t key) 117 { 118 const char *name = key_name(key); 119 120 return name ? name : "unknown"; 121 } 122 123 #define JPG_FILE 0 124 #define BMP_FILE 1 125 126 static char *read_splashfile(char *filename, gsize *file_sizep, 127 int *file_typep) 128 { 129 GError *err = NULL; 130 gchar *content; 131 int file_type; 132 unsigned int filehead; 133 int bmp_bpp; 134 135 if (!g_file_get_contents(filename, &content, file_sizep, &err)) { 136 error_report("failed to read splash file '%s': %s", 137 filename, err->message); 138 g_error_free(err); 139 return NULL; 140 } 141 142 /* check file size */ 143 if (*file_sizep < 30) { 144 goto error; 145 } 146 147 /* check magic ID */ 148 filehead = lduw_le_p(content); 149 if (filehead == 0xd8ff) { 150 file_type = JPG_FILE; 151 } else if (filehead == 0x4d42) { 152 file_type = BMP_FILE; 153 } else { 154 goto error; 155 } 156 157 /* check BMP bpp */ 158 if (file_type == BMP_FILE) { 159 bmp_bpp = lduw_le_p(&content[28]); 160 if (bmp_bpp != 24) { 161 goto error; 162 } 163 } 164 165 /* return values */ 166 *file_typep = file_type; 167 168 return content; 169 170 error: 171 error_report("splash file '%s' format not recognized; must be JPEG " 172 "or 24 bit BMP", filename); 173 g_free(content); 174 return NULL; 175 } 176 177 static void fw_cfg_bootsplash(FWCfgState *s) 178 { 179 const char *boot_splash_filename = NULL; 180 const char *boot_splash_time = NULL; 181 char *filename, *file_data; 182 gsize file_size; 183 int file_type; 184 185 /* get user configuration */ 186 QemuOptsList *plist = qemu_find_opts("boot-opts"); 187 QemuOpts *opts = QTAILQ_FIRST(&plist->head); 188 boot_splash_filename = qemu_opt_get(opts, "splash"); 189 boot_splash_time = qemu_opt_get(opts, "splash-time"); 190 191 /* insert splash time if user configurated */ 192 if (boot_splash_time) { 193 int64_t bst_val = qemu_opt_get_number(opts, "splash-time", -1); 194 uint16_t bst_le16; 195 196 /* validate the input */ 197 if (bst_val < 0 || bst_val > 0xffff) { 198 error_report("splash-time is invalid," 199 "it should be a value between 0 and 65535"); 200 exit(1); 201 } 202 /* use little endian format */ 203 bst_le16 = cpu_to_le16(bst_val); 204 fw_cfg_add_file(s, "etc/boot-menu-wait", 205 g_memdup(&bst_le16, sizeof bst_le16), sizeof bst_le16); 206 } 207 208 /* insert splash file if user configurated */ 209 if (boot_splash_filename) { 210 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename); 211 if (filename == NULL) { 212 error_report("failed to find file '%s'", boot_splash_filename); 213 return; 214 } 215 216 /* loading file data */ 217 file_data = read_splashfile(filename, &file_size, &file_type); 218 if (file_data == NULL) { 219 g_free(filename); 220 return; 221 } 222 g_free(boot_splash_filedata); 223 boot_splash_filedata = (uint8_t *)file_data; 224 225 /* insert data */ 226 if (file_type == JPG_FILE) { 227 fw_cfg_add_file(s, "bootsplash.jpg", 228 boot_splash_filedata, file_size); 229 } else { 230 fw_cfg_add_file(s, "bootsplash.bmp", 231 boot_splash_filedata, file_size); 232 } 233 g_free(filename); 234 } 235 } 236 237 static void fw_cfg_reboot(FWCfgState *s) 238 { 239 const char *reboot_timeout = NULL; 240 int64_t rt_val = -1; 241 uint32_t rt_le32; 242 243 /* get user configuration */ 244 QemuOptsList *plist = qemu_find_opts("boot-opts"); 245 QemuOpts *opts = QTAILQ_FIRST(&plist->head); 246 reboot_timeout = qemu_opt_get(opts, "reboot-timeout"); 247 248 if (reboot_timeout) { 249 rt_val = qemu_opt_get_number(opts, "reboot-timeout", -1); 250 /* validate the input */ 251 if (rt_val < 0 || rt_val > 0xffff) { 252 error_report("reboot timeout is invalid," 253 "it should be a value between 0 and 65535"); 254 exit(1); 255 } 256 } 257 258 rt_le32 = cpu_to_le32(rt_val); 259 fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&rt_le32, 4), 4); 260 } 261 262 static void fw_cfg_write(FWCfgState *s, uint8_t value) 263 { 264 /* nothing, write support removed in QEMU v2.4+ */ 265 } 266 267 static inline uint16_t fw_cfg_file_slots(const FWCfgState *s) 268 { 269 return s->file_slots; 270 } 271 272 /* Note: this function returns an exclusive limit. */ 273 static inline uint32_t fw_cfg_max_entry(const FWCfgState *s) 274 { 275 return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s); 276 } 277 278 static int fw_cfg_select(FWCfgState *s, uint16_t key) 279 { 280 int arch, ret; 281 FWCfgEntry *e; 282 283 s->cur_offset = 0; 284 if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) { 285 s->cur_entry = FW_CFG_INVALID; 286 ret = 0; 287 } else { 288 s->cur_entry = key; 289 ret = 1; 290 /* entry successfully selected, now run callback if present */ 291 arch = !!(key & FW_CFG_ARCH_LOCAL); 292 e = &s->entries[arch][key & FW_CFG_ENTRY_MASK]; 293 if (e->select_cb) { 294 e->select_cb(e->callback_opaque); 295 } 296 } 297 298 trace_fw_cfg_select(s, key, trace_key_name(key), ret); 299 return ret; 300 } 301 302 static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size) 303 { 304 FWCfgState *s = opaque; 305 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); 306 FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL : 307 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; 308 uint64_t value = 0; 309 310 assert(size > 0 && size <= sizeof(value)); 311 if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) { 312 /* The least significant 'size' bytes of the return value are 313 * expected to contain a string preserving portion of the item 314 * data, padded with zeros on the right in case we run out early. 315 * In technical terms, we're composing the host-endian representation 316 * of the big endian interpretation of the fw_cfg string. 317 */ 318 do { 319 value = (value << 8) | e->data[s->cur_offset++]; 320 } while (--size && s->cur_offset < e->len); 321 /* If size is still not zero, we *did* run out early, so continue 322 * left-shifting, to add the appropriate number of padding zeros 323 * on the right. 324 */ 325 value <<= 8 * size; 326 } 327 328 trace_fw_cfg_read(s, value); 329 return value; 330 } 331 332 static void fw_cfg_data_mem_write(void *opaque, hwaddr addr, 333 uint64_t value, unsigned size) 334 { 335 FWCfgState *s = opaque; 336 unsigned i = size; 337 338 do { 339 fw_cfg_write(s, value >> (8 * --i)); 340 } while (i); 341 } 342 343 static void fw_cfg_dma_transfer(FWCfgState *s) 344 { 345 dma_addr_t len; 346 FWCfgDmaAccess dma; 347 int arch; 348 FWCfgEntry *e; 349 int read = 0, write = 0; 350 dma_addr_t dma_addr; 351 352 /* Reset the address before the next access */ 353 dma_addr = s->dma_addr; 354 s->dma_addr = 0; 355 356 if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) { 357 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), 358 FW_CFG_DMA_CTL_ERROR); 359 return; 360 } 361 362 dma.address = be64_to_cpu(dma.address); 363 dma.length = be32_to_cpu(dma.length); 364 dma.control = be32_to_cpu(dma.control); 365 366 if (dma.control & FW_CFG_DMA_CTL_SELECT) { 367 fw_cfg_select(s, dma.control >> 16); 368 } 369 370 arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); 371 e = (s->cur_entry == FW_CFG_INVALID) ? NULL : 372 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; 373 374 if (dma.control & FW_CFG_DMA_CTL_READ) { 375 read = 1; 376 write = 0; 377 } else if (dma.control & FW_CFG_DMA_CTL_WRITE) { 378 read = 0; 379 write = 1; 380 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) { 381 read = 0; 382 write = 0; 383 } else { 384 dma.length = 0; 385 } 386 387 dma.control = 0; 388 389 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) { 390 if (s->cur_entry == FW_CFG_INVALID || !e->data || 391 s->cur_offset >= e->len) { 392 len = dma.length; 393 394 /* If the access is not a read access, it will be a skip access, 395 * tested before. 396 */ 397 if (read) { 398 if (dma_memory_set(s->dma_as, dma.address, 0, len)) { 399 dma.control |= FW_CFG_DMA_CTL_ERROR; 400 } 401 } 402 if (write) { 403 dma.control |= FW_CFG_DMA_CTL_ERROR; 404 } 405 } else { 406 if (dma.length <= (e->len - s->cur_offset)) { 407 len = dma.length; 408 } else { 409 len = (e->len - s->cur_offset); 410 } 411 412 /* If the access is not a read access, it will be a skip access, 413 * tested before. 414 */ 415 if (read) { 416 if (dma_memory_write(s->dma_as, dma.address, 417 &e->data[s->cur_offset], len)) { 418 dma.control |= FW_CFG_DMA_CTL_ERROR; 419 } 420 } 421 if (write) { 422 if (!e->allow_write || 423 len != dma.length || 424 dma_memory_read(s->dma_as, dma.address, 425 &e->data[s->cur_offset], len)) { 426 dma.control |= FW_CFG_DMA_CTL_ERROR; 427 } else if (e->write_cb) { 428 e->write_cb(e->callback_opaque, s->cur_offset, len); 429 } 430 } 431 432 s->cur_offset += len; 433 } 434 435 dma.address += len; 436 dma.length -= len; 437 438 } 439 440 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), 441 dma.control); 442 443 trace_fw_cfg_read(s, 0); 444 } 445 446 static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr, 447 unsigned size) 448 { 449 /* Return a signature value (and handle various read sizes) */ 450 return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8); 451 } 452 453 static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr, 454 uint64_t value, unsigned size) 455 { 456 FWCfgState *s = opaque; 457 458 if (size == 4) { 459 if (addr == 0) { 460 /* FWCfgDmaAccess high address */ 461 s->dma_addr = value << 32; 462 } else if (addr == 4) { 463 /* FWCfgDmaAccess low address */ 464 s->dma_addr |= value; 465 fw_cfg_dma_transfer(s); 466 } 467 } else if (size == 8 && addr == 0) { 468 s->dma_addr = value; 469 fw_cfg_dma_transfer(s); 470 } 471 } 472 473 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr, 474 unsigned size, bool is_write, 475 MemTxAttrs attrs) 476 { 477 return !is_write || ((size == 4 && (addr == 0 || addr == 4)) || 478 (size == 8 && addr == 0)); 479 } 480 481 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr, 482 unsigned size, bool is_write, 483 MemTxAttrs attrs) 484 { 485 return addr == 0; 486 } 487 488 static uint64_t fw_cfg_ctl_mem_read(void *opaque, hwaddr addr, unsigned size) 489 { 490 return 0; 491 } 492 493 static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr, 494 uint64_t value, unsigned size) 495 { 496 fw_cfg_select(opaque, (uint16_t)value); 497 } 498 499 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr, 500 unsigned size, bool is_write, 501 MemTxAttrs attrs) 502 { 503 return is_write && size == 2; 504 } 505 506 static void fw_cfg_comb_write(void *opaque, hwaddr addr, 507 uint64_t value, unsigned size) 508 { 509 switch (size) { 510 case 1: 511 fw_cfg_write(opaque, (uint8_t)value); 512 break; 513 case 2: 514 fw_cfg_select(opaque, (uint16_t)value); 515 break; 516 } 517 } 518 519 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr, 520 unsigned size, bool is_write, 521 MemTxAttrs attrs) 522 { 523 return (size == 1) || (is_write && size == 2); 524 } 525 526 static const MemoryRegionOps fw_cfg_ctl_mem_ops = { 527 .read = fw_cfg_ctl_mem_read, 528 .write = fw_cfg_ctl_mem_write, 529 .endianness = DEVICE_BIG_ENDIAN, 530 .valid.accepts = fw_cfg_ctl_mem_valid, 531 }; 532 533 static const MemoryRegionOps fw_cfg_data_mem_ops = { 534 .read = fw_cfg_data_read, 535 .write = fw_cfg_data_mem_write, 536 .endianness = DEVICE_BIG_ENDIAN, 537 .valid = { 538 .min_access_size = 1, 539 .max_access_size = 1, 540 .accepts = fw_cfg_data_mem_valid, 541 }, 542 }; 543 544 static const MemoryRegionOps fw_cfg_comb_mem_ops = { 545 .read = fw_cfg_data_read, 546 .write = fw_cfg_comb_write, 547 .endianness = DEVICE_LITTLE_ENDIAN, 548 .valid.accepts = fw_cfg_comb_valid, 549 }; 550 551 static const MemoryRegionOps fw_cfg_dma_mem_ops = { 552 .read = fw_cfg_dma_mem_read, 553 .write = fw_cfg_dma_mem_write, 554 .endianness = DEVICE_BIG_ENDIAN, 555 .valid.accepts = fw_cfg_dma_mem_valid, 556 .valid.max_access_size = 8, 557 .impl.max_access_size = 8, 558 }; 559 560 static void fw_cfg_reset(DeviceState *d) 561 { 562 FWCfgState *s = FW_CFG(d); 563 564 /* we never register a read callback for FW_CFG_SIGNATURE */ 565 fw_cfg_select(s, FW_CFG_SIGNATURE); 566 } 567 568 /* Save restore 32 bit int as uint16_t 569 This is a Big hack, but it is how the old state did it. 570 Or we broke compatibility in the state, or we can't use struct tm 571 */ 572 573 static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size, 574 const VMStateField *field) 575 { 576 uint32_t *v = pv; 577 *v = qemu_get_be16(f); 578 return 0; 579 } 580 581 static int put_unused(QEMUFile *f, void *pv, size_t size, 582 const VMStateField *field, QJSON *vmdesc) 583 { 584 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n"); 585 fprintf(stderr, "This functions shouldn't be called.\n"); 586 587 return 0; 588 } 589 590 static const VMStateInfo vmstate_hack_uint32_as_uint16 = { 591 .name = "int32_as_uint16", 592 .get = get_uint32_as_uint16, 593 .put = put_unused, 594 }; 595 596 #define VMSTATE_UINT16_HACK(_f, _s, _t) \ 597 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t) 598 599 600 static bool is_version_1(void *opaque, int version_id) 601 { 602 return version_id == 1; 603 } 604 605 bool fw_cfg_dma_enabled(void *opaque) 606 { 607 FWCfgState *s = opaque; 608 609 return s->dma_enabled; 610 } 611 612 static const VMStateDescription vmstate_fw_cfg_dma = { 613 .name = "fw_cfg/dma", 614 .needed = fw_cfg_dma_enabled, 615 .fields = (VMStateField[]) { 616 VMSTATE_UINT64(dma_addr, FWCfgState), 617 VMSTATE_END_OF_LIST() 618 }, 619 }; 620 621 static const VMStateDescription vmstate_fw_cfg = { 622 .name = "fw_cfg", 623 .version_id = 2, 624 .minimum_version_id = 1, 625 .fields = (VMStateField[]) { 626 VMSTATE_UINT16(cur_entry, FWCfgState), 627 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1), 628 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2), 629 VMSTATE_END_OF_LIST() 630 }, 631 .subsections = (const VMStateDescription*[]) { 632 &vmstate_fw_cfg_dma, 633 NULL, 634 } 635 }; 636 637 static void fw_cfg_add_bytes_callback(FWCfgState *s, uint16_t key, 638 FWCfgCallback select_cb, 639 FWCfgWriteCallback write_cb, 640 void *callback_opaque, 641 void *data, size_t len, 642 bool read_only) 643 { 644 int arch = !!(key & FW_CFG_ARCH_LOCAL); 645 646 key &= FW_CFG_ENTRY_MASK; 647 648 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX); 649 assert(s->entries[arch][key].data == NULL); /* avoid key conflict */ 650 651 s->entries[arch][key].data = data; 652 s->entries[arch][key].len = (uint32_t)len; 653 s->entries[arch][key].select_cb = select_cb; 654 s->entries[arch][key].write_cb = write_cb; 655 s->entries[arch][key].callback_opaque = callback_opaque; 656 s->entries[arch][key].allow_write = !read_only; 657 } 658 659 static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key, 660 void *data, size_t len) 661 { 662 void *ptr; 663 int arch = !!(key & FW_CFG_ARCH_LOCAL); 664 665 key &= FW_CFG_ENTRY_MASK; 666 667 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX); 668 669 /* return the old data to the function caller, avoid memory leak */ 670 ptr = s->entries[arch][key].data; 671 s->entries[arch][key].data = data; 672 s->entries[arch][key].len = len; 673 s->entries[arch][key].callback_opaque = NULL; 674 s->entries[arch][key].allow_write = false; 675 676 return ptr; 677 } 678 679 void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len) 680 { 681 trace_fw_cfg_add_bytes(key, trace_key_name(key), len); 682 fw_cfg_add_bytes_callback(s, key, NULL, NULL, NULL, data, len, true); 683 } 684 685 void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value) 686 { 687 size_t sz = strlen(value) + 1; 688 689 trace_fw_cfg_add_string(key, trace_key_name(key), value); 690 fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz); 691 } 692 693 void fw_cfg_modify_string(FWCfgState *s, uint16_t key, const char *value) 694 { 695 size_t sz = strlen(value) + 1; 696 char *old; 697 698 old = fw_cfg_modify_bytes_read(s, key, g_memdup(value, sz), sz); 699 g_free(old); 700 } 701 702 void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value) 703 { 704 uint16_t *copy; 705 706 copy = g_malloc(sizeof(value)); 707 *copy = cpu_to_le16(value); 708 trace_fw_cfg_add_i16(key, trace_key_name(key), value); 709 fw_cfg_add_bytes(s, key, copy, sizeof(value)); 710 } 711 712 void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value) 713 { 714 uint16_t *copy, *old; 715 716 copy = g_malloc(sizeof(value)); 717 *copy = cpu_to_le16(value); 718 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); 719 g_free(old); 720 } 721 722 void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value) 723 { 724 uint32_t *copy; 725 726 copy = g_malloc(sizeof(value)); 727 *copy = cpu_to_le32(value); 728 trace_fw_cfg_add_i32(key, trace_key_name(key), value); 729 fw_cfg_add_bytes(s, key, copy, sizeof(value)); 730 } 731 732 void fw_cfg_modify_i32(FWCfgState *s, uint16_t key, uint32_t value) 733 { 734 uint32_t *copy, *old; 735 736 copy = g_malloc(sizeof(value)); 737 *copy = cpu_to_le32(value); 738 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); 739 g_free(old); 740 } 741 742 void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value) 743 { 744 uint64_t *copy; 745 746 copy = g_malloc(sizeof(value)); 747 *copy = cpu_to_le64(value); 748 trace_fw_cfg_add_i64(key, trace_key_name(key), value); 749 fw_cfg_add_bytes(s, key, copy, sizeof(value)); 750 } 751 752 void fw_cfg_modify_i64(FWCfgState *s, uint16_t key, uint64_t value) 753 { 754 uint64_t *copy, *old; 755 756 copy = g_malloc(sizeof(value)); 757 *copy = cpu_to_le64(value); 758 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); 759 g_free(old); 760 } 761 762 void fw_cfg_set_order_override(FWCfgState *s, int order) 763 { 764 assert(s->fw_cfg_order_override == 0); 765 s->fw_cfg_order_override = order; 766 } 767 768 void fw_cfg_reset_order_override(FWCfgState *s) 769 { 770 assert(s->fw_cfg_order_override != 0); 771 s->fw_cfg_order_override = 0; 772 } 773 774 /* 775 * This is the legacy order list. For legacy systems, files are in 776 * the fw_cfg in the order defined below, by the "order" value. Note 777 * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a 778 * specific area, but there may be more than one and they occur in the 779 * order that the user specifies them on the command line. Those are 780 * handled in a special manner, using the order override above. 781 * 782 * For non-legacy, the files are sorted by filename to avoid this kind 783 * of complexity in the future. 784 * 785 * This is only for x86, other arches don't implement versioning so 786 * they won't set legacy mode. 787 */ 788 static struct { 789 const char *name; 790 int order; 791 } fw_cfg_order[] = { 792 { "etc/boot-menu-wait", 10 }, 793 { "bootsplash.jpg", 11 }, 794 { "bootsplash.bmp", 12 }, 795 { "etc/boot-fail-wait", 15 }, 796 { "etc/smbios/smbios-tables", 20 }, 797 { "etc/smbios/smbios-anchor", 30 }, 798 { "etc/e820", 40 }, 799 { "etc/reserved-memory-end", 50 }, 800 { "genroms/kvmvapic.bin", 55 }, 801 { "genroms/linuxboot.bin", 60 }, 802 { }, /* VGA ROMs from pc_vga_init come here, 70. */ 803 { }, /* NIC option ROMs from pc_nic_init come here, 80. */ 804 { "etc/system-states", 90 }, 805 { }, /* User ROMs come here, 100. */ 806 { }, /* Device FW comes here, 110. */ 807 { "etc/extra-pci-roots", 120 }, 808 { "etc/acpi/tables", 130 }, 809 { "etc/table-loader", 140 }, 810 { "etc/tpm/log", 150 }, 811 { "etc/acpi/rsdp", 160 }, 812 { "bootorder", 170 }, 813 814 #define FW_CFG_ORDER_OVERRIDE_LAST 200 815 }; 816 817 static int get_fw_cfg_order(FWCfgState *s, const char *name) 818 { 819 int i; 820 821 if (s->fw_cfg_order_override > 0) { 822 return s->fw_cfg_order_override; 823 } 824 825 for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) { 826 if (fw_cfg_order[i].name == NULL) { 827 continue; 828 } 829 830 if (strcmp(name, fw_cfg_order[i].name) == 0) { 831 return fw_cfg_order[i].order; 832 } 833 } 834 835 /* Stick unknown stuff at the end. */ 836 warn_report("Unknown firmware file in legacy mode: %s", name); 837 return FW_CFG_ORDER_OVERRIDE_LAST; 838 } 839 840 void fw_cfg_add_file_callback(FWCfgState *s, const char *filename, 841 FWCfgCallback select_cb, 842 FWCfgWriteCallback write_cb, 843 void *callback_opaque, 844 void *data, size_t len, bool read_only) 845 { 846 int i, index, count; 847 size_t dsize; 848 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 849 int order = 0; 850 851 if (!s->files) { 852 dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s); 853 s->files = g_malloc0(dsize); 854 fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize); 855 } 856 857 count = be32_to_cpu(s->files->count); 858 assert(count < fw_cfg_file_slots(s)); 859 860 /* Find the insertion point. */ 861 if (mc->legacy_fw_cfg_order) { 862 /* 863 * Sort by order. For files with the same order, we keep them 864 * in the sequence in which they were added. 865 */ 866 order = get_fw_cfg_order(s, filename); 867 for (index = count; 868 index > 0 && order < s->entry_order[index - 1]; 869 index--); 870 } else { 871 /* Sort by file name. */ 872 for (index = count; 873 index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0; 874 index--); 875 } 876 877 /* 878 * Move all the entries from the index point and after down one 879 * to create a slot for the new entry. Because calculations are 880 * being done with the index, make it so that "i" is the current 881 * index and "i - 1" is the one being copied from, thus the 882 * unusual start and end in the for statement. 883 */ 884 for (i = count; i > index; i--) { 885 s->files->f[i] = s->files->f[i - 1]; 886 s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i); 887 s->entries[0][FW_CFG_FILE_FIRST + i] = 888 s->entries[0][FW_CFG_FILE_FIRST + i - 1]; 889 s->entry_order[i] = s->entry_order[i - 1]; 890 } 891 892 memset(&s->files->f[index], 0, sizeof(FWCfgFile)); 893 memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry)); 894 895 pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename); 896 for (i = 0; i <= count; i++) { 897 if (i != index && 898 strcmp(s->files->f[index].name, s->files->f[i].name) == 0) { 899 error_report("duplicate fw_cfg file name: %s", 900 s->files->f[index].name); 901 exit(1); 902 } 903 } 904 905 fw_cfg_add_bytes_callback(s, FW_CFG_FILE_FIRST + index, 906 select_cb, write_cb, 907 callback_opaque, data, len, 908 read_only); 909 910 s->files->f[index].size = cpu_to_be32(len); 911 s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index); 912 s->entry_order[index] = order; 913 trace_fw_cfg_add_file(s, index, s->files->f[index].name, len); 914 915 s->files->count = cpu_to_be32(count+1); 916 } 917 918 void fw_cfg_add_file(FWCfgState *s, const char *filename, 919 void *data, size_t len) 920 { 921 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true); 922 } 923 924 void *fw_cfg_modify_file(FWCfgState *s, const char *filename, 925 void *data, size_t len) 926 { 927 int i, index; 928 void *ptr = NULL; 929 930 assert(s->files); 931 932 index = be32_to_cpu(s->files->count); 933 934 for (i = 0; i < index; i++) { 935 if (strcmp(filename, s->files->f[i].name) == 0) { 936 ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i, 937 data, len); 938 s->files->f[i].size = cpu_to_be32(len); 939 return ptr; 940 } 941 } 942 943 assert(index < fw_cfg_file_slots(s)); 944 945 /* add new one */ 946 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true); 947 return NULL; 948 } 949 950 static void fw_cfg_machine_reset(void *opaque) 951 { 952 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 953 FWCfgState *s = opaque; 954 void *ptr; 955 size_t len; 956 char *buf; 957 958 buf = get_boot_devices_list(&len); 959 ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)buf, len); 960 g_free(ptr); 961 962 if (!mc->legacy_fw_cfg_order) { 963 buf = get_boot_devices_lchs_list(&len); 964 ptr = fw_cfg_modify_file(s, "bios-geometry", (uint8_t *)buf, len); 965 g_free(ptr); 966 } 967 } 968 969 static void fw_cfg_machine_ready(struct Notifier *n, void *data) 970 { 971 FWCfgState *s = container_of(n, FWCfgState, machine_ready); 972 qemu_register_reset(fw_cfg_machine_reset, s); 973 } 974 975 976 977 static void fw_cfg_common_realize(DeviceState *dev, Error **errp) 978 { 979 FWCfgState *s = FW_CFG(dev); 980 MachineState *machine = MACHINE(qdev_get_machine()); 981 uint32_t version = FW_CFG_VERSION; 982 983 if (!fw_cfg_find()) { 984 error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG); 985 return; 986 } 987 988 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4); 989 fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16); 990 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics); 991 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu); 992 fw_cfg_bootsplash(s); 993 fw_cfg_reboot(s); 994 995 if (s->dma_enabled) { 996 version |= FW_CFG_VERSION_DMA; 997 } 998 999 fw_cfg_add_i32(s, FW_CFG_ID, version); 1000 1001 s->machine_ready.notify = fw_cfg_machine_ready; 1002 qemu_add_machine_init_done_notifier(&s->machine_ready); 1003 } 1004 1005 FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, 1006 AddressSpace *dma_as) 1007 { 1008 DeviceState *dev; 1009 SysBusDevice *sbd; 1010 FWCfgIoState *ios; 1011 FWCfgState *s; 1012 bool dma_requested = dma_iobase && dma_as; 1013 1014 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 1015 if (!dma_requested) { 1016 qdev_prop_set_bit(dev, "dma_enabled", false); 1017 } 1018 1019 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1020 OBJECT(dev), NULL); 1021 qdev_init_nofail(dev); 1022 1023 sbd = SYS_BUS_DEVICE(dev); 1024 ios = FW_CFG_IO(dev); 1025 sysbus_add_io(sbd, iobase, &ios->comb_iomem); 1026 1027 s = FW_CFG(dev); 1028 1029 if (s->dma_enabled) { 1030 /* 64 bits for the address field */ 1031 s->dma_as = dma_as; 1032 s->dma_addr = 0; 1033 sysbus_add_io(sbd, dma_iobase, &s->dma_iomem); 1034 } 1035 1036 return s; 1037 } 1038 1039 FWCfgState *fw_cfg_init_io(uint32_t iobase) 1040 { 1041 return fw_cfg_init_io_dma(iobase, 0, NULL); 1042 } 1043 1044 FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, 1045 hwaddr data_addr, uint32_t data_width, 1046 hwaddr dma_addr, AddressSpace *dma_as) 1047 { 1048 DeviceState *dev; 1049 SysBusDevice *sbd; 1050 FWCfgState *s; 1051 bool dma_requested = dma_addr && dma_as; 1052 1053 dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 1054 qdev_prop_set_uint32(dev, "data_width", data_width); 1055 if (!dma_requested) { 1056 qdev_prop_set_bit(dev, "dma_enabled", false); 1057 } 1058 1059 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1060 OBJECT(dev), NULL); 1061 qdev_init_nofail(dev); 1062 1063 sbd = SYS_BUS_DEVICE(dev); 1064 sysbus_mmio_map(sbd, 0, ctl_addr); 1065 sysbus_mmio_map(sbd, 1, data_addr); 1066 1067 s = FW_CFG(dev); 1068 1069 if (s->dma_enabled) { 1070 s->dma_as = dma_as; 1071 s->dma_addr = 0; 1072 sysbus_mmio_map(sbd, 2, dma_addr); 1073 } 1074 1075 return s; 1076 } 1077 1078 FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr) 1079 { 1080 return fw_cfg_init_mem_wide(ctl_addr, data_addr, 1081 fw_cfg_data_mem_ops.valid.max_access_size, 1082 0, NULL); 1083 } 1084 1085 1086 FWCfgState *fw_cfg_find(void) 1087 { 1088 /* Returns NULL unless there is exactly one fw_cfg device */ 1089 return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL)); 1090 } 1091 1092 1093 static void fw_cfg_class_init(ObjectClass *klass, void *data) 1094 { 1095 DeviceClass *dc = DEVICE_CLASS(klass); 1096 1097 dc->reset = fw_cfg_reset; 1098 dc->vmsd = &vmstate_fw_cfg; 1099 } 1100 1101 static const TypeInfo fw_cfg_info = { 1102 .name = TYPE_FW_CFG, 1103 .parent = TYPE_SYS_BUS_DEVICE, 1104 .abstract = true, 1105 .instance_size = sizeof(FWCfgState), 1106 .class_init = fw_cfg_class_init, 1107 }; 1108 1109 static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp) 1110 { 1111 uint16_t file_slots_max; 1112 1113 if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) { 1114 error_setg(errp, "\"file_slots\" must be at least 0x%x", 1115 FW_CFG_FILE_SLOTS_MIN); 1116 return; 1117 } 1118 1119 /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value 1120 * that we permit. The actual (exclusive) value coming from the 1121 * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */ 1122 file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1; 1123 if (fw_cfg_file_slots(s) > file_slots_max) { 1124 error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16, 1125 file_slots_max); 1126 return; 1127 } 1128 1129 s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s)); 1130 s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s)); 1131 s->entry_order = g_new0(int, fw_cfg_max_entry(s)); 1132 } 1133 1134 static Property fw_cfg_io_properties[] = { 1135 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled, 1136 true), 1137 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots, 1138 FW_CFG_FILE_SLOTS_DFLT), 1139 DEFINE_PROP_END_OF_LIST(), 1140 }; 1141 1142 static void fw_cfg_io_realize(DeviceState *dev, Error **errp) 1143 { 1144 FWCfgIoState *s = FW_CFG_IO(dev); 1145 Error *local_err = NULL; 1146 1147 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err); 1148 if (local_err) { 1149 error_propagate(errp, local_err); 1150 return; 1151 } 1152 1153 /* when using port i/o, the 8-bit data register ALWAYS overlaps 1154 * with half of the 16-bit control register. Hence, the total size 1155 * of the i/o region used is FW_CFG_CTL_SIZE */ 1156 memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops, 1157 FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE); 1158 1159 if (FW_CFG(s)->dma_enabled) { 1160 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), 1161 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", 1162 sizeof(dma_addr_t)); 1163 } 1164 1165 fw_cfg_common_realize(dev, errp); 1166 } 1167 1168 static void fw_cfg_io_class_init(ObjectClass *klass, void *data) 1169 { 1170 DeviceClass *dc = DEVICE_CLASS(klass); 1171 1172 dc->realize = fw_cfg_io_realize; 1173 dc->props = fw_cfg_io_properties; 1174 } 1175 1176 static const TypeInfo fw_cfg_io_info = { 1177 .name = TYPE_FW_CFG_IO, 1178 .parent = TYPE_FW_CFG, 1179 .instance_size = sizeof(FWCfgIoState), 1180 .class_init = fw_cfg_io_class_init, 1181 }; 1182 1183 1184 static Property fw_cfg_mem_properties[] = { 1185 DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1), 1186 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled, 1187 true), 1188 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots, 1189 FW_CFG_FILE_SLOTS_DFLT), 1190 DEFINE_PROP_END_OF_LIST(), 1191 }; 1192 1193 static void fw_cfg_mem_realize(DeviceState *dev, Error **errp) 1194 { 1195 FWCfgMemState *s = FW_CFG_MEM(dev); 1196 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1197 const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops; 1198 Error *local_err = NULL; 1199 1200 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err); 1201 if (local_err) { 1202 error_propagate(errp, local_err); 1203 return; 1204 } 1205 1206 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops, 1207 FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE); 1208 sysbus_init_mmio(sbd, &s->ctl_iomem); 1209 1210 if (s->data_width > data_ops->valid.max_access_size) { 1211 s->wide_data_ops = *data_ops; 1212 1213 s->wide_data_ops.valid.max_access_size = s->data_width; 1214 s->wide_data_ops.impl.max_access_size = s->data_width; 1215 data_ops = &s->wide_data_ops; 1216 } 1217 memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s), 1218 "fwcfg.data", data_ops->valid.max_access_size); 1219 sysbus_init_mmio(sbd, &s->data_iomem); 1220 1221 if (FW_CFG(s)->dma_enabled) { 1222 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), 1223 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", 1224 sizeof(dma_addr_t)); 1225 sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem); 1226 } 1227 1228 fw_cfg_common_realize(dev, errp); 1229 } 1230 1231 static void fw_cfg_mem_class_init(ObjectClass *klass, void *data) 1232 { 1233 DeviceClass *dc = DEVICE_CLASS(klass); 1234 1235 dc->realize = fw_cfg_mem_realize; 1236 dc->props = fw_cfg_mem_properties; 1237 } 1238 1239 static const TypeInfo fw_cfg_mem_info = { 1240 .name = TYPE_FW_CFG_MEM, 1241 .parent = TYPE_FW_CFG, 1242 .instance_size = sizeof(FWCfgMemState), 1243 .class_init = fw_cfg_mem_class_init, 1244 }; 1245 1246 1247 static void fw_cfg_register_types(void) 1248 { 1249 type_register_static(&fw_cfg_info); 1250 type_register_static(&fw_cfg_io_info); 1251 type_register_static(&fw_cfg_mem_info); 1252 } 1253 1254 type_init(fw_cfg_register_types) 1255