1 /* 2 * QEMU Firmware configuration device emulation 3 * 4 * Copyright (c) 2008 Gleb Natapov 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/dma.h" 29 #include "hw/boards.h" 30 #include "hw/isa/isa.h" 31 #include "hw/nvram/fw_cfg.h" 32 #include "hw/sysbus.h" 33 #include "trace.h" 34 #include "qemu/error-report.h" 35 #include "qemu/option.h" 36 #include "qemu/config-file.h" 37 #include "qemu/cutils.h" 38 #include "qapi/error.h" 39 40 #define FW_CFG_FILE_SLOTS_DFLT 0x20 41 42 /* FW_CFG_VERSION bits */ 43 #define FW_CFG_VERSION 0x01 44 #define FW_CFG_VERSION_DMA 0x02 45 46 /* FW_CFG_DMA_CONTROL bits */ 47 #define FW_CFG_DMA_CTL_ERROR 0x01 48 #define FW_CFG_DMA_CTL_READ 0x02 49 #define FW_CFG_DMA_CTL_SKIP 0x04 50 #define FW_CFG_DMA_CTL_SELECT 0x08 51 #define FW_CFG_DMA_CTL_WRITE 0x10 52 53 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */ 54 55 struct FWCfgEntry { 56 uint32_t len; 57 bool allow_write; 58 uint8_t *data; 59 void *callback_opaque; 60 FWCfgCallback select_cb; 61 FWCfgWriteCallback write_cb; 62 }; 63 64 #define JPG_FILE 0 65 #define BMP_FILE 1 66 67 static char *read_splashfile(char *filename, gsize *file_sizep, 68 int *file_typep) 69 { 70 GError *err = NULL; 71 gboolean res; 72 gchar *content; 73 int file_type; 74 unsigned int filehead; 75 int bmp_bpp; 76 77 res = g_file_get_contents(filename, &content, file_sizep, &err); 78 if (res == FALSE) { 79 error_report("failed to read splash file '%s'", filename); 80 g_error_free(err); 81 return NULL; 82 } 83 84 /* check file size */ 85 if (*file_sizep < 30) { 86 goto error; 87 } 88 89 /* check magic ID */ 90 filehead = ((content[0] & 0xff) + (content[1] << 8)) & 0xffff; 91 if (filehead == 0xd8ff) { 92 file_type = JPG_FILE; 93 } else if (filehead == 0x4d42) { 94 file_type = BMP_FILE; 95 } else { 96 goto error; 97 } 98 99 /* check BMP bpp */ 100 if (file_type == BMP_FILE) { 101 bmp_bpp = (content[28] + (content[29] << 8)) & 0xffff; 102 if (bmp_bpp != 24) { 103 goto error; 104 } 105 } 106 107 /* return values */ 108 *file_typep = file_type; 109 110 return content; 111 112 error: 113 error_report("splash file '%s' format not recognized; must be JPEG " 114 "or 24 bit BMP", filename); 115 g_free(content); 116 return NULL; 117 } 118 119 static void fw_cfg_bootsplash(FWCfgState *s) 120 { 121 int boot_splash_time = -1; 122 const char *boot_splash_filename = NULL; 123 char *p; 124 char *filename, *file_data; 125 gsize file_size; 126 int file_type; 127 const char *temp; 128 129 /* get user configuration */ 130 QemuOptsList *plist = qemu_find_opts("boot-opts"); 131 QemuOpts *opts = QTAILQ_FIRST(&plist->head); 132 if (opts != NULL) { 133 temp = qemu_opt_get(opts, "splash"); 134 if (temp != NULL) { 135 boot_splash_filename = temp; 136 } 137 temp = qemu_opt_get(opts, "splash-time"); 138 if (temp != NULL) { 139 p = (char *)temp; 140 boot_splash_time = strtol(p, &p, 10); 141 } 142 } 143 144 /* insert splash time if user configurated */ 145 if (boot_splash_time >= 0) { 146 /* validate the input */ 147 if (boot_splash_time > 0xffff) { 148 error_report("splash time is big than 65535, force it to 65535."); 149 boot_splash_time = 0xffff; 150 } 151 /* use little endian format */ 152 qemu_extra_params_fw[0] = (uint8_t)(boot_splash_time & 0xff); 153 qemu_extra_params_fw[1] = (uint8_t)((boot_splash_time >> 8) & 0xff); 154 fw_cfg_add_file(s, "etc/boot-menu-wait", qemu_extra_params_fw, 2); 155 } 156 157 /* insert splash file if user configurated */ 158 if (boot_splash_filename != NULL) { 159 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename); 160 if (filename == NULL) { 161 error_report("failed to find file '%s'.", boot_splash_filename); 162 return; 163 } 164 165 /* loading file data */ 166 file_data = read_splashfile(filename, &file_size, &file_type); 167 if (file_data == NULL) { 168 g_free(filename); 169 return; 170 } 171 g_free(boot_splash_filedata); 172 boot_splash_filedata = (uint8_t *)file_data; 173 boot_splash_filedata_size = file_size; 174 175 /* insert data */ 176 if (file_type == JPG_FILE) { 177 fw_cfg_add_file(s, "bootsplash.jpg", 178 boot_splash_filedata, boot_splash_filedata_size); 179 } else { 180 fw_cfg_add_file(s, "bootsplash.bmp", 181 boot_splash_filedata, boot_splash_filedata_size); 182 } 183 g_free(filename); 184 } 185 } 186 187 static void fw_cfg_reboot(FWCfgState *s) 188 { 189 int reboot_timeout = -1; 190 char *p; 191 const char *temp; 192 193 /* get user configuration */ 194 QemuOptsList *plist = qemu_find_opts("boot-opts"); 195 QemuOpts *opts = QTAILQ_FIRST(&plist->head); 196 if (opts != NULL) { 197 temp = qemu_opt_get(opts, "reboot-timeout"); 198 if (temp != NULL) { 199 p = (char *)temp; 200 reboot_timeout = strtol(p, &p, 10); 201 } 202 } 203 /* validate the input */ 204 if (reboot_timeout > 0xffff) { 205 error_report("reboot timeout is larger than 65535, force it to 65535."); 206 reboot_timeout = 0xffff; 207 } 208 fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&reboot_timeout, 4), 4); 209 } 210 211 static void fw_cfg_write(FWCfgState *s, uint8_t value) 212 { 213 /* nothing, write support removed in QEMU v2.4+ */ 214 } 215 216 static inline uint16_t fw_cfg_file_slots(const FWCfgState *s) 217 { 218 return s->file_slots; 219 } 220 221 /* Note: this function returns an exclusive limit. */ 222 static inline uint32_t fw_cfg_max_entry(const FWCfgState *s) 223 { 224 return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s); 225 } 226 227 static int fw_cfg_select(FWCfgState *s, uint16_t key) 228 { 229 int arch, ret; 230 FWCfgEntry *e; 231 232 s->cur_offset = 0; 233 if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) { 234 s->cur_entry = FW_CFG_INVALID; 235 ret = 0; 236 } else { 237 s->cur_entry = key; 238 ret = 1; 239 /* entry successfully selected, now run callback if present */ 240 arch = !!(key & FW_CFG_ARCH_LOCAL); 241 e = &s->entries[arch][key & FW_CFG_ENTRY_MASK]; 242 if (e->select_cb) { 243 e->select_cb(e->callback_opaque); 244 } 245 } 246 247 trace_fw_cfg_select(s, key, ret); 248 return ret; 249 } 250 251 static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size) 252 { 253 FWCfgState *s = opaque; 254 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); 255 FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL : 256 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; 257 uint64_t value = 0; 258 259 assert(size > 0 && size <= sizeof(value)); 260 if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) { 261 /* The least significant 'size' bytes of the return value are 262 * expected to contain a string preserving portion of the item 263 * data, padded with zeros on the right in case we run out early. 264 * In technical terms, we're composing the host-endian representation 265 * of the big endian interpretation of the fw_cfg string. 266 */ 267 do { 268 value = (value << 8) | e->data[s->cur_offset++]; 269 } while (--size && s->cur_offset < e->len); 270 /* If size is still not zero, we *did* run out early, so continue 271 * left-shifting, to add the appropriate number of padding zeros 272 * on the right. 273 */ 274 value <<= 8 * size; 275 } 276 277 trace_fw_cfg_read(s, value); 278 return value; 279 } 280 281 static void fw_cfg_data_mem_write(void *opaque, hwaddr addr, 282 uint64_t value, unsigned size) 283 { 284 FWCfgState *s = opaque; 285 unsigned i = size; 286 287 do { 288 fw_cfg_write(s, value >> (8 * --i)); 289 } while (i); 290 } 291 292 static void fw_cfg_dma_transfer(FWCfgState *s) 293 { 294 dma_addr_t len; 295 FWCfgDmaAccess dma; 296 int arch; 297 FWCfgEntry *e; 298 int read = 0, write = 0; 299 dma_addr_t dma_addr; 300 301 /* Reset the address before the next access */ 302 dma_addr = s->dma_addr; 303 s->dma_addr = 0; 304 305 if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) { 306 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), 307 FW_CFG_DMA_CTL_ERROR); 308 return; 309 } 310 311 dma.address = be64_to_cpu(dma.address); 312 dma.length = be32_to_cpu(dma.length); 313 dma.control = be32_to_cpu(dma.control); 314 315 if (dma.control & FW_CFG_DMA_CTL_SELECT) { 316 fw_cfg_select(s, dma.control >> 16); 317 } 318 319 arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); 320 e = (s->cur_entry == FW_CFG_INVALID) ? NULL : 321 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; 322 323 if (dma.control & FW_CFG_DMA_CTL_READ) { 324 read = 1; 325 write = 0; 326 } else if (dma.control & FW_CFG_DMA_CTL_WRITE) { 327 read = 0; 328 write = 1; 329 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) { 330 read = 0; 331 write = 0; 332 } else { 333 dma.length = 0; 334 } 335 336 dma.control = 0; 337 338 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) { 339 if (s->cur_entry == FW_CFG_INVALID || !e->data || 340 s->cur_offset >= e->len) { 341 len = dma.length; 342 343 /* If the access is not a read access, it will be a skip access, 344 * tested before. 345 */ 346 if (read) { 347 if (dma_memory_set(s->dma_as, dma.address, 0, len)) { 348 dma.control |= FW_CFG_DMA_CTL_ERROR; 349 } 350 } 351 if (write) { 352 dma.control |= FW_CFG_DMA_CTL_ERROR; 353 } 354 } else { 355 if (dma.length <= (e->len - s->cur_offset)) { 356 len = dma.length; 357 } else { 358 len = (e->len - s->cur_offset); 359 } 360 361 /* If the access is not a read access, it will be a skip access, 362 * tested before. 363 */ 364 if (read) { 365 if (dma_memory_write(s->dma_as, dma.address, 366 &e->data[s->cur_offset], len)) { 367 dma.control |= FW_CFG_DMA_CTL_ERROR; 368 } 369 } 370 if (write) { 371 if (!e->allow_write || 372 len != dma.length || 373 dma_memory_read(s->dma_as, dma.address, 374 &e->data[s->cur_offset], len)) { 375 dma.control |= FW_CFG_DMA_CTL_ERROR; 376 } else if (e->write_cb) { 377 e->write_cb(e->callback_opaque, s->cur_offset, len); 378 } 379 } 380 381 s->cur_offset += len; 382 } 383 384 dma.address += len; 385 dma.length -= len; 386 387 } 388 389 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), 390 dma.control); 391 392 trace_fw_cfg_read(s, 0); 393 } 394 395 static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr, 396 unsigned size) 397 { 398 /* Return a signature value (and handle various read sizes) */ 399 return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8); 400 } 401 402 static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr, 403 uint64_t value, unsigned size) 404 { 405 FWCfgState *s = opaque; 406 407 if (size == 4) { 408 if (addr == 0) { 409 /* FWCfgDmaAccess high address */ 410 s->dma_addr = value << 32; 411 } else if (addr == 4) { 412 /* FWCfgDmaAccess low address */ 413 s->dma_addr |= value; 414 fw_cfg_dma_transfer(s); 415 } 416 } else if (size == 8 && addr == 0) { 417 s->dma_addr = value; 418 fw_cfg_dma_transfer(s); 419 } 420 } 421 422 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr, 423 unsigned size, bool is_write, 424 MemTxAttrs attrs) 425 { 426 return !is_write || ((size == 4 && (addr == 0 || addr == 4)) || 427 (size == 8 && addr == 0)); 428 } 429 430 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr, 431 unsigned size, bool is_write, 432 MemTxAttrs attrs) 433 { 434 return addr == 0; 435 } 436 437 static uint64_t fw_cfg_ctl_mem_read(void *opaque, hwaddr addr, unsigned size) 438 { 439 return 0; 440 } 441 442 static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr, 443 uint64_t value, unsigned size) 444 { 445 fw_cfg_select(opaque, (uint16_t)value); 446 } 447 448 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr, 449 unsigned size, bool is_write, 450 MemTxAttrs attrs) 451 { 452 return is_write && size == 2; 453 } 454 455 static void fw_cfg_comb_write(void *opaque, hwaddr addr, 456 uint64_t value, unsigned size) 457 { 458 switch (size) { 459 case 1: 460 fw_cfg_write(opaque, (uint8_t)value); 461 break; 462 case 2: 463 fw_cfg_select(opaque, (uint16_t)value); 464 break; 465 } 466 } 467 468 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr, 469 unsigned size, bool is_write, 470 MemTxAttrs attrs) 471 { 472 return (size == 1) || (is_write && size == 2); 473 } 474 475 static const MemoryRegionOps fw_cfg_ctl_mem_ops = { 476 .read = fw_cfg_ctl_mem_read, 477 .write = fw_cfg_ctl_mem_write, 478 .endianness = DEVICE_BIG_ENDIAN, 479 .valid.accepts = fw_cfg_ctl_mem_valid, 480 }; 481 482 static const MemoryRegionOps fw_cfg_data_mem_ops = { 483 .read = fw_cfg_data_read, 484 .write = fw_cfg_data_mem_write, 485 .endianness = DEVICE_BIG_ENDIAN, 486 .valid = { 487 .min_access_size = 1, 488 .max_access_size = 1, 489 .accepts = fw_cfg_data_mem_valid, 490 }, 491 }; 492 493 static const MemoryRegionOps fw_cfg_comb_mem_ops = { 494 .read = fw_cfg_data_read, 495 .write = fw_cfg_comb_write, 496 .endianness = DEVICE_LITTLE_ENDIAN, 497 .valid.accepts = fw_cfg_comb_valid, 498 }; 499 500 static const MemoryRegionOps fw_cfg_dma_mem_ops = { 501 .read = fw_cfg_dma_mem_read, 502 .write = fw_cfg_dma_mem_write, 503 .endianness = DEVICE_BIG_ENDIAN, 504 .valid.accepts = fw_cfg_dma_mem_valid, 505 .valid.max_access_size = 8, 506 .impl.max_access_size = 8, 507 }; 508 509 static void fw_cfg_reset(DeviceState *d) 510 { 511 FWCfgState *s = FW_CFG(d); 512 513 /* we never register a read callback for FW_CFG_SIGNATURE */ 514 fw_cfg_select(s, FW_CFG_SIGNATURE); 515 } 516 517 /* Save restore 32 bit int as uint16_t 518 This is a Big hack, but it is how the old state did it. 519 Or we broke compatibility in the state, or we can't use struct tm 520 */ 521 522 static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size, 523 VMStateField *field) 524 { 525 uint32_t *v = pv; 526 *v = qemu_get_be16(f); 527 return 0; 528 } 529 530 static int put_unused(QEMUFile *f, void *pv, size_t size, VMStateField *field, 531 QJSON *vmdesc) 532 { 533 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n"); 534 fprintf(stderr, "This functions shouldn't be called.\n"); 535 536 return 0; 537 } 538 539 static const VMStateInfo vmstate_hack_uint32_as_uint16 = { 540 .name = "int32_as_uint16", 541 .get = get_uint32_as_uint16, 542 .put = put_unused, 543 }; 544 545 #define VMSTATE_UINT16_HACK(_f, _s, _t) \ 546 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t) 547 548 549 static bool is_version_1(void *opaque, int version_id) 550 { 551 return version_id == 1; 552 } 553 554 bool fw_cfg_dma_enabled(void *opaque) 555 { 556 FWCfgState *s = opaque; 557 558 return s->dma_enabled; 559 } 560 561 static const VMStateDescription vmstate_fw_cfg_dma = { 562 .name = "fw_cfg/dma", 563 .needed = fw_cfg_dma_enabled, 564 .fields = (VMStateField[]) { 565 VMSTATE_UINT64(dma_addr, FWCfgState), 566 VMSTATE_END_OF_LIST() 567 }, 568 }; 569 570 static const VMStateDescription vmstate_fw_cfg = { 571 .name = "fw_cfg", 572 .version_id = 2, 573 .minimum_version_id = 1, 574 .fields = (VMStateField[]) { 575 VMSTATE_UINT16(cur_entry, FWCfgState), 576 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1), 577 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2), 578 VMSTATE_END_OF_LIST() 579 }, 580 .subsections = (const VMStateDescription*[]) { 581 &vmstate_fw_cfg_dma, 582 NULL, 583 } 584 }; 585 586 static void fw_cfg_add_bytes_callback(FWCfgState *s, uint16_t key, 587 FWCfgCallback select_cb, 588 FWCfgWriteCallback write_cb, 589 void *callback_opaque, 590 void *data, size_t len, 591 bool read_only) 592 { 593 int arch = !!(key & FW_CFG_ARCH_LOCAL); 594 595 key &= FW_CFG_ENTRY_MASK; 596 597 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX); 598 assert(s->entries[arch][key].data == NULL); /* avoid key conflict */ 599 600 s->entries[arch][key].data = data; 601 s->entries[arch][key].len = (uint32_t)len; 602 s->entries[arch][key].select_cb = select_cb; 603 s->entries[arch][key].write_cb = write_cb; 604 s->entries[arch][key].callback_opaque = callback_opaque; 605 s->entries[arch][key].allow_write = !read_only; 606 } 607 608 static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key, 609 void *data, size_t len) 610 { 611 void *ptr; 612 int arch = !!(key & FW_CFG_ARCH_LOCAL); 613 614 key &= FW_CFG_ENTRY_MASK; 615 616 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX); 617 618 /* return the old data to the function caller, avoid memory leak */ 619 ptr = s->entries[arch][key].data; 620 s->entries[arch][key].data = data; 621 s->entries[arch][key].len = len; 622 s->entries[arch][key].callback_opaque = NULL; 623 s->entries[arch][key].allow_write = false; 624 625 return ptr; 626 } 627 628 void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len) 629 { 630 fw_cfg_add_bytes_callback(s, key, NULL, NULL, NULL, data, len, true); 631 } 632 633 void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value) 634 { 635 size_t sz = strlen(value) + 1; 636 637 fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz); 638 } 639 640 void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value) 641 { 642 uint16_t *copy; 643 644 copy = g_malloc(sizeof(value)); 645 *copy = cpu_to_le16(value); 646 fw_cfg_add_bytes(s, key, copy, sizeof(value)); 647 } 648 649 void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value) 650 { 651 uint16_t *copy, *old; 652 653 copy = g_malloc(sizeof(value)); 654 *copy = cpu_to_le16(value); 655 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); 656 g_free(old); 657 } 658 659 void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value) 660 { 661 uint32_t *copy; 662 663 copy = g_malloc(sizeof(value)); 664 *copy = cpu_to_le32(value); 665 fw_cfg_add_bytes(s, key, copy, sizeof(value)); 666 } 667 668 void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value) 669 { 670 uint64_t *copy; 671 672 copy = g_malloc(sizeof(value)); 673 *copy = cpu_to_le64(value); 674 fw_cfg_add_bytes(s, key, copy, sizeof(value)); 675 } 676 677 void fw_cfg_set_order_override(FWCfgState *s, int order) 678 { 679 assert(s->fw_cfg_order_override == 0); 680 s->fw_cfg_order_override = order; 681 } 682 683 void fw_cfg_reset_order_override(FWCfgState *s) 684 { 685 assert(s->fw_cfg_order_override != 0); 686 s->fw_cfg_order_override = 0; 687 } 688 689 /* 690 * This is the legacy order list. For legacy systems, files are in 691 * the fw_cfg in the order defined below, by the "order" value. Note 692 * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a 693 * specific area, but there may be more than one and they occur in the 694 * order that the user specifies them on the command line. Those are 695 * handled in a special manner, using the order override above. 696 * 697 * For non-legacy, the files are sorted by filename to avoid this kind 698 * of complexity in the future. 699 * 700 * This is only for x86, other arches don't implement versioning so 701 * they won't set legacy mode. 702 */ 703 static struct { 704 const char *name; 705 int order; 706 } fw_cfg_order[] = { 707 { "etc/boot-menu-wait", 10 }, 708 { "bootsplash.jpg", 11 }, 709 { "bootsplash.bmp", 12 }, 710 { "etc/boot-fail-wait", 15 }, 711 { "etc/smbios/smbios-tables", 20 }, 712 { "etc/smbios/smbios-anchor", 30 }, 713 { "etc/e820", 40 }, 714 { "etc/reserved-memory-end", 50 }, 715 { "genroms/kvmvapic.bin", 55 }, 716 { "genroms/linuxboot.bin", 60 }, 717 { }, /* VGA ROMs from pc_vga_init come here, 70. */ 718 { }, /* NIC option ROMs from pc_nic_init come here, 80. */ 719 { "etc/system-states", 90 }, 720 { }, /* User ROMs come here, 100. */ 721 { }, /* Device FW comes here, 110. */ 722 { "etc/extra-pci-roots", 120 }, 723 { "etc/acpi/tables", 130 }, 724 { "etc/table-loader", 140 }, 725 { "etc/tpm/log", 150 }, 726 { "etc/acpi/rsdp", 160 }, 727 { "bootorder", 170 }, 728 729 #define FW_CFG_ORDER_OVERRIDE_LAST 200 730 }; 731 732 static int get_fw_cfg_order(FWCfgState *s, const char *name) 733 { 734 int i; 735 736 if (s->fw_cfg_order_override > 0) { 737 return s->fw_cfg_order_override; 738 } 739 740 for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) { 741 if (fw_cfg_order[i].name == NULL) { 742 continue; 743 } 744 745 if (strcmp(name, fw_cfg_order[i].name) == 0) { 746 return fw_cfg_order[i].order; 747 } 748 } 749 750 /* Stick unknown stuff at the end. */ 751 warn_report("Unknown firmware file in legacy mode: %s", name); 752 return FW_CFG_ORDER_OVERRIDE_LAST; 753 } 754 755 void fw_cfg_add_file_callback(FWCfgState *s, const char *filename, 756 FWCfgCallback select_cb, 757 FWCfgWriteCallback write_cb, 758 void *callback_opaque, 759 void *data, size_t len, bool read_only) 760 { 761 int i, index, count; 762 size_t dsize; 763 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 764 int order = 0; 765 766 if (!s->files) { 767 dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s); 768 s->files = g_malloc0(dsize); 769 fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize); 770 } 771 772 count = be32_to_cpu(s->files->count); 773 assert(count < fw_cfg_file_slots(s)); 774 775 /* Find the insertion point. */ 776 if (mc->legacy_fw_cfg_order) { 777 /* 778 * Sort by order. For files with the same order, we keep them 779 * in the sequence in which they were added. 780 */ 781 order = get_fw_cfg_order(s, filename); 782 for (index = count; 783 index > 0 && order < s->entry_order[index - 1]; 784 index--); 785 } else { 786 /* Sort by file name. */ 787 for (index = count; 788 index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0; 789 index--); 790 } 791 792 /* 793 * Move all the entries from the index point and after down one 794 * to create a slot for the new entry. Because calculations are 795 * being done with the index, make it so that "i" is the current 796 * index and "i - 1" is the one being copied from, thus the 797 * unusual start and end in the for statement. 798 */ 799 for (i = count; i > index; i--) { 800 s->files->f[i] = s->files->f[i - 1]; 801 s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i); 802 s->entries[0][FW_CFG_FILE_FIRST + i] = 803 s->entries[0][FW_CFG_FILE_FIRST + i - 1]; 804 s->entry_order[i] = s->entry_order[i - 1]; 805 } 806 807 memset(&s->files->f[index], 0, sizeof(FWCfgFile)); 808 memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry)); 809 810 pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename); 811 for (i = 0; i <= count; i++) { 812 if (i != index && 813 strcmp(s->files->f[index].name, s->files->f[i].name) == 0) { 814 error_report("duplicate fw_cfg file name: %s", 815 s->files->f[index].name); 816 exit(1); 817 } 818 } 819 820 fw_cfg_add_bytes_callback(s, FW_CFG_FILE_FIRST + index, 821 select_cb, write_cb, 822 callback_opaque, data, len, 823 read_only); 824 825 s->files->f[index].size = cpu_to_be32(len); 826 s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index); 827 s->entry_order[index] = order; 828 trace_fw_cfg_add_file(s, index, s->files->f[index].name, len); 829 830 s->files->count = cpu_to_be32(count+1); 831 } 832 833 void fw_cfg_add_file(FWCfgState *s, const char *filename, 834 void *data, size_t len) 835 { 836 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true); 837 } 838 839 void *fw_cfg_modify_file(FWCfgState *s, const char *filename, 840 void *data, size_t len) 841 { 842 int i, index; 843 void *ptr = NULL; 844 845 assert(s->files); 846 847 index = be32_to_cpu(s->files->count); 848 849 for (i = 0; i < index; i++) { 850 if (strcmp(filename, s->files->f[i].name) == 0) { 851 ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i, 852 data, len); 853 s->files->f[i].size = cpu_to_be32(len); 854 return ptr; 855 } 856 } 857 858 assert(index < fw_cfg_file_slots(s)); 859 860 /* add new one */ 861 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true); 862 return NULL; 863 } 864 865 static void fw_cfg_machine_reset(void *opaque) 866 { 867 void *ptr; 868 size_t len; 869 FWCfgState *s = opaque; 870 char *bootindex = get_boot_devices_list(&len); 871 872 ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)bootindex, len); 873 g_free(ptr); 874 } 875 876 static void fw_cfg_machine_ready(struct Notifier *n, void *data) 877 { 878 FWCfgState *s = container_of(n, FWCfgState, machine_ready); 879 qemu_register_reset(fw_cfg_machine_reset, s); 880 } 881 882 883 884 static void fw_cfg_common_realize(DeviceState *dev, Error **errp) 885 { 886 FWCfgState *s = FW_CFG(dev); 887 MachineState *machine = MACHINE(qdev_get_machine()); 888 uint32_t version = FW_CFG_VERSION; 889 890 if (!fw_cfg_find()) { 891 error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG); 892 return; 893 } 894 895 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4); 896 fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16); 897 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics); 898 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu); 899 fw_cfg_bootsplash(s); 900 fw_cfg_reboot(s); 901 902 if (s->dma_enabled) { 903 version |= FW_CFG_VERSION_DMA; 904 } 905 906 fw_cfg_add_i32(s, FW_CFG_ID, version); 907 908 s->machine_ready.notify = fw_cfg_machine_ready; 909 qemu_add_machine_init_done_notifier(&s->machine_ready); 910 } 911 912 FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, 913 AddressSpace *dma_as) 914 { 915 DeviceState *dev; 916 SysBusDevice *sbd; 917 FWCfgIoState *ios; 918 FWCfgState *s; 919 bool dma_requested = dma_iobase && dma_as; 920 921 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 922 if (!dma_requested) { 923 qdev_prop_set_bit(dev, "dma_enabled", false); 924 } 925 926 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 927 OBJECT(dev), NULL); 928 qdev_init_nofail(dev); 929 930 sbd = SYS_BUS_DEVICE(dev); 931 ios = FW_CFG_IO(dev); 932 sysbus_add_io(sbd, iobase, &ios->comb_iomem); 933 934 s = FW_CFG(dev); 935 936 if (s->dma_enabled) { 937 /* 64 bits for the address field */ 938 s->dma_as = dma_as; 939 s->dma_addr = 0; 940 sysbus_add_io(sbd, dma_iobase, &s->dma_iomem); 941 } 942 943 return s; 944 } 945 946 FWCfgState *fw_cfg_init_io(uint32_t iobase) 947 { 948 return fw_cfg_init_io_dma(iobase, 0, NULL); 949 } 950 951 FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, 952 hwaddr data_addr, uint32_t data_width, 953 hwaddr dma_addr, AddressSpace *dma_as) 954 { 955 DeviceState *dev; 956 SysBusDevice *sbd; 957 FWCfgState *s; 958 bool dma_requested = dma_addr && dma_as; 959 960 dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 961 qdev_prop_set_uint32(dev, "data_width", data_width); 962 if (!dma_requested) { 963 qdev_prop_set_bit(dev, "dma_enabled", false); 964 } 965 966 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 967 OBJECT(dev), NULL); 968 qdev_init_nofail(dev); 969 970 sbd = SYS_BUS_DEVICE(dev); 971 sysbus_mmio_map(sbd, 0, ctl_addr); 972 sysbus_mmio_map(sbd, 1, data_addr); 973 974 s = FW_CFG(dev); 975 976 if (s->dma_enabled) { 977 s->dma_as = dma_as; 978 s->dma_addr = 0; 979 sysbus_mmio_map(sbd, 2, dma_addr); 980 } 981 982 return s; 983 } 984 985 FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr) 986 { 987 return fw_cfg_init_mem_wide(ctl_addr, data_addr, 988 fw_cfg_data_mem_ops.valid.max_access_size, 989 0, NULL); 990 } 991 992 993 FWCfgState *fw_cfg_find(void) 994 { 995 /* Returns NULL unless there is exactly one fw_cfg device */ 996 return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL)); 997 } 998 999 1000 static void fw_cfg_class_init(ObjectClass *klass, void *data) 1001 { 1002 DeviceClass *dc = DEVICE_CLASS(klass); 1003 1004 dc->reset = fw_cfg_reset; 1005 dc->vmsd = &vmstate_fw_cfg; 1006 } 1007 1008 static const TypeInfo fw_cfg_info = { 1009 .name = TYPE_FW_CFG, 1010 .parent = TYPE_SYS_BUS_DEVICE, 1011 .abstract = true, 1012 .instance_size = sizeof(FWCfgState), 1013 .class_init = fw_cfg_class_init, 1014 }; 1015 1016 static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp) 1017 { 1018 uint16_t file_slots_max; 1019 1020 if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) { 1021 error_setg(errp, "\"file_slots\" must be at least 0x%x", 1022 FW_CFG_FILE_SLOTS_MIN); 1023 return; 1024 } 1025 1026 /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value 1027 * that we permit. The actual (exclusive) value coming from the 1028 * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */ 1029 file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1; 1030 if (fw_cfg_file_slots(s) > file_slots_max) { 1031 error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16, 1032 file_slots_max); 1033 return; 1034 } 1035 1036 s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s)); 1037 s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s)); 1038 s->entry_order = g_new0(int, fw_cfg_max_entry(s)); 1039 } 1040 1041 static Property fw_cfg_io_properties[] = { 1042 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled, 1043 true), 1044 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots, 1045 FW_CFG_FILE_SLOTS_DFLT), 1046 DEFINE_PROP_END_OF_LIST(), 1047 }; 1048 1049 static void fw_cfg_io_realize(DeviceState *dev, Error **errp) 1050 { 1051 FWCfgIoState *s = FW_CFG_IO(dev); 1052 Error *local_err = NULL; 1053 1054 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err); 1055 if (local_err) { 1056 error_propagate(errp, local_err); 1057 return; 1058 } 1059 1060 /* when using port i/o, the 8-bit data register ALWAYS overlaps 1061 * with half of the 16-bit control register. Hence, the total size 1062 * of the i/o region used is FW_CFG_CTL_SIZE */ 1063 memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops, 1064 FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE); 1065 1066 if (FW_CFG(s)->dma_enabled) { 1067 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), 1068 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", 1069 sizeof(dma_addr_t)); 1070 } 1071 1072 fw_cfg_common_realize(dev, errp); 1073 } 1074 1075 static void fw_cfg_io_class_init(ObjectClass *klass, void *data) 1076 { 1077 DeviceClass *dc = DEVICE_CLASS(klass); 1078 1079 dc->realize = fw_cfg_io_realize; 1080 dc->props = fw_cfg_io_properties; 1081 } 1082 1083 static const TypeInfo fw_cfg_io_info = { 1084 .name = TYPE_FW_CFG_IO, 1085 .parent = TYPE_FW_CFG, 1086 .instance_size = sizeof(FWCfgIoState), 1087 .class_init = fw_cfg_io_class_init, 1088 }; 1089 1090 1091 static Property fw_cfg_mem_properties[] = { 1092 DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1), 1093 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled, 1094 true), 1095 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots, 1096 FW_CFG_FILE_SLOTS_DFLT), 1097 DEFINE_PROP_END_OF_LIST(), 1098 }; 1099 1100 static void fw_cfg_mem_realize(DeviceState *dev, Error **errp) 1101 { 1102 FWCfgMemState *s = FW_CFG_MEM(dev); 1103 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1104 const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops; 1105 Error *local_err = NULL; 1106 1107 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err); 1108 if (local_err) { 1109 error_propagate(errp, local_err); 1110 return; 1111 } 1112 1113 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops, 1114 FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE); 1115 sysbus_init_mmio(sbd, &s->ctl_iomem); 1116 1117 if (s->data_width > data_ops->valid.max_access_size) { 1118 s->wide_data_ops = *data_ops; 1119 1120 s->wide_data_ops.valid.max_access_size = s->data_width; 1121 s->wide_data_ops.impl.max_access_size = s->data_width; 1122 data_ops = &s->wide_data_ops; 1123 } 1124 memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s), 1125 "fwcfg.data", data_ops->valid.max_access_size); 1126 sysbus_init_mmio(sbd, &s->data_iomem); 1127 1128 if (FW_CFG(s)->dma_enabled) { 1129 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), 1130 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", 1131 sizeof(dma_addr_t)); 1132 sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem); 1133 } 1134 1135 fw_cfg_common_realize(dev, errp); 1136 } 1137 1138 static void fw_cfg_mem_class_init(ObjectClass *klass, void *data) 1139 { 1140 DeviceClass *dc = DEVICE_CLASS(klass); 1141 1142 dc->realize = fw_cfg_mem_realize; 1143 dc->props = fw_cfg_mem_properties; 1144 } 1145 1146 static const TypeInfo fw_cfg_mem_info = { 1147 .name = TYPE_FW_CFG_MEM, 1148 .parent = TYPE_FW_CFG, 1149 .instance_size = sizeof(FWCfgMemState), 1150 .class_init = fw_cfg_mem_class_init, 1151 }; 1152 1153 1154 static void fw_cfg_register_types(void) 1155 { 1156 type_register_static(&fw_cfg_info); 1157 type_register_static(&fw_cfg_io_info); 1158 type_register_static(&fw_cfg_mem_info); 1159 } 1160 1161 type_init(fw_cfg_register_types) 1162