1 /* 2 * QEMU model of the Xilinx Ethernet Lite MAC. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/sysbus.h" 26 #include "hw/hw.h" 27 #include "net/net.h" 28 29 #define D(x) 30 #define R_TX_BUF0 0 31 #define R_TX_LEN0 (0x07f4 / 4) 32 #define R_TX_GIE0 (0x07f8 / 4) 33 #define R_TX_CTRL0 (0x07fc / 4) 34 #define R_TX_BUF1 (0x0800 / 4) 35 #define R_TX_LEN1 (0x0ff4 / 4) 36 #define R_TX_CTRL1 (0x0ffc / 4) 37 38 #define R_RX_BUF0 (0x1000 / 4) 39 #define R_RX_CTRL0 (0x17fc / 4) 40 #define R_RX_BUF1 (0x1800 / 4) 41 #define R_RX_CTRL1 (0x1ffc / 4) 42 #define R_MAX (0x2000 / 4) 43 44 #define GIE_GIE 0x80000000 45 46 #define CTRL_I 0x8 47 #define CTRL_P 0x2 48 #define CTRL_S 0x1 49 50 struct xlx_ethlite 51 { 52 SysBusDevice busdev; 53 MemoryRegion mmio; 54 qemu_irq irq; 55 NICState *nic; 56 NICConf conf; 57 58 uint32_t c_tx_pingpong; 59 uint32_t c_rx_pingpong; 60 unsigned int txbuf; 61 unsigned int rxbuf; 62 63 uint32_t regs[R_MAX]; 64 }; 65 66 static inline void eth_pulse_irq(struct xlx_ethlite *s) 67 { 68 /* Only the first gie reg is active. */ 69 if (s->regs[R_TX_GIE0] & GIE_GIE) { 70 qemu_irq_pulse(s->irq); 71 } 72 } 73 74 static uint64_t 75 eth_read(void *opaque, hwaddr addr, unsigned int size) 76 { 77 struct xlx_ethlite *s = opaque; 78 uint32_t r = 0; 79 80 addr >>= 2; 81 82 switch (addr) 83 { 84 case R_TX_GIE0: 85 case R_TX_LEN0: 86 case R_TX_LEN1: 87 case R_TX_CTRL1: 88 case R_TX_CTRL0: 89 case R_RX_CTRL1: 90 case R_RX_CTRL0: 91 r = s->regs[addr]; 92 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r)); 93 break; 94 95 default: 96 r = tswap32(s->regs[addr]); 97 break; 98 } 99 return r; 100 } 101 102 static void 103 eth_write(void *opaque, hwaddr addr, 104 uint64_t val64, unsigned int size) 105 { 106 struct xlx_ethlite *s = opaque; 107 unsigned int base = 0; 108 uint32_t value = val64; 109 110 addr >>= 2; 111 switch (addr) 112 { 113 case R_TX_CTRL0: 114 case R_TX_CTRL1: 115 if (addr == R_TX_CTRL1) 116 base = 0x800 / 4; 117 118 D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n", 119 __func__, addr * 4, value)); 120 if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { 121 qemu_send_packet(qemu_get_queue(s->nic), 122 (void *) &s->regs[base], 123 s->regs[base + R_TX_LEN0]); 124 D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0])); 125 if (s->regs[base + R_TX_CTRL0] & CTRL_I) 126 eth_pulse_irq(s); 127 } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { 128 memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6); 129 if (s->regs[base + R_TX_CTRL0] & CTRL_I) 130 eth_pulse_irq(s); 131 } 132 133 /* We are fast and get ready pretty much immediately so 134 we actually never flip the S nor P bits to one. */ 135 s->regs[addr] = value & ~(CTRL_P | CTRL_S); 136 break; 137 138 /* Keep these native. */ 139 case R_RX_CTRL0: 140 case R_RX_CTRL1: 141 if (!(value & CTRL_S)) { 142 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 143 } 144 case R_TX_LEN0: 145 case R_TX_LEN1: 146 case R_TX_GIE0: 147 D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n", 148 __func__, addr * 4, value)); 149 s->regs[addr] = value; 150 break; 151 152 default: 153 s->regs[addr] = tswap32(value); 154 break; 155 } 156 } 157 158 static const MemoryRegionOps eth_ops = { 159 .read = eth_read, 160 .write = eth_write, 161 .endianness = DEVICE_NATIVE_ENDIAN, 162 .valid = { 163 .min_access_size = 4, 164 .max_access_size = 4 165 } 166 }; 167 168 static int eth_can_rx(NetClientState *nc) 169 { 170 struct xlx_ethlite *s = qemu_get_nic_opaque(nc); 171 unsigned int rxbase = s->rxbuf * (0x800 / 4); 172 173 return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S); 174 } 175 176 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 177 { 178 struct xlx_ethlite *s = qemu_get_nic_opaque(nc); 179 unsigned int rxbase = s->rxbuf * (0x800 / 4); 180 181 /* DA filter. */ 182 if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6)) 183 return size; 184 185 if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) { 186 D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0])); 187 return -1; 188 } 189 190 D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase)); 191 memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size); 192 193 s->regs[rxbase + R_RX_CTRL0] |= CTRL_S; 194 if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I) 195 eth_pulse_irq(s); 196 197 /* If c_rx_pingpong was set flip buffers. */ 198 s->rxbuf ^= s->c_rx_pingpong; 199 return size; 200 } 201 202 static void eth_cleanup(NetClientState *nc) 203 { 204 struct xlx_ethlite *s = qemu_get_nic_opaque(nc); 205 206 s->nic = NULL; 207 } 208 209 static NetClientInfo net_xilinx_ethlite_info = { 210 .type = NET_CLIENT_OPTIONS_KIND_NIC, 211 .size = sizeof(NICState), 212 .can_receive = eth_can_rx, 213 .receive = eth_rx, 214 .cleanup = eth_cleanup, 215 }; 216 217 static int xilinx_ethlite_init(SysBusDevice *dev) 218 { 219 struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev); 220 221 sysbus_init_irq(dev, &s->irq); 222 s->rxbuf = 0; 223 224 memory_region_init_io(&s->mmio, OBJECT(s), ð_ops, s, 225 "xlnx.xps-ethernetlite", R_MAX * 4); 226 sysbus_init_mmio(dev, &s->mmio); 227 228 qemu_macaddr_default_if_unset(&s->conf.macaddr); 229 s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, 230 object_get_typename(OBJECT(dev)), dev->qdev.id, s); 231 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 232 return 0; 233 } 234 235 static Property xilinx_ethlite_properties[] = { 236 DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1), 237 DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1), 238 DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf), 239 DEFINE_PROP_END_OF_LIST(), 240 }; 241 242 static void xilinx_ethlite_class_init(ObjectClass *klass, void *data) 243 { 244 DeviceClass *dc = DEVICE_CLASS(klass); 245 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 246 247 k->init = xilinx_ethlite_init; 248 dc->props = xilinx_ethlite_properties; 249 } 250 251 static const TypeInfo xilinx_ethlite_info = { 252 .name = "xlnx.xps-ethernetlite", 253 .parent = TYPE_SYS_BUS_DEVICE, 254 .instance_size = sizeof(struct xlx_ethlite), 255 .class_init = xilinx_ethlite_class_init, 256 }; 257 258 static void xilinx_ethlite_register_types(void) 259 { 260 type_register_static(&xilinx_ethlite_info); 261 } 262 263 type_init(xilinx_ethlite_register_types) 264