1 /* 2 * QEMU model of the Xilinx Ethernet Lite MAC. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "cpu.h" /* FIXME should not use tswap* */ 28 #include "hw/sysbus.h" 29 #include "hw/hw.h" 30 #include "net/net.h" 31 32 #define D(x) 33 #define R_TX_BUF0 0 34 #define R_TX_LEN0 (0x07f4 / 4) 35 #define R_TX_GIE0 (0x07f8 / 4) 36 #define R_TX_CTRL0 (0x07fc / 4) 37 #define R_TX_BUF1 (0x0800 / 4) 38 #define R_TX_LEN1 (0x0ff4 / 4) 39 #define R_TX_CTRL1 (0x0ffc / 4) 40 41 #define R_RX_BUF0 (0x1000 / 4) 42 #define R_RX_CTRL0 (0x17fc / 4) 43 #define R_RX_BUF1 (0x1800 / 4) 44 #define R_RX_CTRL1 (0x1ffc / 4) 45 #define R_MAX (0x2000 / 4) 46 47 #define GIE_GIE 0x80000000 48 49 #define CTRL_I 0x8 50 #define CTRL_P 0x2 51 #define CTRL_S 0x1 52 53 #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite" 54 #define XILINX_ETHLITE(obj) \ 55 OBJECT_CHECK(struct xlx_ethlite, (obj), TYPE_XILINX_ETHLITE) 56 57 struct xlx_ethlite 58 { 59 SysBusDevice parent_obj; 60 61 MemoryRegion mmio; 62 qemu_irq irq; 63 NICState *nic; 64 NICConf conf; 65 66 uint32_t c_tx_pingpong; 67 uint32_t c_rx_pingpong; 68 unsigned int txbuf; 69 unsigned int rxbuf; 70 71 uint32_t regs[R_MAX]; 72 }; 73 74 static inline void eth_pulse_irq(struct xlx_ethlite *s) 75 { 76 /* Only the first gie reg is active. */ 77 if (s->regs[R_TX_GIE0] & GIE_GIE) { 78 qemu_irq_pulse(s->irq); 79 } 80 } 81 82 static uint64_t 83 eth_read(void *opaque, hwaddr addr, unsigned int size) 84 { 85 struct xlx_ethlite *s = opaque; 86 uint32_t r = 0; 87 88 addr >>= 2; 89 90 switch (addr) 91 { 92 case R_TX_GIE0: 93 case R_TX_LEN0: 94 case R_TX_LEN1: 95 case R_TX_CTRL1: 96 case R_TX_CTRL0: 97 case R_RX_CTRL1: 98 case R_RX_CTRL0: 99 r = s->regs[addr]; 100 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r)); 101 break; 102 103 default: 104 r = tswap32(s->regs[addr]); 105 break; 106 } 107 return r; 108 } 109 110 static void 111 eth_write(void *opaque, hwaddr addr, 112 uint64_t val64, unsigned int size) 113 { 114 struct xlx_ethlite *s = opaque; 115 unsigned int base = 0; 116 uint32_t value = val64; 117 118 addr >>= 2; 119 switch (addr) 120 { 121 case R_TX_CTRL0: 122 case R_TX_CTRL1: 123 if (addr == R_TX_CTRL1) 124 base = 0x800 / 4; 125 126 D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n", 127 __func__, addr * 4, value)); 128 if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { 129 qemu_send_packet(qemu_get_queue(s->nic), 130 (void *) &s->regs[base], 131 s->regs[base + R_TX_LEN0]); 132 D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0])); 133 if (s->regs[base + R_TX_CTRL0] & CTRL_I) 134 eth_pulse_irq(s); 135 } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { 136 memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6); 137 if (s->regs[base + R_TX_CTRL0] & CTRL_I) 138 eth_pulse_irq(s); 139 } 140 141 /* We are fast and get ready pretty much immediately so 142 we actually never flip the S nor P bits to one. */ 143 s->regs[addr] = value & ~(CTRL_P | CTRL_S); 144 break; 145 146 /* Keep these native. */ 147 case R_RX_CTRL0: 148 case R_RX_CTRL1: 149 if (!(value & CTRL_S)) { 150 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 151 } 152 /* fall through */ 153 case R_TX_LEN0: 154 case R_TX_LEN1: 155 case R_TX_GIE0: 156 D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n", 157 __func__, addr * 4, value)); 158 s->regs[addr] = value; 159 break; 160 161 default: 162 s->regs[addr] = tswap32(value); 163 break; 164 } 165 } 166 167 static const MemoryRegionOps eth_ops = { 168 .read = eth_read, 169 .write = eth_write, 170 .endianness = DEVICE_NATIVE_ENDIAN, 171 .valid = { 172 .min_access_size = 4, 173 .max_access_size = 4 174 } 175 }; 176 177 static int eth_can_rx(NetClientState *nc) 178 { 179 struct xlx_ethlite *s = qemu_get_nic_opaque(nc); 180 unsigned int rxbase = s->rxbuf * (0x800 / 4); 181 182 return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S); 183 } 184 185 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 186 { 187 struct xlx_ethlite *s = qemu_get_nic_opaque(nc); 188 unsigned int rxbase = s->rxbuf * (0x800 / 4); 189 190 /* DA filter. */ 191 if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6)) 192 return size; 193 194 if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) { 195 D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0])); 196 return -1; 197 } 198 199 D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase)); 200 if (size > (R_MAX - R_RX_BUF0 - rxbase) * 4) { 201 D(qemu_log("ethlite packet is too big, size=%x\n", size)); 202 return -1; 203 } 204 memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size); 205 206 s->regs[rxbase + R_RX_CTRL0] |= CTRL_S; 207 if (s->regs[R_RX_CTRL0] & CTRL_I) { 208 eth_pulse_irq(s); 209 } 210 211 /* If c_rx_pingpong was set flip buffers. */ 212 s->rxbuf ^= s->c_rx_pingpong; 213 return size; 214 } 215 216 static void xilinx_ethlite_reset(DeviceState *dev) 217 { 218 struct xlx_ethlite *s = XILINX_ETHLITE(dev); 219 220 s->rxbuf = 0; 221 } 222 223 static NetClientInfo net_xilinx_ethlite_info = { 224 .type = NET_CLIENT_DRIVER_NIC, 225 .size = sizeof(NICState), 226 .can_receive = eth_can_rx, 227 .receive = eth_rx, 228 }; 229 230 static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) 231 { 232 struct xlx_ethlite *s = XILINX_ETHLITE(dev); 233 234 qemu_macaddr_default_if_unset(&s->conf.macaddr); 235 s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, 236 object_get_typename(OBJECT(dev)), dev->id, s); 237 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 238 } 239 240 static void xilinx_ethlite_init(Object *obj) 241 { 242 struct xlx_ethlite *s = XILINX_ETHLITE(obj); 243 244 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 245 246 memory_region_init_io(&s->mmio, obj, ð_ops, s, 247 "xlnx.xps-ethernetlite", R_MAX * 4); 248 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 249 } 250 251 static Property xilinx_ethlite_properties[] = { 252 DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1), 253 DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1), 254 DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf), 255 DEFINE_PROP_END_OF_LIST(), 256 }; 257 258 static void xilinx_ethlite_class_init(ObjectClass *klass, void *data) 259 { 260 DeviceClass *dc = DEVICE_CLASS(klass); 261 262 dc->realize = xilinx_ethlite_realize; 263 dc->reset = xilinx_ethlite_reset; 264 dc->props = xilinx_ethlite_properties; 265 } 266 267 static const TypeInfo xilinx_ethlite_info = { 268 .name = TYPE_XILINX_ETHLITE, 269 .parent = TYPE_SYS_BUS_DEVICE, 270 .instance_size = sizeof(struct xlx_ethlite), 271 .instance_init = xilinx_ethlite_init, 272 .class_init = xilinx_ethlite_class_init, 273 }; 274 275 static void xilinx_ethlite_register_types(void) 276 { 277 type_register_static(&xilinx_ethlite_info); 278 } 279 280 type_init(xilinx_ethlite_register_types) 281