xref: /openbmc/qemu/hw/net/xilinx_ethlite.c (revision 21f5826a)
1 /*
2  * QEMU model of the Xilinx Ethernet Lite MAC.
3  *
4  * Copyright (c) 2009 Edgar E. Iglesias.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "hw/sysbus.h"
26 #include "hw/hw.h"
27 #include "net/net.h"
28 
29 #define D(x)
30 #define R_TX_BUF0     0
31 #define R_TX_LEN0     (0x07f4 / 4)
32 #define R_TX_GIE0     (0x07f8 / 4)
33 #define R_TX_CTRL0    (0x07fc / 4)
34 #define R_TX_BUF1     (0x0800 / 4)
35 #define R_TX_LEN1     (0x0ff4 / 4)
36 #define R_TX_CTRL1    (0x0ffc / 4)
37 
38 #define R_RX_BUF0     (0x1000 / 4)
39 #define R_RX_CTRL0    (0x17fc / 4)
40 #define R_RX_BUF1     (0x1800 / 4)
41 #define R_RX_CTRL1    (0x1ffc / 4)
42 #define R_MAX         (0x2000 / 4)
43 
44 #define GIE_GIE    0x80000000
45 
46 #define CTRL_I     0x8
47 #define CTRL_P     0x2
48 #define CTRL_S     0x1
49 
50 #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
51 #define XILINX_ETHLITE(obj) \
52     OBJECT_CHECK(struct xlx_ethlite, (obj), TYPE_XILINX_ETHLITE)
53 
54 struct xlx_ethlite
55 {
56     SysBusDevice parent_obj;
57 
58     MemoryRegion mmio;
59     qemu_irq irq;
60     NICState *nic;
61     NICConf conf;
62 
63     uint32_t c_tx_pingpong;
64     uint32_t c_rx_pingpong;
65     unsigned int txbuf;
66     unsigned int rxbuf;
67 
68     uint32_t regs[R_MAX];
69 };
70 
71 static inline void eth_pulse_irq(struct xlx_ethlite *s)
72 {
73     /* Only the first gie reg is active.  */
74     if (s->regs[R_TX_GIE0] & GIE_GIE) {
75         qemu_irq_pulse(s->irq);
76     }
77 }
78 
79 static uint64_t
80 eth_read(void *opaque, hwaddr addr, unsigned int size)
81 {
82     struct xlx_ethlite *s = opaque;
83     uint32_t r = 0;
84 
85     addr >>= 2;
86 
87     switch (addr)
88     {
89         case R_TX_GIE0:
90         case R_TX_LEN0:
91         case R_TX_LEN1:
92         case R_TX_CTRL1:
93         case R_TX_CTRL0:
94         case R_RX_CTRL1:
95         case R_RX_CTRL0:
96             r = s->regs[addr];
97             D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r));
98             break;
99 
100         default:
101             r = tswap32(s->regs[addr]);
102             break;
103     }
104     return r;
105 }
106 
107 static void
108 eth_write(void *opaque, hwaddr addr,
109           uint64_t val64, unsigned int size)
110 {
111     struct xlx_ethlite *s = opaque;
112     unsigned int base = 0;
113     uint32_t value = val64;
114 
115     addr >>= 2;
116     switch (addr)
117     {
118         case R_TX_CTRL0:
119         case R_TX_CTRL1:
120             if (addr == R_TX_CTRL1)
121                 base = 0x800 / 4;
122 
123             D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
124                        __func__, addr * 4, value));
125             if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
126                 qemu_send_packet(qemu_get_queue(s->nic),
127                                  (void *) &s->regs[base],
128                                  s->regs[base + R_TX_LEN0]);
129                 D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
130                 if (s->regs[base + R_TX_CTRL0] & CTRL_I)
131                     eth_pulse_irq(s);
132             } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
133                 memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
134                 if (s->regs[base + R_TX_CTRL0] & CTRL_I)
135                     eth_pulse_irq(s);
136             }
137 
138             /* We are fast and get ready pretty much immediately so
139                we actually never flip the S nor P bits to one.  */
140             s->regs[addr] = value & ~(CTRL_P | CTRL_S);
141             break;
142 
143         /* Keep these native.  */
144         case R_RX_CTRL0:
145         case R_RX_CTRL1:
146             if (!(value & CTRL_S)) {
147                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
148             }
149         case R_TX_LEN0:
150         case R_TX_LEN1:
151         case R_TX_GIE0:
152             D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
153                        __func__, addr * 4, value));
154             s->regs[addr] = value;
155             break;
156 
157         default:
158             s->regs[addr] = tswap32(value);
159             break;
160     }
161 }
162 
163 static const MemoryRegionOps eth_ops = {
164     .read = eth_read,
165     .write = eth_write,
166     .endianness = DEVICE_NATIVE_ENDIAN,
167     .valid = {
168         .min_access_size = 4,
169         .max_access_size = 4
170     }
171 };
172 
173 static int eth_can_rx(NetClientState *nc)
174 {
175     struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
176     unsigned int rxbase = s->rxbuf * (0x800 / 4);
177 
178     return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
179 }
180 
181 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
182 {
183     struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
184     unsigned int rxbase = s->rxbuf * (0x800 / 4);
185 
186     /* DA filter.  */
187     if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
188         return size;
189 
190     if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
191         D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
192         return -1;
193     }
194 
195     D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase));
196     memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
197 
198     s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
199     if (s->regs[R_RX_CTRL0] & CTRL_I) {
200         eth_pulse_irq(s);
201     }
202 
203     /* If c_rx_pingpong was set flip buffers.  */
204     s->rxbuf ^= s->c_rx_pingpong;
205     return size;
206 }
207 
208 static void xilinx_ethlite_reset(DeviceState *dev)
209 {
210     struct xlx_ethlite *s = XILINX_ETHLITE(dev);
211 
212     s->rxbuf = 0;
213 }
214 
215 static NetClientInfo net_xilinx_ethlite_info = {
216     .type = NET_CLIENT_OPTIONS_KIND_NIC,
217     .size = sizeof(NICState),
218     .can_receive = eth_can_rx,
219     .receive = eth_rx,
220 };
221 
222 static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
223 {
224     struct xlx_ethlite *s = XILINX_ETHLITE(dev);
225 
226     qemu_macaddr_default_if_unset(&s->conf.macaddr);
227     s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
228                           object_get_typename(OBJECT(dev)), dev->id, s);
229     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
230 }
231 
232 static void xilinx_ethlite_init(Object *obj)
233 {
234     struct xlx_ethlite *s = XILINX_ETHLITE(obj);
235 
236     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
237 
238     memory_region_init_io(&s->mmio, obj, &eth_ops, s,
239                           "xlnx.xps-ethernetlite", R_MAX * 4);
240     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
241 }
242 
243 static Property xilinx_ethlite_properties[] = {
244     DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
245     DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
246     DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
247     DEFINE_PROP_END_OF_LIST(),
248 };
249 
250 static void xilinx_ethlite_class_init(ObjectClass *klass, void *data)
251 {
252     DeviceClass *dc = DEVICE_CLASS(klass);
253 
254     dc->realize = xilinx_ethlite_realize;
255     dc->reset = xilinx_ethlite_reset;
256     dc->props = xilinx_ethlite_properties;
257 }
258 
259 static const TypeInfo xilinx_ethlite_info = {
260     .name          = TYPE_XILINX_ETHLITE,
261     .parent        = TYPE_SYS_BUS_DEVICE,
262     .instance_size = sizeof(struct xlx_ethlite),
263     .instance_init = xilinx_ethlite_init,
264     .class_init    = xilinx_ethlite_class_init,
265 };
266 
267 static void xilinx_ethlite_register_types(void)
268 {
269     type_register_static(&xilinx_ethlite_info);
270 }
271 
272 type_init(xilinx_ethlite_register_types)
273