1 /* 2 * QEMU model of Xilinx AXI-Ethernet. 3 * 4 * Copyright (c) 2011 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "qapi/error.h" 28 #include "qemu/log.h" 29 #include "qemu/module.h" 30 #include "net/net.h" 31 #include "net/checksum.h" 32 33 #include "hw/stream.h" 34 35 #define DPHY(x) 36 37 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" 38 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream" 39 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream" 40 41 #define XILINX_AXI_ENET(obj) \ 42 OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET) 43 44 #define XILINX_AXI_ENET_DATA_STREAM(obj) \ 45 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ 46 TYPE_XILINX_AXI_ENET_DATA_STREAM) 47 48 #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \ 49 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ 50 TYPE_XILINX_AXI_ENET_CONTROL_STREAM) 51 52 /* Advertisement control register. */ 53 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 54 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 55 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 56 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 57 58 #define CONTROL_PAYLOAD_WORDS 5 59 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) 60 61 struct PHY { 62 uint32_t regs[32]; 63 64 int link; 65 66 unsigned int (*read)(struct PHY *phy, unsigned int req); 67 void (*write)(struct PHY *phy, unsigned int req, 68 unsigned int data); 69 }; 70 71 static unsigned int tdk_read(struct PHY *phy, unsigned int req) 72 { 73 int regnum; 74 unsigned r = 0; 75 76 regnum = req & 0x1f; 77 78 switch (regnum) { 79 case 1: 80 if (!phy->link) { 81 break; 82 } 83 /* MR1. */ 84 /* Speeds and modes. */ 85 r |= (1 << 13) | (1 << 14); 86 r |= (1 << 11) | (1 << 12); 87 r |= (1 << 5); /* Autoneg complete. */ 88 r |= (1 << 3); /* Autoneg able. */ 89 r |= (1 << 2); /* link. */ 90 r |= (1 << 1); /* link. */ 91 break; 92 case 5: 93 /* Link partner ability. 94 We are kind; always agree with whatever best mode 95 the guest advertises. */ 96 r = 1 << 14; /* Success. */ 97 /* Copy advertised modes. */ 98 r |= phy->regs[4] & (15 << 5); 99 /* Autoneg support. */ 100 r |= 1; 101 break; 102 case 17: 103 /* Marvell PHY on many xilinx boards. */ 104 r = 0x8000; /* 1000Mb */ 105 break; 106 case 18: 107 { 108 /* Diagnostics reg. */ 109 int duplex = 0; 110 int speed_100 = 0; 111 112 if (!phy->link) { 113 break; 114 } 115 116 /* Are we advertising 100 half or 100 duplex ? */ 117 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); 118 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); 119 120 /* Are we advertising 10 duplex or 100 duplex ? */ 121 duplex = !!(phy->regs[4] & ADVERTISE_100FULL); 122 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); 123 r = (speed_100 << 10) | (duplex << 11); 124 } 125 break; 126 127 default: 128 r = phy->regs[regnum]; 129 break; 130 } 131 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum)); 132 return r; 133 } 134 135 static void 136 tdk_write(struct PHY *phy, unsigned int req, unsigned int data) 137 { 138 int regnum; 139 140 regnum = req & 0x1f; 141 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data)); 142 switch (regnum) { 143 default: 144 phy->regs[regnum] = data; 145 break; 146 } 147 148 /* Unconditionally clear regs[BMCR][BMCR_RESET] */ 149 phy->regs[0] &= ~0x8000; 150 } 151 152 static void 153 tdk_init(struct PHY *phy) 154 { 155 phy->regs[0] = 0x3100; 156 /* PHY Id. */ 157 phy->regs[2] = 0x0300; 158 phy->regs[3] = 0xe400; 159 /* Autonegotiation advertisement reg. */ 160 phy->regs[4] = 0x01E1; 161 phy->link = 1; 162 163 phy->read = tdk_read; 164 phy->write = tdk_write; 165 } 166 167 struct MDIOBus { 168 /* bus. */ 169 int mdc; 170 int mdio; 171 172 /* decoder. */ 173 enum { 174 PREAMBLE, 175 SOF, 176 OPC, 177 ADDR, 178 REQ, 179 TURNAROUND, 180 DATA 181 } state; 182 unsigned int drive; 183 184 unsigned int cnt; 185 unsigned int addr; 186 unsigned int opc; 187 unsigned int req; 188 unsigned int data; 189 190 struct PHY *devs[32]; 191 }; 192 193 static void 194 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 195 { 196 bus->devs[addr & 0x1f] = phy; 197 } 198 199 #ifdef USE_THIS_DEAD_CODE 200 static void 201 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 202 { 203 bus->devs[addr & 0x1f] = NULL; 204 } 205 #endif 206 207 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, 208 unsigned int reg) 209 { 210 struct PHY *phy; 211 uint16_t data; 212 213 phy = bus->devs[addr]; 214 if (phy && phy->read) { 215 data = phy->read(phy, reg); 216 } else { 217 data = 0xffff; 218 } 219 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 220 return data; 221 } 222 223 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, 224 unsigned int reg, uint16_t data) 225 { 226 struct PHY *phy; 227 228 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 229 phy = bus->devs[addr]; 230 if (phy && phy->write) { 231 phy->write(phy, reg, data); 232 } 233 } 234 235 #define DENET(x) 236 237 #define R_RAF (0x000 / 4) 238 enum { 239 RAF_MCAST_REJ = (1 << 1), 240 RAF_BCAST_REJ = (1 << 2), 241 RAF_EMCF_EN = (1 << 12), 242 RAF_NEWFUNC_EN = (1 << 11) 243 }; 244 245 #define R_IS (0x00C / 4) 246 enum { 247 IS_HARD_ACCESS_COMPLETE = 1, 248 IS_AUTONEG = (1 << 1), 249 IS_RX_COMPLETE = (1 << 2), 250 IS_RX_REJECT = (1 << 3), 251 IS_TX_COMPLETE = (1 << 5), 252 IS_RX_DCM_LOCK = (1 << 6), 253 IS_MGM_RDY = (1 << 7), 254 IS_PHY_RST_DONE = (1 << 8), 255 }; 256 257 #define R_IP (0x010 / 4) 258 #define R_IE (0x014 / 4) 259 #define R_UAWL (0x020 / 4) 260 #define R_UAWU (0x024 / 4) 261 #define R_PPST (0x030 / 4) 262 enum { 263 PPST_LINKSTATUS = (1 << 0), 264 PPST_PHY_LINKSTATUS = (1 << 7), 265 }; 266 267 #define R_STATS_RX_BYTESL (0x200 / 4) 268 #define R_STATS_RX_BYTESH (0x204 / 4) 269 #define R_STATS_TX_BYTESL (0x208 / 4) 270 #define R_STATS_TX_BYTESH (0x20C / 4) 271 #define R_STATS_RXL (0x290 / 4) 272 #define R_STATS_RXH (0x294 / 4) 273 #define R_STATS_RX_BCASTL (0x2a0 / 4) 274 #define R_STATS_RX_BCASTH (0x2a4 / 4) 275 #define R_STATS_RX_MCASTL (0x2a8 / 4) 276 #define R_STATS_RX_MCASTH (0x2ac / 4) 277 278 #define R_RCW0 (0x400 / 4) 279 #define R_RCW1 (0x404 / 4) 280 enum { 281 RCW1_VLAN = (1 << 27), 282 RCW1_RX = (1 << 28), 283 RCW1_FCS = (1 << 29), 284 RCW1_JUM = (1 << 30), 285 RCW1_RST = (1 << 31), 286 }; 287 288 #define R_TC (0x408 / 4) 289 enum { 290 TC_VLAN = (1 << 27), 291 TC_TX = (1 << 28), 292 TC_FCS = (1 << 29), 293 TC_JUM = (1 << 30), 294 TC_RST = (1 << 31), 295 }; 296 297 #define R_EMMC (0x410 / 4) 298 enum { 299 EMMC_LINKSPEED_10MB = (0 << 30), 300 EMMC_LINKSPEED_100MB = (1 << 30), 301 EMMC_LINKSPEED_1000MB = (2 << 30), 302 }; 303 304 #define R_PHYC (0x414 / 4) 305 306 #define R_MC (0x500 / 4) 307 #define MC_EN (1 << 6) 308 309 #define R_MCR (0x504 / 4) 310 #define R_MWD (0x508 / 4) 311 #define R_MRD (0x50c / 4) 312 #define R_MIS (0x600 / 4) 313 #define R_MIP (0x620 / 4) 314 #define R_MIE (0x640 / 4) 315 #define R_MIC (0x640 / 4) 316 317 #define R_UAW0 (0x700 / 4) 318 #define R_UAW1 (0x704 / 4) 319 #define R_FMI (0x708 / 4) 320 #define R_AF0 (0x710 / 4) 321 #define R_AF1 (0x714 / 4) 322 #define R_MAX (0x34 / 4) 323 324 /* Indirect registers. */ 325 struct TEMAC { 326 struct MDIOBus mdio_bus; 327 struct PHY phy; 328 329 void *parent; 330 }; 331 332 typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave; 333 typedef struct XilinxAXIEnet XilinxAXIEnet; 334 335 struct XilinxAXIEnetStreamSlave { 336 Object parent; 337 338 struct XilinxAXIEnet *enet; 339 } ; 340 341 struct XilinxAXIEnet { 342 SysBusDevice busdev; 343 MemoryRegion iomem; 344 qemu_irq irq; 345 StreamSlave *tx_data_dev; 346 StreamSlave *tx_control_dev; 347 XilinxAXIEnetStreamSlave rx_data_dev; 348 XilinxAXIEnetStreamSlave rx_control_dev; 349 NICState *nic; 350 NICConf conf; 351 352 353 uint32_t c_rxmem; 354 uint32_t c_txmem; 355 uint32_t c_phyaddr; 356 357 struct TEMAC TEMAC; 358 359 /* MII regs. */ 360 union { 361 uint32_t regs[4]; 362 struct { 363 uint32_t mc; 364 uint32_t mcr; 365 uint32_t mwd; 366 uint32_t mrd; 367 }; 368 } mii; 369 370 struct { 371 uint64_t rx_bytes; 372 uint64_t tx_bytes; 373 374 uint64_t rx; 375 uint64_t rx_bcast; 376 uint64_t rx_mcast; 377 } stats; 378 379 /* Receive configuration words. */ 380 uint32_t rcw[2]; 381 /* Transmit config. */ 382 uint32_t tc; 383 uint32_t emmc; 384 uint32_t phyc; 385 386 /* Unicast Address Word. */ 387 uint32_t uaw[2]; 388 /* Unicast address filter used with extended mcast. */ 389 uint32_t ext_uaw[2]; 390 uint32_t fmi; 391 392 uint32_t regs[R_MAX]; 393 394 /* Multicast filter addrs. */ 395 uint32_t maddr[4][2]; 396 /* 32K x 1 lookup filter. */ 397 uint32_t ext_mtable[1024]; 398 399 uint32_t hdr[CONTROL_PAYLOAD_WORDS]; 400 401 uint8_t *rxmem; 402 uint32_t rxsize; 403 uint32_t rxpos; 404 405 uint8_t rxapp[CONTROL_PAYLOAD_SIZE]; 406 uint32_t rxappsize; 407 408 /* Whether axienet_eth_rx_notify should flush incoming queue. */ 409 bool need_flush; 410 }; 411 412 static void axienet_rx_reset(XilinxAXIEnet *s) 413 { 414 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; 415 } 416 417 static void axienet_tx_reset(XilinxAXIEnet *s) 418 { 419 s->tc = TC_JUM | TC_TX | TC_VLAN; 420 } 421 422 static inline int axienet_rx_resetting(XilinxAXIEnet *s) 423 { 424 return s->rcw[1] & RCW1_RST; 425 } 426 427 static inline int axienet_rx_enabled(XilinxAXIEnet *s) 428 { 429 return s->rcw[1] & RCW1_RX; 430 } 431 432 static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) 433 { 434 return !!(s->regs[R_RAF] & RAF_EMCF_EN); 435 } 436 437 static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) 438 { 439 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); 440 } 441 442 static void xilinx_axienet_reset(DeviceState *d) 443 { 444 XilinxAXIEnet *s = XILINX_AXI_ENET(d); 445 446 axienet_rx_reset(s); 447 axienet_tx_reset(s); 448 449 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; 450 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; 451 452 s->emmc = EMMC_LINKSPEED_100MB; 453 } 454 455 static void enet_update_irq(XilinxAXIEnet *s) 456 { 457 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; 458 qemu_set_irq(s->irq, !!s->regs[R_IP]); 459 } 460 461 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) 462 { 463 XilinxAXIEnet *s = opaque; 464 uint32_t r = 0; 465 addr >>= 2; 466 467 switch (addr) { 468 case R_RCW0: 469 case R_RCW1: 470 r = s->rcw[addr & 1]; 471 break; 472 473 case R_TC: 474 r = s->tc; 475 break; 476 477 case R_EMMC: 478 r = s->emmc; 479 break; 480 481 case R_PHYC: 482 r = s->phyc; 483 break; 484 485 case R_MCR: 486 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ 487 break; 488 489 case R_STATS_RX_BYTESL: 490 case R_STATS_RX_BYTESH: 491 r = s->stats.rx_bytes >> (32 * (addr & 1)); 492 break; 493 494 case R_STATS_TX_BYTESL: 495 case R_STATS_TX_BYTESH: 496 r = s->stats.tx_bytes >> (32 * (addr & 1)); 497 break; 498 499 case R_STATS_RXL: 500 case R_STATS_RXH: 501 r = s->stats.rx >> (32 * (addr & 1)); 502 break; 503 case R_STATS_RX_BCASTL: 504 case R_STATS_RX_BCASTH: 505 r = s->stats.rx_bcast >> (32 * (addr & 1)); 506 break; 507 case R_STATS_RX_MCASTL: 508 case R_STATS_RX_MCASTH: 509 r = s->stats.rx_mcast >> (32 * (addr & 1)); 510 break; 511 512 case R_MC: 513 case R_MWD: 514 case R_MRD: 515 r = s->mii.regs[addr & 3]; 516 break; 517 518 case R_UAW0: 519 case R_UAW1: 520 r = s->uaw[addr & 1]; 521 break; 522 523 case R_UAWU: 524 case R_UAWL: 525 r = s->ext_uaw[addr & 1]; 526 break; 527 528 case R_FMI: 529 r = s->fmi; 530 break; 531 532 case R_AF0: 533 case R_AF1: 534 r = s->maddr[s->fmi & 3][addr & 1]; 535 break; 536 537 case 0x8000 ... 0x83ff: 538 r = s->ext_mtable[addr - 0x8000]; 539 break; 540 541 default: 542 if (addr < ARRAY_SIZE(s->regs)) { 543 r = s->regs[addr]; 544 } 545 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 546 __func__, addr * 4, r)); 547 break; 548 } 549 return r; 550 } 551 552 static void enet_write(void *opaque, hwaddr addr, 553 uint64_t value, unsigned size) 554 { 555 XilinxAXIEnet *s = opaque; 556 struct TEMAC *t = &s->TEMAC; 557 558 addr >>= 2; 559 switch (addr) { 560 case R_RCW0: 561 case R_RCW1: 562 s->rcw[addr & 1] = value; 563 if ((addr & 1) && value & RCW1_RST) { 564 axienet_rx_reset(s); 565 } else { 566 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 567 } 568 break; 569 570 case R_TC: 571 s->tc = value; 572 if (value & TC_RST) { 573 axienet_tx_reset(s); 574 } 575 break; 576 577 case R_EMMC: 578 s->emmc = value; 579 break; 580 581 case R_PHYC: 582 s->phyc = value; 583 break; 584 585 case R_MC: 586 value &= ((1 << 7) - 1); 587 588 /* Enable the MII. */ 589 if (value & MC_EN) { 590 unsigned int miiclkdiv = value & ((1 << 6) - 1); 591 if (!miiclkdiv) { 592 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n"); 593 } 594 } 595 s->mii.mc = value; 596 break; 597 598 case R_MCR: { 599 unsigned int phyaddr = (value >> 24) & 0x1f; 600 unsigned int regaddr = (value >> 16) & 0x1f; 601 unsigned int op = (value >> 14) & 3; 602 unsigned int initiate = (value >> 11) & 1; 603 604 if (initiate) { 605 if (op == 1) { 606 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); 607 } else if (op == 2) { 608 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); 609 } else { 610 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op); 611 } 612 } 613 s->mii.mcr = value; 614 break; 615 } 616 617 case R_MWD: 618 case R_MRD: 619 s->mii.regs[addr & 3] = value; 620 break; 621 622 623 case R_UAW0: 624 case R_UAW1: 625 s->uaw[addr & 1] = value; 626 break; 627 628 case R_UAWL: 629 case R_UAWU: 630 s->ext_uaw[addr & 1] = value; 631 break; 632 633 case R_FMI: 634 s->fmi = value; 635 break; 636 637 case R_AF0: 638 case R_AF1: 639 s->maddr[s->fmi & 3][addr & 1] = value; 640 break; 641 642 case R_IS: 643 s->regs[addr] &= ~value; 644 break; 645 646 case 0x8000 ... 0x83ff: 647 s->ext_mtable[addr - 0x8000] = value; 648 break; 649 650 default: 651 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 652 __func__, addr * 4, (unsigned)value)); 653 if (addr < ARRAY_SIZE(s->regs)) { 654 s->regs[addr] = value; 655 } 656 break; 657 } 658 enet_update_irq(s); 659 } 660 661 static const MemoryRegionOps enet_ops = { 662 .read = enet_read, 663 .write = enet_write, 664 .endianness = DEVICE_LITTLE_ENDIAN, 665 }; 666 667 static int eth_can_rx(XilinxAXIEnet *s) 668 { 669 /* RX enabled? */ 670 return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s); 671 } 672 673 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) 674 { 675 int match = 1; 676 677 if (memcmp(buf, &f0, 4)) { 678 match = 0; 679 } 680 681 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { 682 match = 0; 683 } 684 685 return match; 686 } 687 688 static void axienet_eth_rx_notify(void *opaque) 689 { 690 XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); 691 692 while (s->rxappsize && stream_can_push(s->tx_control_dev, 693 axienet_eth_rx_notify, s)) { 694 size_t ret = stream_push(s->tx_control_dev, 695 (void *)s->rxapp + CONTROL_PAYLOAD_SIZE 696 - s->rxappsize, s->rxappsize); 697 s->rxappsize -= ret; 698 } 699 700 while (s->rxsize && stream_can_push(s->tx_data_dev, 701 axienet_eth_rx_notify, s)) { 702 size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, 703 s->rxsize); 704 s->rxsize -= ret; 705 s->rxpos += ret; 706 if (!s->rxsize) { 707 s->regs[R_IS] |= IS_RX_COMPLETE; 708 if (s->need_flush) { 709 s->need_flush = false; 710 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 711 } 712 } 713 } 714 enet_update_irq(s); 715 } 716 717 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 718 { 719 XilinxAXIEnet *s = qemu_get_nic_opaque(nc); 720 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 721 0xff, 0xff, 0xff}; 722 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; 723 uint32_t app[CONTROL_PAYLOAD_WORDS] = {0}; 724 int promisc = s->fmi & (1 << 31); 725 int unicast, broadcast, multicast, ip_multicast = 0; 726 uint32_t csum32; 727 uint16_t csum16; 728 int i; 729 730 DENET(qemu_log("%s: %zd bytes\n", __func__, size)); 731 732 if (!eth_can_rx(s)) { 733 s->need_flush = true; 734 return 0; 735 } 736 737 unicast = ~buf[0] & 0x1; 738 broadcast = memcmp(buf, sa_bcast, 6) == 0; 739 multicast = !unicast && !broadcast; 740 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { 741 ip_multicast = 1; 742 } 743 744 /* Jumbo or vlan sizes ? */ 745 if (!(s->rcw[1] & RCW1_JUM)) { 746 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { 747 return size; 748 } 749 } 750 751 /* Basic Address filters. If you want to use the extended filters 752 you'll generally have to place the ethernet mac into promiscuous mode 753 to avoid the basic filtering from dropping most frames. */ 754 if (!promisc) { 755 if (unicast) { 756 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { 757 return size; 758 } 759 } else { 760 if (broadcast) { 761 /* Broadcast. */ 762 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 763 return size; 764 } 765 } else { 766 int drop = 1; 767 768 /* Multicast. */ 769 if (s->regs[R_RAF] & RAF_MCAST_REJ) { 770 return size; 771 } 772 773 for (i = 0; i < 4; i++) { 774 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { 775 drop = 0; 776 break; 777 } 778 } 779 780 if (drop) { 781 return size; 782 } 783 } 784 } 785 } 786 787 /* Extended mcast filtering enabled? */ 788 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) { 789 if (unicast) { 790 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { 791 return size; 792 } 793 } else { 794 if (broadcast) { 795 /* Broadcast. ??? */ 796 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 797 return size; 798 } 799 } else { 800 int idx, bit; 801 802 /* Multicast. */ 803 if (!memcmp(buf, sa_ipmcast, 3)) { 804 return size; 805 } 806 807 idx = (buf[4] & 0x7f) << 8; 808 idx |= buf[5]; 809 810 bit = 1 << (idx & 0x1f); 811 idx >>= 5; 812 813 if (!(s->ext_mtable[idx] & bit)) { 814 return size; 815 } 816 } 817 } 818 } 819 820 if (size < 12) { 821 s->regs[R_IS] |= IS_RX_REJECT; 822 enet_update_irq(s); 823 return -1; 824 } 825 826 if (size > (s->c_rxmem - 4)) { 827 size = s->c_rxmem - 4; 828 } 829 830 memcpy(s->rxmem, buf, size); 831 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ 832 833 if (s->rcw[1] & RCW1_FCS) { 834 size += 4; /* fcs is inband. */ 835 } 836 837 app[0] = 5 << 28; 838 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); 839 /* Fold it once. */ 840 csum32 = (csum32 & 0xffff) + (csum32 >> 16); 841 /* And twice to get rid of possible carries. */ 842 csum16 = (csum32 & 0xffff) + (csum32 >> 16); 843 app[3] = csum16; 844 app[4] = size & 0xffff; 845 846 s->stats.rx_bytes += size; 847 s->stats.rx++; 848 if (multicast) { 849 s->stats.rx_mcast++; 850 app[2] |= 1 | (ip_multicast << 1); 851 } else if (broadcast) { 852 s->stats.rx_bcast++; 853 app[2] |= 1 << 3; 854 } 855 856 /* Good frame. */ 857 app[2] |= 1 << 6; 858 859 s->rxsize = size; 860 s->rxpos = 0; 861 for (i = 0; i < ARRAY_SIZE(app); ++i) { 862 app[i] = cpu_to_le32(app[i]); 863 } 864 s->rxappsize = CONTROL_PAYLOAD_SIZE; 865 memcpy(s->rxapp, app, s->rxappsize); 866 axienet_eth_rx_notify(s); 867 868 enet_update_irq(s); 869 return size; 870 } 871 872 static size_t 873 xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len) 874 { 875 int i; 876 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); 877 XilinxAXIEnet *s = cs->enet; 878 879 if (len != CONTROL_PAYLOAD_SIZE) { 880 hw_error("AXI Enet requires %d byte control stream payload\n", 881 (int)CONTROL_PAYLOAD_SIZE); 882 } 883 884 memcpy(s->hdr, buf, len); 885 886 for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { 887 s->hdr[i] = le32_to_cpu(s->hdr[i]); 888 } 889 return len; 890 } 891 892 static size_t 893 xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size) 894 { 895 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); 896 XilinxAXIEnet *s = ds->enet; 897 898 /* TX enable ? */ 899 if (!(s->tc & TC_TX)) { 900 return size; 901 } 902 903 /* Jumbo or vlan sizes ? */ 904 if (!(s->tc & TC_JUM)) { 905 if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) { 906 return size; 907 } 908 } 909 910 if (s->hdr[0] & 1) { 911 unsigned int start_off = s->hdr[1] >> 16; 912 unsigned int write_off = s->hdr[1] & 0xffff; 913 uint32_t tmp_csum; 914 uint16_t csum; 915 916 tmp_csum = net_checksum_add(size - start_off, 917 (uint8_t *)buf + start_off); 918 /* Accumulate the seed. */ 919 tmp_csum += s->hdr[2] & 0xffff; 920 921 /* Fold the 32bit partial checksum. */ 922 csum = net_checksum_finish(tmp_csum); 923 924 /* Writeback. */ 925 buf[write_off] = csum >> 8; 926 buf[write_off + 1] = csum & 0xff; 927 } 928 929 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 930 931 s->stats.tx_bytes += size; 932 s->regs[R_IS] |= IS_TX_COMPLETE; 933 enet_update_irq(s); 934 935 return size; 936 } 937 938 static NetClientInfo net_xilinx_enet_info = { 939 .type = NET_CLIENT_DRIVER_NIC, 940 .size = sizeof(NICState), 941 .receive = eth_rx, 942 }; 943 944 static void xilinx_enet_realize(DeviceState *dev, Error **errp) 945 { 946 XilinxAXIEnet *s = XILINX_AXI_ENET(dev); 947 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); 948 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM( 949 &s->rx_control_dev); 950 Error *local_err = NULL; 951 952 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", 953 (Object **) &ds->enet, 954 object_property_allow_set_link, 955 OBJ_PROP_LINK_STRONG, 956 &local_err); 957 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", 958 (Object **) &cs->enet, 959 object_property_allow_set_link, 960 OBJ_PROP_LINK_STRONG, 961 &local_err); 962 if (local_err) { 963 goto xilinx_enet_realize_fail; 964 } 965 object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_err); 966 object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_err); 967 if (local_err) { 968 goto xilinx_enet_realize_fail; 969 } 970 971 qemu_macaddr_default_if_unset(&s->conf.macaddr); 972 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, 973 object_get_typename(OBJECT(dev)), dev->id, s); 974 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 975 976 tdk_init(&s->TEMAC.phy); 977 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); 978 979 s->TEMAC.parent = s; 980 981 s->rxmem = g_malloc(s->c_rxmem); 982 return; 983 984 xilinx_enet_realize_fail: 985 error_propagate(errp, local_err); 986 } 987 988 static void xilinx_enet_init(Object *obj) 989 { 990 XilinxAXIEnet *s = XILINX_AXI_ENET(obj); 991 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 992 993 object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), 994 TYPE_XILINX_AXI_ENET_DATA_STREAM); 995 object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), 996 TYPE_XILINX_AXI_ENET_CONTROL_STREAM); 997 object_property_add_child(OBJECT(s), "axistream-connected-target", 998 (Object *)&s->rx_data_dev, &error_abort); 999 object_property_add_child(OBJECT(s), "axistream-control-connected-target", 1000 (Object *)&s->rx_control_dev, &error_abort); 1001 1002 sysbus_init_irq(sbd, &s->irq); 1003 1004 memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); 1005 sysbus_init_mmio(sbd, &s->iomem); 1006 } 1007 1008 static Property xilinx_enet_properties[] = { 1009 DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), 1010 DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), 1011 DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), 1012 DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), 1013 DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, 1014 tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), 1015 DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, 1016 tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), 1017 DEFINE_PROP_END_OF_LIST(), 1018 }; 1019 1020 static void xilinx_enet_class_init(ObjectClass *klass, void *data) 1021 { 1022 DeviceClass *dc = DEVICE_CLASS(klass); 1023 1024 dc->realize = xilinx_enet_realize; 1025 dc->props = xilinx_enet_properties; 1026 dc->reset = xilinx_axienet_reset; 1027 } 1028 1029 static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data) 1030 { 1031 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); 1032 1033 ssc->push = data; 1034 } 1035 1036 static const TypeInfo xilinx_enet_info = { 1037 .name = TYPE_XILINX_AXI_ENET, 1038 .parent = TYPE_SYS_BUS_DEVICE, 1039 .instance_size = sizeof(XilinxAXIEnet), 1040 .class_init = xilinx_enet_class_init, 1041 .instance_init = xilinx_enet_init, 1042 }; 1043 1044 static const TypeInfo xilinx_enet_data_stream_info = { 1045 .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, 1046 .parent = TYPE_OBJECT, 1047 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), 1048 .class_init = xilinx_enet_stream_class_init, 1049 .class_data = xilinx_axienet_data_stream_push, 1050 .interfaces = (InterfaceInfo[]) { 1051 { TYPE_STREAM_SLAVE }, 1052 { } 1053 } 1054 }; 1055 1056 static const TypeInfo xilinx_enet_control_stream_info = { 1057 .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, 1058 .parent = TYPE_OBJECT, 1059 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), 1060 .class_init = xilinx_enet_stream_class_init, 1061 .class_data = xilinx_axienet_control_stream_push, 1062 .interfaces = (InterfaceInfo[]) { 1063 { TYPE_STREAM_SLAVE }, 1064 { } 1065 } 1066 }; 1067 1068 static void xilinx_enet_register_types(void) 1069 { 1070 type_register_static(&xilinx_enet_info); 1071 type_register_static(&xilinx_enet_data_stream_info); 1072 type_register_static(&xilinx_enet_control_stream_info); 1073 } 1074 1075 type_init(xilinx_enet_register_types) 1076