1 /* 2 * QEMU model of Xilinx AXI-Ethernet. 3 * 4 * Copyright (c) 2011 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/sysbus.h" 28 #include "qapi/error.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 #include "net/net.h" 32 #include "net/checksum.h" 33 34 #include "hw/hw.h" 35 #include "hw/irq.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/stream.h" 38 39 #define DPHY(x) 40 41 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" 42 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream" 43 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream" 44 45 #define XILINX_AXI_ENET(obj) \ 46 OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET) 47 48 #define XILINX_AXI_ENET_DATA_STREAM(obj) \ 49 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ 50 TYPE_XILINX_AXI_ENET_DATA_STREAM) 51 52 #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \ 53 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ 54 TYPE_XILINX_AXI_ENET_CONTROL_STREAM) 55 56 /* Advertisement control register. */ 57 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 58 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 59 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 60 61 #define CONTROL_PAYLOAD_WORDS 5 62 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) 63 64 struct PHY { 65 uint32_t regs[32]; 66 67 int link; 68 69 unsigned int (*read)(struct PHY *phy, unsigned int req); 70 void (*write)(struct PHY *phy, unsigned int req, 71 unsigned int data); 72 }; 73 74 static unsigned int tdk_read(struct PHY *phy, unsigned int req) 75 { 76 int regnum; 77 unsigned r = 0; 78 79 regnum = req & 0x1f; 80 81 switch (regnum) { 82 case 1: 83 if (!phy->link) { 84 break; 85 } 86 /* MR1. */ 87 /* Speeds and modes. */ 88 r |= (1 << 13) | (1 << 14); 89 r |= (1 << 11) | (1 << 12); 90 r |= (1 << 5); /* Autoneg complete. */ 91 r |= (1 << 3); /* Autoneg able. */ 92 r |= (1 << 2); /* link. */ 93 r |= (1 << 1); /* link. */ 94 break; 95 case 5: 96 /* Link partner ability. 97 We are kind; always agree with whatever best mode 98 the guest advertises. */ 99 r = 1 << 14; /* Success. */ 100 /* Copy advertised modes. */ 101 r |= phy->regs[4] & (15 << 5); 102 /* Autoneg support. */ 103 r |= 1; 104 break; 105 case 17: 106 /* Marvell PHY on many xilinx boards. */ 107 r = 0x8000; /* 1000Mb */ 108 break; 109 case 18: 110 { 111 /* Diagnostics reg. */ 112 int duplex = 0; 113 int speed_100 = 0; 114 115 if (!phy->link) { 116 break; 117 } 118 119 /* Are we advertising 100 half or 100 duplex ? */ 120 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); 121 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); 122 123 /* Are we advertising 10 duplex or 100 duplex ? */ 124 duplex = !!(phy->regs[4] & ADVERTISE_100FULL); 125 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); 126 r = (speed_100 << 10) | (duplex << 11); 127 } 128 break; 129 130 default: 131 r = phy->regs[regnum]; 132 break; 133 } 134 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum)); 135 return r; 136 } 137 138 static void 139 tdk_write(struct PHY *phy, unsigned int req, unsigned int data) 140 { 141 int regnum; 142 143 regnum = req & 0x1f; 144 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data)); 145 switch (regnum) { 146 default: 147 phy->regs[regnum] = data; 148 break; 149 } 150 151 /* Unconditionally clear regs[BMCR][BMCR_RESET] and auto-neg */ 152 phy->regs[0] &= ~0x8200; 153 } 154 155 static void 156 tdk_init(struct PHY *phy) 157 { 158 phy->regs[0] = 0x3100; 159 /* PHY Id. */ 160 phy->regs[2] = 0x0300; 161 phy->regs[3] = 0xe400; 162 /* Autonegotiation advertisement reg. */ 163 phy->regs[4] = 0x01E1; 164 phy->link = 1; 165 166 phy->read = tdk_read; 167 phy->write = tdk_write; 168 } 169 170 struct MDIOBus { 171 struct PHY *devs[32]; 172 }; 173 174 static void 175 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 176 { 177 bus->devs[addr & 0x1f] = phy; 178 } 179 180 #ifdef USE_THIS_DEAD_CODE 181 static void 182 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 183 { 184 bus->devs[addr & 0x1f] = NULL; 185 } 186 #endif 187 188 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, 189 unsigned int reg) 190 { 191 struct PHY *phy; 192 uint16_t data; 193 194 phy = bus->devs[addr]; 195 if (phy && phy->read) { 196 data = phy->read(phy, reg); 197 } else { 198 data = 0xffff; 199 } 200 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 201 return data; 202 } 203 204 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, 205 unsigned int reg, uint16_t data) 206 { 207 struct PHY *phy; 208 209 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 210 phy = bus->devs[addr]; 211 if (phy && phy->write) { 212 phy->write(phy, reg, data); 213 } 214 } 215 216 #define DENET(x) 217 218 #define R_RAF (0x000 / 4) 219 enum { 220 RAF_MCAST_REJ = (1 << 1), 221 RAF_BCAST_REJ = (1 << 2), 222 RAF_EMCF_EN = (1 << 12), 223 RAF_NEWFUNC_EN = (1 << 11) 224 }; 225 226 #define R_IS (0x00C / 4) 227 enum { 228 IS_HARD_ACCESS_COMPLETE = 1, 229 IS_AUTONEG = (1 << 1), 230 IS_RX_COMPLETE = (1 << 2), 231 IS_RX_REJECT = (1 << 3), 232 IS_TX_COMPLETE = (1 << 5), 233 IS_RX_DCM_LOCK = (1 << 6), 234 IS_MGM_RDY = (1 << 7), 235 IS_PHY_RST_DONE = (1 << 8), 236 }; 237 238 #define R_IP (0x010 / 4) 239 #define R_IE (0x014 / 4) 240 #define R_UAWL (0x020 / 4) 241 #define R_UAWU (0x024 / 4) 242 #define R_PPST (0x030 / 4) 243 enum { 244 PPST_LINKSTATUS = (1 << 0), 245 PPST_PHY_LINKSTATUS = (1 << 7), 246 }; 247 248 #define R_STATS_RX_BYTESL (0x200 / 4) 249 #define R_STATS_RX_BYTESH (0x204 / 4) 250 #define R_STATS_TX_BYTESL (0x208 / 4) 251 #define R_STATS_TX_BYTESH (0x20C / 4) 252 #define R_STATS_RXL (0x290 / 4) 253 #define R_STATS_RXH (0x294 / 4) 254 #define R_STATS_RX_BCASTL (0x2a0 / 4) 255 #define R_STATS_RX_BCASTH (0x2a4 / 4) 256 #define R_STATS_RX_MCASTL (0x2a8 / 4) 257 #define R_STATS_RX_MCASTH (0x2ac / 4) 258 259 #define R_RCW0 (0x400 / 4) 260 #define R_RCW1 (0x404 / 4) 261 enum { 262 RCW1_VLAN = (1 << 27), 263 RCW1_RX = (1 << 28), 264 RCW1_FCS = (1 << 29), 265 RCW1_JUM = (1 << 30), 266 RCW1_RST = (1 << 31), 267 }; 268 269 #define R_TC (0x408 / 4) 270 enum { 271 TC_VLAN = (1 << 27), 272 TC_TX = (1 << 28), 273 TC_FCS = (1 << 29), 274 TC_JUM = (1 << 30), 275 TC_RST = (1 << 31), 276 }; 277 278 #define R_EMMC (0x410 / 4) 279 enum { 280 EMMC_LINKSPEED_10MB = (0 << 30), 281 EMMC_LINKSPEED_100MB = (1 << 30), 282 EMMC_LINKSPEED_1000MB = (2 << 30), 283 }; 284 285 #define R_PHYC (0x414 / 4) 286 287 #define R_MC (0x500 / 4) 288 #define MC_EN (1 << 6) 289 290 #define R_MCR (0x504 / 4) 291 #define R_MWD (0x508 / 4) 292 #define R_MRD (0x50c / 4) 293 #define R_MIS (0x600 / 4) 294 #define R_MIP (0x620 / 4) 295 #define R_MIE (0x640 / 4) 296 #define R_MIC (0x640 / 4) 297 298 #define R_UAW0 (0x700 / 4) 299 #define R_UAW1 (0x704 / 4) 300 #define R_FMI (0x708 / 4) 301 #define R_AF0 (0x710 / 4) 302 #define R_AF1 (0x714 / 4) 303 #define R_MAX (0x34 / 4) 304 305 /* Indirect registers. */ 306 struct TEMAC { 307 struct MDIOBus mdio_bus; 308 struct PHY phy; 309 310 void *parent; 311 }; 312 313 typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave; 314 typedef struct XilinxAXIEnet XilinxAXIEnet; 315 316 struct XilinxAXIEnetStreamSlave { 317 Object parent; 318 319 struct XilinxAXIEnet *enet; 320 } ; 321 322 struct XilinxAXIEnet { 323 SysBusDevice busdev; 324 MemoryRegion iomem; 325 qemu_irq irq; 326 StreamSlave *tx_data_dev; 327 StreamSlave *tx_control_dev; 328 XilinxAXIEnetStreamSlave rx_data_dev; 329 XilinxAXIEnetStreamSlave rx_control_dev; 330 NICState *nic; 331 NICConf conf; 332 333 334 uint32_t c_rxmem; 335 uint32_t c_txmem; 336 uint32_t c_phyaddr; 337 338 struct TEMAC TEMAC; 339 340 /* MII regs. */ 341 union { 342 uint32_t regs[4]; 343 struct { 344 uint32_t mc; 345 uint32_t mcr; 346 uint32_t mwd; 347 uint32_t mrd; 348 }; 349 } mii; 350 351 struct { 352 uint64_t rx_bytes; 353 uint64_t tx_bytes; 354 355 uint64_t rx; 356 uint64_t rx_bcast; 357 uint64_t rx_mcast; 358 } stats; 359 360 /* Receive configuration words. */ 361 uint32_t rcw[2]; 362 /* Transmit config. */ 363 uint32_t tc; 364 uint32_t emmc; 365 uint32_t phyc; 366 367 /* Unicast Address Word. */ 368 uint32_t uaw[2]; 369 /* Unicast address filter used with extended mcast. */ 370 uint32_t ext_uaw[2]; 371 uint32_t fmi; 372 373 uint32_t regs[R_MAX]; 374 375 /* Multicast filter addrs. */ 376 uint32_t maddr[4][2]; 377 /* 32K x 1 lookup filter. */ 378 uint32_t ext_mtable[1024]; 379 380 uint32_t hdr[CONTROL_PAYLOAD_WORDS]; 381 382 uint8_t *txmem; 383 uint32_t txpos; 384 385 uint8_t *rxmem; 386 uint32_t rxsize; 387 uint32_t rxpos; 388 389 uint8_t rxapp[CONTROL_PAYLOAD_SIZE]; 390 uint32_t rxappsize; 391 392 /* Whether axienet_eth_rx_notify should flush incoming queue. */ 393 bool need_flush; 394 }; 395 396 static void axienet_rx_reset(XilinxAXIEnet *s) 397 { 398 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; 399 } 400 401 static void axienet_tx_reset(XilinxAXIEnet *s) 402 { 403 s->tc = TC_JUM | TC_TX | TC_VLAN; 404 s->txpos = 0; 405 } 406 407 static inline int axienet_rx_resetting(XilinxAXIEnet *s) 408 { 409 return s->rcw[1] & RCW1_RST; 410 } 411 412 static inline int axienet_rx_enabled(XilinxAXIEnet *s) 413 { 414 return s->rcw[1] & RCW1_RX; 415 } 416 417 static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) 418 { 419 return !!(s->regs[R_RAF] & RAF_EMCF_EN); 420 } 421 422 static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) 423 { 424 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); 425 } 426 427 static void xilinx_axienet_reset(DeviceState *d) 428 { 429 XilinxAXIEnet *s = XILINX_AXI_ENET(d); 430 431 axienet_rx_reset(s); 432 axienet_tx_reset(s); 433 434 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; 435 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; 436 437 s->emmc = EMMC_LINKSPEED_100MB; 438 } 439 440 static void enet_update_irq(XilinxAXIEnet *s) 441 { 442 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; 443 qemu_set_irq(s->irq, !!s->regs[R_IP]); 444 } 445 446 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) 447 { 448 XilinxAXIEnet *s = opaque; 449 uint32_t r = 0; 450 addr >>= 2; 451 452 switch (addr) { 453 case R_RCW0: 454 case R_RCW1: 455 r = s->rcw[addr & 1]; 456 break; 457 458 case R_TC: 459 r = s->tc; 460 break; 461 462 case R_EMMC: 463 r = s->emmc; 464 break; 465 466 case R_PHYC: 467 r = s->phyc; 468 break; 469 470 case R_MCR: 471 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ 472 break; 473 474 case R_STATS_RX_BYTESL: 475 case R_STATS_RX_BYTESH: 476 r = s->stats.rx_bytes >> (32 * (addr & 1)); 477 break; 478 479 case R_STATS_TX_BYTESL: 480 case R_STATS_TX_BYTESH: 481 r = s->stats.tx_bytes >> (32 * (addr & 1)); 482 break; 483 484 case R_STATS_RXL: 485 case R_STATS_RXH: 486 r = s->stats.rx >> (32 * (addr & 1)); 487 break; 488 case R_STATS_RX_BCASTL: 489 case R_STATS_RX_BCASTH: 490 r = s->stats.rx_bcast >> (32 * (addr & 1)); 491 break; 492 case R_STATS_RX_MCASTL: 493 case R_STATS_RX_MCASTH: 494 r = s->stats.rx_mcast >> (32 * (addr & 1)); 495 break; 496 497 case R_MC: 498 case R_MWD: 499 case R_MRD: 500 r = s->mii.regs[addr & 3]; 501 break; 502 503 case R_UAW0: 504 case R_UAW1: 505 r = s->uaw[addr & 1]; 506 break; 507 508 case R_UAWU: 509 case R_UAWL: 510 r = s->ext_uaw[addr & 1]; 511 break; 512 513 case R_FMI: 514 r = s->fmi; 515 break; 516 517 case R_AF0: 518 case R_AF1: 519 r = s->maddr[s->fmi & 3][addr & 1]; 520 break; 521 522 case 0x8000 ... 0x83ff: 523 r = s->ext_mtable[addr - 0x8000]; 524 break; 525 526 default: 527 if (addr < ARRAY_SIZE(s->regs)) { 528 r = s->regs[addr]; 529 } 530 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 531 __func__, addr * 4, r)); 532 break; 533 } 534 return r; 535 } 536 537 static void enet_write(void *opaque, hwaddr addr, 538 uint64_t value, unsigned size) 539 { 540 XilinxAXIEnet *s = opaque; 541 struct TEMAC *t = &s->TEMAC; 542 543 addr >>= 2; 544 switch (addr) { 545 case R_RCW0: 546 case R_RCW1: 547 s->rcw[addr & 1] = value; 548 if ((addr & 1) && value & RCW1_RST) { 549 axienet_rx_reset(s); 550 } else { 551 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 552 } 553 break; 554 555 case R_TC: 556 s->tc = value; 557 if (value & TC_RST) { 558 axienet_tx_reset(s); 559 } 560 break; 561 562 case R_EMMC: 563 s->emmc = value; 564 break; 565 566 case R_PHYC: 567 s->phyc = value; 568 break; 569 570 case R_MC: 571 value &= ((1 << 7) - 1); 572 573 /* Enable the MII. */ 574 if (value & MC_EN) { 575 unsigned int miiclkdiv = value & ((1 << 6) - 1); 576 if (!miiclkdiv) { 577 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n"); 578 } 579 } 580 s->mii.mc = value; 581 break; 582 583 case R_MCR: { 584 unsigned int phyaddr = (value >> 24) & 0x1f; 585 unsigned int regaddr = (value >> 16) & 0x1f; 586 unsigned int op = (value >> 14) & 3; 587 unsigned int initiate = (value >> 11) & 1; 588 589 if (initiate) { 590 if (op == 1) { 591 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); 592 } else if (op == 2) { 593 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); 594 } else { 595 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op); 596 } 597 } 598 s->mii.mcr = value; 599 break; 600 } 601 602 case R_MWD: 603 case R_MRD: 604 s->mii.regs[addr & 3] = value; 605 break; 606 607 608 case R_UAW0: 609 case R_UAW1: 610 s->uaw[addr & 1] = value; 611 break; 612 613 case R_UAWL: 614 case R_UAWU: 615 s->ext_uaw[addr & 1] = value; 616 break; 617 618 case R_FMI: 619 s->fmi = value; 620 break; 621 622 case R_AF0: 623 case R_AF1: 624 s->maddr[s->fmi & 3][addr & 1] = value; 625 break; 626 627 case R_IS: 628 s->regs[addr] &= ~value; 629 break; 630 631 case 0x8000 ... 0x83ff: 632 s->ext_mtable[addr - 0x8000] = value; 633 break; 634 635 default: 636 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 637 __func__, addr * 4, (unsigned)value)); 638 if (addr < ARRAY_SIZE(s->regs)) { 639 s->regs[addr] = value; 640 } 641 break; 642 } 643 enet_update_irq(s); 644 } 645 646 static const MemoryRegionOps enet_ops = { 647 .read = enet_read, 648 .write = enet_write, 649 .endianness = DEVICE_LITTLE_ENDIAN, 650 }; 651 652 static int eth_can_rx(XilinxAXIEnet *s) 653 { 654 /* RX enabled? */ 655 return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s); 656 } 657 658 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) 659 { 660 int match = 1; 661 662 if (memcmp(buf, &f0, 4)) { 663 match = 0; 664 } 665 666 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { 667 match = 0; 668 } 669 670 return match; 671 } 672 673 static void axienet_eth_rx_notify(void *opaque) 674 { 675 XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); 676 677 while (s->rxappsize && stream_can_push(s->tx_control_dev, 678 axienet_eth_rx_notify, s)) { 679 size_t ret = stream_push(s->tx_control_dev, 680 (void *)s->rxapp + CONTROL_PAYLOAD_SIZE 681 - s->rxappsize, s->rxappsize, true); 682 s->rxappsize -= ret; 683 } 684 685 while (s->rxsize && stream_can_push(s->tx_data_dev, 686 axienet_eth_rx_notify, s)) { 687 size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, 688 s->rxsize, true); 689 s->rxsize -= ret; 690 s->rxpos += ret; 691 if (!s->rxsize) { 692 s->regs[R_IS] |= IS_RX_COMPLETE; 693 if (s->need_flush) { 694 s->need_flush = false; 695 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 696 } 697 } 698 } 699 enet_update_irq(s); 700 } 701 702 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 703 { 704 XilinxAXIEnet *s = qemu_get_nic_opaque(nc); 705 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 706 0xff, 0xff, 0xff}; 707 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; 708 uint32_t app[CONTROL_PAYLOAD_WORDS] = {0}; 709 int promisc = s->fmi & (1 << 31); 710 int unicast, broadcast, multicast, ip_multicast = 0; 711 uint32_t csum32; 712 uint16_t csum16; 713 int i; 714 715 DENET(qemu_log("%s: %zd bytes\n", __func__, size)); 716 717 if (!eth_can_rx(s)) { 718 s->need_flush = true; 719 return 0; 720 } 721 722 unicast = ~buf[0] & 0x1; 723 broadcast = memcmp(buf, sa_bcast, 6) == 0; 724 multicast = !unicast && !broadcast; 725 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { 726 ip_multicast = 1; 727 } 728 729 /* Jumbo or vlan sizes ? */ 730 if (!(s->rcw[1] & RCW1_JUM)) { 731 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { 732 return size; 733 } 734 } 735 736 /* Basic Address filters. If you want to use the extended filters 737 you'll generally have to place the ethernet mac into promiscuous mode 738 to avoid the basic filtering from dropping most frames. */ 739 if (!promisc) { 740 if (unicast) { 741 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { 742 return size; 743 } 744 } else { 745 if (broadcast) { 746 /* Broadcast. */ 747 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 748 return size; 749 } 750 } else { 751 int drop = 1; 752 753 /* Multicast. */ 754 if (s->regs[R_RAF] & RAF_MCAST_REJ) { 755 return size; 756 } 757 758 for (i = 0; i < 4; i++) { 759 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { 760 drop = 0; 761 break; 762 } 763 } 764 765 if (drop) { 766 return size; 767 } 768 } 769 } 770 } 771 772 /* Extended mcast filtering enabled? */ 773 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) { 774 if (unicast) { 775 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { 776 return size; 777 } 778 } else { 779 if (broadcast) { 780 /* Broadcast. ??? */ 781 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 782 return size; 783 } 784 } else { 785 int idx, bit; 786 787 /* Multicast. */ 788 if (!memcmp(buf, sa_ipmcast, 3)) { 789 return size; 790 } 791 792 idx = (buf[4] & 0x7f) << 8; 793 idx |= buf[5]; 794 795 bit = 1 << (idx & 0x1f); 796 idx >>= 5; 797 798 if (!(s->ext_mtable[idx] & bit)) { 799 return size; 800 } 801 } 802 } 803 } 804 805 if (size < 12) { 806 s->regs[R_IS] |= IS_RX_REJECT; 807 enet_update_irq(s); 808 return -1; 809 } 810 811 if (size > (s->c_rxmem - 4)) { 812 size = s->c_rxmem - 4; 813 } 814 815 memcpy(s->rxmem, buf, size); 816 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ 817 818 if (s->rcw[1] & RCW1_FCS) { 819 size += 4; /* fcs is inband. */ 820 } 821 822 app[0] = 5 << 28; 823 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); 824 /* Fold it once. */ 825 csum32 = (csum32 & 0xffff) + (csum32 >> 16); 826 /* And twice to get rid of possible carries. */ 827 csum16 = (csum32 & 0xffff) + (csum32 >> 16); 828 app[3] = csum16; 829 app[4] = size & 0xffff; 830 831 s->stats.rx_bytes += size; 832 s->stats.rx++; 833 if (multicast) { 834 s->stats.rx_mcast++; 835 app[2] |= 1 | (ip_multicast << 1); 836 } else if (broadcast) { 837 s->stats.rx_bcast++; 838 app[2] |= 1 << 3; 839 } 840 841 /* Good frame. */ 842 app[2] |= 1 << 6; 843 844 s->rxsize = size; 845 s->rxpos = 0; 846 for (i = 0; i < ARRAY_SIZE(app); ++i) { 847 app[i] = cpu_to_le32(app[i]); 848 } 849 s->rxappsize = CONTROL_PAYLOAD_SIZE; 850 memcpy(s->rxapp, app, s->rxappsize); 851 axienet_eth_rx_notify(s); 852 853 enet_update_irq(s); 854 return size; 855 } 856 857 static size_t 858 xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len, 859 bool eop) 860 { 861 int i; 862 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); 863 XilinxAXIEnet *s = cs->enet; 864 865 assert(eop); 866 if (len != CONTROL_PAYLOAD_SIZE) { 867 hw_error("AXI Enet requires %d byte control stream payload\n", 868 (int)CONTROL_PAYLOAD_SIZE); 869 } 870 871 memcpy(s->hdr, buf, len); 872 873 for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { 874 s->hdr[i] = le32_to_cpu(s->hdr[i]); 875 } 876 return len; 877 } 878 879 static size_t 880 xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, 881 bool eop) 882 { 883 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); 884 XilinxAXIEnet *s = ds->enet; 885 886 /* TX enable ? */ 887 if (!(s->tc & TC_TX)) { 888 return size; 889 } 890 891 if (s->txpos + size > s->c_txmem) { 892 qemu_log_mask(LOG_GUEST_ERROR, "%s: Packet larger than txmem\n", 893 TYPE_XILINX_AXI_ENET); 894 s->txpos = 0; 895 return size; 896 } 897 898 if (s->txpos == 0 && eop) { 899 /* Fast path single fragment. */ 900 s->txpos = size; 901 } else { 902 memcpy(s->txmem + s->txpos, buf, size); 903 buf = s->txmem; 904 s->txpos += size; 905 906 if (!eop) { 907 return size; 908 } 909 } 910 911 /* Jumbo or vlan sizes ? */ 912 if (!(s->tc & TC_JUM)) { 913 if (s->txpos > 1518 && s->txpos <= 1522 && !(s->tc & TC_VLAN)) { 914 s->txpos = 0; 915 return size; 916 } 917 } 918 919 if (s->hdr[0] & 1) { 920 unsigned int start_off = s->hdr[1] >> 16; 921 unsigned int write_off = s->hdr[1] & 0xffff; 922 uint32_t tmp_csum; 923 uint16_t csum; 924 925 tmp_csum = net_checksum_add(s->txpos - start_off, 926 buf + start_off); 927 /* Accumulate the seed. */ 928 tmp_csum += s->hdr[2] & 0xffff; 929 930 /* Fold the 32bit partial checksum. */ 931 csum = net_checksum_finish(tmp_csum); 932 933 /* Writeback. */ 934 buf[write_off] = csum >> 8; 935 buf[write_off + 1] = csum & 0xff; 936 } 937 938 qemu_send_packet(qemu_get_queue(s->nic), buf, s->txpos); 939 940 s->stats.tx_bytes += s->txpos; 941 s->regs[R_IS] |= IS_TX_COMPLETE; 942 enet_update_irq(s); 943 944 s->txpos = 0; 945 return size; 946 } 947 948 static NetClientInfo net_xilinx_enet_info = { 949 .type = NET_CLIENT_DRIVER_NIC, 950 .size = sizeof(NICState), 951 .receive = eth_rx, 952 }; 953 954 static void xilinx_enet_realize(DeviceState *dev, Error **errp) 955 { 956 XilinxAXIEnet *s = XILINX_AXI_ENET(dev); 957 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); 958 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM( 959 &s->rx_control_dev); 960 961 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", 962 (Object **) &ds->enet, 963 object_property_allow_set_link, 964 OBJ_PROP_LINK_STRONG); 965 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", 966 (Object **) &cs->enet, 967 object_property_allow_set_link, 968 OBJ_PROP_LINK_STRONG); 969 object_property_set_link(OBJECT(ds), "enet", OBJECT(s), &error_abort); 970 object_property_set_link(OBJECT(cs), "enet", OBJECT(s), &error_abort); 971 972 qemu_macaddr_default_if_unset(&s->conf.macaddr); 973 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, 974 object_get_typename(OBJECT(dev)), dev->id, s); 975 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 976 977 tdk_init(&s->TEMAC.phy); 978 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); 979 980 s->TEMAC.parent = s; 981 982 s->rxmem = g_malloc(s->c_rxmem); 983 s->txmem = g_malloc(s->c_txmem); 984 } 985 986 static void xilinx_enet_init(Object *obj) 987 { 988 XilinxAXIEnet *s = XILINX_AXI_ENET(obj); 989 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 990 991 object_initialize_child(OBJECT(s), "axistream-connected-target", 992 &s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM); 993 object_initialize_child(OBJECT(s), "axistream-control-connected-target", 994 &s->rx_control_dev, 995 TYPE_XILINX_AXI_ENET_CONTROL_STREAM); 996 sysbus_init_irq(sbd, &s->irq); 997 998 memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); 999 sysbus_init_mmio(sbd, &s->iomem); 1000 } 1001 1002 static Property xilinx_enet_properties[] = { 1003 DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), 1004 DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), 1005 DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), 1006 DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), 1007 DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, 1008 tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), 1009 DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, 1010 tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), 1011 DEFINE_PROP_END_OF_LIST(), 1012 }; 1013 1014 static void xilinx_enet_class_init(ObjectClass *klass, void *data) 1015 { 1016 DeviceClass *dc = DEVICE_CLASS(klass); 1017 1018 dc->realize = xilinx_enet_realize; 1019 device_class_set_props(dc, xilinx_enet_properties); 1020 dc->reset = xilinx_axienet_reset; 1021 } 1022 1023 static void xilinx_enet_control_stream_class_init(ObjectClass *klass, 1024 void *data) 1025 { 1026 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); 1027 1028 ssc->push = xilinx_axienet_control_stream_push; 1029 } 1030 1031 static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data) 1032 { 1033 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); 1034 1035 ssc->push = xilinx_axienet_data_stream_push; 1036 } 1037 1038 static const TypeInfo xilinx_enet_info = { 1039 .name = TYPE_XILINX_AXI_ENET, 1040 .parent = TYPE_SYS_BUS_DEVICE, 1041 .instance_size = sizeof(XilinxAXIEnet), 1042 .class_init = xilinx_enet_class_init, 1043 .instance_init = xilinx_enet_init, 1044 }; 1045 1046 static const TypeInfo xilinx_enet_data_stream_info = { 1047 .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, 1048 .parent = TYPE_OBJECT, 1049 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), 1050 .class_init = xilinx_enet_data_stream_class_init, 1051 .interfaces = (InterfaceInfo[]) { 1052 { TYPE_STREAM_SLAVE }, 1053 { } 1054 } 1055 }; 1056 1057 static const TypeInfo xilinx_enet_control_stream_info = { 1058 .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, 1059 .parent = TYPE_OBJECT, 1060 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), 1061 .class_init = xilinx_enet_control_stream_class_init, 1062 .interfaces = (InterfaceInfo[]) { 1063 { TYPE_STREAM_SLAVE }, 1064 { } 1065 } 1066 }; 1067 1068 static void xilinx_enet_register_types(void) 1069 { 1070 type_register_static(&xilinx_enet_info); 1071 type_register_static(&xilinx_enet_data_stream_info); 1072 type_register_static(&xilinx_enet_control_stream_info); 1073 } 1074 1075 type_init(xilinx_enet_register_types) 1076