1 /* 2 * QEMU model of Xilinx AXI-Ethernet. 3 * 4 * Copyright (c) 2011 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/sysbus.h" 26 #include "qemu/log.h" 27 #include "net/net.h" 28 #include "net/checksum.h" 29 #include "qapi/qmp/qerror.h" 30 31 #include "hw/stream.h" 32 33 #define DPHY(x) 34 35 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" 36 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream" 37 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream" 38 39 #define XILINX_AXI_ENET(obj) \ 40 OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET) 41 42 #define XILINX_AXI_ENET_DATA_STREAM(obj) \ 43 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ 44 TYPE_XILINX_AXI_ENET_DATA_STREAM) 45 46 #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \ 47 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ 48 TYPE_XILINX_AXI_ENET_CONTROL_STREAM) 49 50 /* Advertisement control register. */ 51 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 52 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 53 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 54 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 55 56 #define CONTROL_PAYLOAD_WORDS 5 57 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) 58 59 struct PHY { 60 uint32_t regs[32]; 61 62 int link; 63 64 unsigned int (*read)(struct PHY *phy, unsigned int req); 65 void (*write)(struct PHY *phy, unsigned int req, 66 unsigned int data); 67 }; 68 69 static unsigned int tdk_read(struct PHY *phy, unsigned int req) 70 { 71 int regnum; 72 unsigned r = 0; 73 74 regnum = req & 0x1f; 75 76 switch (regnum) { 77 case 1: 78 if (!phy->link) { 79 break; 80 } 81 /* MR1. */ 82 /* Speeds and modes. */ 83 r |= (1 << 13) | (1 << 14); 84 r |= (1 << 11) | (1 << 12); 85 r |= (1 << 5); /* Autoneg complete. */ 86 r |= (1 << 3); /* Autoneg able. */ 87 r |= (1 << 2); /* link. */ 88 r |= (1 << 1); /* link. */ 89 break; 90 case 5: 91 /* Link partner ability. 92 We are kind; always agree with whatever best mode 93 the guest advertises. */ 94 r = 1 << 14; /* Success. */ 95 /* Copy advertised modes. */ 96 r |= phy->regs[4] & (15 << 5); 97 /* Autoneg support. */ 98 r |= 1; 99 break; 100 case 17: 101 /* Marvell PHY on many xilinx boards. */ 102 r = 0x8000; /* 1000Mb */ 103 break; 104 case 18: 105 { 106 /* Diagnostics reg. */ 107 int duplex = 0; 108 int speed_100 = 0; 109 110 if (!phy->link) { 111 break; 112 } 113 114 /* Are we advertising 100 half or 100 duplex ? */ 115 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); 116 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); 117 118 /* Are we advertising 10 duplex or 100 duplex ? */ 119 duplex = !!(phy->regs[4] & ADVERTISE_100FULL); 120 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); 121 r = (speed_100 << 10) | (duplex << 11); 122 } 123 break; 124 125 default: 126 r = phy->regs[regnum]; 127 break; 128 } 129 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum)); 130 return r; 131 } 132 133 static void 134 tdk_write(struct PHY *phy, unsigned int req, unsigned int data) 135 { 136 int regnum; 137 138 regnum = req & 0x1f; 139 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data)); 140 switch (regnum) { 141 default: 142 phy->regs[regnum] = data; 143 break; 144 } 145 146 /* Unconditionally clear regs[BMCR][BMCR_RESET] */ 147 phy->regs[0] &= ~0x8000; 148 } 149 150 static void 151 tdk_init(struct PHY *phy) 152 { 153 phy->regs[0] = 0x3100; 154 /* PHY Id. */ 155 phy->regs[2] = 0x0300; 156 phy->regs[3] = 0xe400; 157 /* Autonegotiation advertisement reg. */ 158 phy->regs[4] = 0x01E1; 159 phy->link = 1; 160 161 phy->read = tdk_read; 162 phy->write = tdk_write; 163 } 164 165 struct MDIOBus { 166 /* bus. */ 167 int mdc; 168 int mdio; 169 170 /* decoder. */ 171 enum { 172 PREAMBLE, 173 SOF, 174 OPC, 175 ADDR, 176 REQ, 177 TURNAROUND, 178 DATA 179 } state; 180 unsigned int drive; 181 182 unsigned int cnt; 183 unsigned int addr; 184 unsigned int opc; 185 unsigned int req; 186 unsigned int data; 187 188 struct PHY *devs[32]; 189 }; 190 191 static void 192 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 193 { 194 bus->devs[addr & 0x1f] = phy; 195 } 196 197 #ifdef USE_THIS_DEAD_CODE 198 static void 199 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 200 { 201 bus->devs[addr & 0x1f] = NULL; 202 } 203 #endif 204 205 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, 206 unsigned int reg) 207 { 208 struct PHY *phy; 209 uint16_t data; 210 211 phy = bus->devs[addr]; 212 if (phy && phy->read) { 213 data = phy->read(phy, reg); 214 } else { 215 data = 0xffff; 216 } 217 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 218 return data; 219 } 220 221 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, 222 unsigned int reg, uint16_t data) 223 { 224 struct PHY *phy; 225 226 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 227 phy = bus->devs[addr]; 228 if (phy && phy->write) { 229 phy->write(phy, reg, data); 230 } 231 } 232 233 #define DENET(x) 234 235 #define R_RAF (0x000 / 4) 236 enum { 237 RAF_MCAST_REJ = (1 << 1), 238 RAF_BCAST_REJ = (1 << 2), 239 RAF_EMCF_EN = (1 << 12), 240 RAF_NEWFUNC_EN = (1 << 11) 241 }; 242 243 #define R_IS (0x00C / 4) 244 enum { 245 IS_HARD_ACCESS_COMPLETE = 1, 246 IS_AUTONEG = (1 << 1), 247 IS_RX_COMPLETE = (1 << 2), 248 IS_RX_REJECT = (1 << 3), 249 IS_TX_COMPLETE = (1 << 5), 250 IS_RX_DCM_LOCK = (1 << 6), 251 IS_MGM_RDY = (1 << 7), 252 IS_PHY_RST_DONE = (1 << 8), 253 }; 254 255 #define R_IP (0x010 / 4) 256 #define R_IE (0x014 / 4) 257 #define R_UAWL (0x020 / 4) 258 #define R_UAWU (0x024 / 4) 259 #define R_PPST (0x030 / 4) 260 enum { 261 PPST_LINKSTATUS = (1 << 0), 262 PPST_PHY_LINKSTATUS = (1 << 7), 263 }; 264 265 #define R_STATS_RX_BYTESL (0x200 / 4) 266 #define R_STATS_RX_BYTESH (0x204 / 4) 267 #define R_STATS_TX_BYTESL (0x208 / 4) 268 #define R_STATS_TX_BYTESH (0x20C / 4) 269 #define R_STATS_RXL (0x290 / 4) 270 #define R_STATS_RXH (0x294 / 4) 271 #define R_STATS_RX_BCASTL (0x2a0 / 4) 272 #define R_STATS_RX_BCASTH (0x2a4 / 4) 273 #define R_STATS_RX_MCASTL (0x2a8 / 4) 274 #define R_STATS_RX_MCASTH (0x2ac / 4) 275 276 #define R_RCW0 (0x400 / 4) 277 #define R_RCW1 (0x404 / 4) 278 enum { 279 RCW1_VLAN = (1 << 27), 280 RCW1_RX = (1 << 28), 281 RCW1_FCS = (1 << 29), 282 RCW1_JUM = (1 << 30), 283 RCW1_RST = (1 << 31), 284 }; 285 286 #define R_TC (0x408 / 4) 287 enum { 288 TC_VLAN = (1 << 27), 289 TC_TX = (1 << 28), 290 TC_FCS = (1 << 29), 291 TC_JUM = (1 << 30), 292 TC_RST = (1 << 31), 293 }; 294 295 #define R_EMMC (0x410 / 4) 296 enum { 297 EMMC_LINKSPEED_10MB = (0 << 30), 298 EMMC_LINKSPEED_100MB = (1 << 30), 299 EMMC_LINKSPEED_1000MB = (2 << 30), 300 }; 301 302 #define R_PHYC (0x414 / 4) 303 304 #define R_MC (0x500 / 4) 305 #define MC_EN (1 << 6) 306 307 #define R_MCR (0x504 / 4) 308 #define R_MWD (0x508 / 4) 309 #define R_MRD (0x50c / 4) 310 #define R_MIS (0x600 / 4) 311 #define R_MIP (0x620 / 4) 312 #define R_MIE (0x640 / 4) 313 #define R_MIC (0x640 / 4) 314 315 #define R_UAW0 (0x700 / 4) 316 #define R_UAW1 (0x704 / 4) 317 #define R_FMI (0x708 / 4) 318 #define R_AF0 (0x710 / 4) 319 #define R_AF1 (0x714 / 4) 320 #define R_MAX (0x34 / 4) 321 322 /* Indirect registers. */ 323 struct TEMAC { 324 struct MDIOBus mdio_bus; 325 struct PHY phy; 326 327 void *parent; 328 }; 329 330 typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave; 331 typedef struct XilinxAXIEnet XilinxAXIEnet; 332 333 struct XilinxAXIEnetStreamSlave { 334 Object parent; 335 336 struct XilinxAXIEnet *enet; 337 } ; 338 339 struct XilinxAXIEnet { 340 SysBusDevice busdev; 341 MemoryRegion iomem; 342 qemu_irq irq; 343 StreamSlave *tx_data_dev; 344 StreamSlave *tx_control_dev; 345 XilinxAXIEnetStreamSlave rx_data_dev; 346 XilinxAXIEnetStreamSlave rx_control_dev; 347 NICState *nic; 348 NICConf conf; 349 350 351 uint32_t c_rxmem; 352 uint32_t c_txmem; 353 uint32_t c_phyaddr; 354 355 struct TEMAC TEMAC; 356 357 /* MII regs. */ 358 union { 359 uint32_t regs[4]; 360 struct { 361 uint32_t mc; 362 uint32_t mcr; 363 uint32_t mwd; 364 uint32_t mrd; 365 }; 366 } mii; 367 368 struct { 369 uint64_t rx_bytes; 370 uint64_t tx_bytes; 371 372 uint64_t rx; 373 uint64_t rx_bcast; 374 uint64_t rx_mcast; 375 } stats; 376 377 /* Receive configuration words. */ 378 uint32_t rcw[2]; 379 /* Transmit config. */ 380 uint32_t tc; 381 uint32_t emmc; 382 uint32_t phyc; 383 384 /* Unicast Address Word. */ 385 uint32_t uaw[2]; 386 /* Unicast address filter used with extended mcast. */ 387 uint32_t ext_uaw[2]; 388 uint32_t fmi; 389 390 uint32_t regs[R_MAX]; 391 392 /* Multicast filter addrs. */ 393 uint32_t maddr[4][2]; 394 /* 32K x 1 lookup filter. */ 395 uint32_t ext_mtable[1024]; 396 397 uint32_t hdr[CONTROL_PAYLOAD_WORDS]; 398 399 uint8_t *rxmem; 400 uint32_t rxsize; 401 uint32_t rxpos; 402 403 uint8_t rxapp[CONTROL_PAYLOAD_SIZE]; 404 uint32_t rxappsize; 405 }; 406 407 static void axienet_rx_reset(XilinxAXIEnet *s) 408 { 409 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; 410 } 411 412 static void axienet_tx_reset(XilinxAXIEnet *s) 413 { 414 s->tc = TC_JUM | TC_TX | TC_VLAN; 415 } 416 417 static inline int axienet_rx_resetting(XilinxAXIEnet *s) 418 { 419 return s->rcw[1] & RCW1_RST; 420 } 421 422 static inline int axienet_rx_enabled(XilinxAXIEnet *s) 423 { 424 return s->rcw[1] & RCW1_RX; 425 } 426 427 static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) 428 { 429 return !!(s->regs[R_RAF] & RAF_EMCF_EN); 430 } 431 432 static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) 433 { 434 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); 435 } 436 437 static void xilinx_axienet_reset(DeviceState *d) 438 { 439 XilinxAXIEnet *s = XILINX_AXI_ENET(d); 440 441 axienet_rx_reset(s); 442 axienet_tx_reset(s); 443 444 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; 445 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; 446 447 s->emmc = EMMC_LINKSPEED_100MB; 448 } 449 450 static void enet_update_irq(XilinxAXIEnet *s) 451 { 452 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; 453 qemu_set_irq(s->irq, !!s->regs[R_IP]); 454 } 455 456 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) 457 { 458 XilinxAXIEnet *s = opaque; 459 uint32_t r = 0; 460 addr >>= 2; 461 462 switch (addr) { 463 case R_RCW0: 464 case R_RCW1: 465 r = s->rcw[addr & 1]; 466 break; 467 468 case R_TC: 469 r = s->tc; 470 break; 471 472 case R_EMMC: 473 r = s->emmc; 474 break; 475 476 case R_PHYC: 477 r = s->phyc; 478 break; 479 480 case R_MCR: 481 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ 482 break; 483 484 case R_STATS_RX_BYTESL: 485 case R_STATS_RX_BYTESH: 486 r = s->stats.rx_bytes >> (32 * (addr & 1)); 487 break; 488 489 case R_STATS_TX_BYTESL: 490 case R_STATS_TX_BYTESH: 491 r = s->stats.tx_bytes >> (32 * (addr & 1)); 492 break; 493 494 case R_STATS_RXL: 495 case R_STATS_RXH: 496 r = s->stats.rx >> (32 * (addr & 1)); 497 break; 498 case R_STATS_RX_BCASTL: 499 case R_STATS_RX_BCASTH: 500 r = s->stats.rx_bcast >> (32 * (addr & 1)); 501 break; 502 case R_STATS_RX_MCASTL: 503 case R_STATS_RX_MCASTH: 504 r = s->stats.rx_mcast >> (32 * (addr & 1)); 505 break; 506 507 case R_MC: 508 case R_MWD: 509 case R_MRD: 510 r = s->mii.regs[addr & 3]; 511 break; 512 513 case R_UAW0: 514 case R_UAW1: 515 r = s->uaw[addr & 1]; 516 break; 517 518 case R_UAWU: 519 case R_UAWL: 520 r = s->ext_uaw[addr & 1]; 521 break; 522 523 case R_FMI: 524 r = s->fmi; 525 break; 526 527 case R_AF0: 528 case R_AF1: 529 r = s->maddr[s->fmi & 3][addr & 1]; 530 break; 531 532 case 0x8000 ... 0x83ff: 533 r = s->ext_mtable[addr - 0x8000]; 534 break; 535 536 default: 537 if (addr < ARRAY_SIZE(s->regs)) { 538 r = s->regs[addr]; 539 } 540 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 541 __func__, addr * 4, r)); 542 break; 543 } 544 return r; 545 } 546 547 static void enet_write(void *opaque, hwaddr addr, 548 uint64_t value, unsigned size) 549 { 550 XilinxAXIEnet *s = opaque; 551 struct TEMAC *t = &s->TEMAC; 552 553 addr >>= 2; 554 switch (addr) { 555 case R_RCW0: 556 case R_RCW1: 557 s->rcw[addr & 1] = value; 558 if ((addr & 1) && value & RCW1_RST) { 559 axienet_rx_reset(s); 560 } else { 561 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 562 } 563 break; 564 565 case R_TC: 566 s->tc = value; 567 if (value & TC_RST) { 568 axienet_tx_reset(s); 569 } 570 break; 571 572 case R_EMMC: 573 s->emmc = value; 574 break; 575 576 case R_PHYC: 577 s->phyc = value; 578 break; 579 580 case R_MC: 581 value &= ((1 << 7) - 1); 582 583 /* Enable the MII. */ 584 if (value & MC_EN) { 585 unsigned int miiclkdiv = value & ((1 << 6) - 1); 586 if (!miiclkdiv) { 587 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n"); 588 } 589 } 590 s->mii.mc = value; 591 break; 592 593 case R_MCR: { 594 unsigned int phyaddr = (value >> 24) & 0x1f; 595 unsigned int regaddr = (value >> 16) & 0x1f; 596 unsigned int op = (value >> 14) & 3; 597 unsigned int initiate = (value >> 11) & 1; 598 599 if (initiate) { 600 if (op == 1) { 601 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); 602 } else if (op == 2) { 603 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); 604 } else { 605 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op); 606 } 607 } 608 s->mii.mcr = value; 609 break; 610 } 611 612 case R_MWD: 613 case R_MRD: 614 s->mii.regs[addr & 3] = value; 615 break; 616 617 618 case R_UAW0: 619 case R_UAW1: 620 s->uaw[addr & 1] = value; 621 break; 622 623 case R_UAWL: 624 case R_UAWU: 625 s->ext_uaw[addr & 1] = value; 626 break; 627 628 case R_FMI: 629 s->fmi = value; 630 break; 631 632 case R_AF0: 633 case R_AF1: 634 s->maddr[s->fmi & 3][addr & 1] = value; 635 break; 636 637 case R_IS: 638 s->regs[addr] &= ~value; 639 break; 640 641 case 0x8000 ... 0x83ff: 642 s->ext_mtable[addr - 0x8000] = value; 643 break; 644 645 default: 646 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 647 __func__, addr * 4, (unsigned)value)); 648 if (addr < ARRAY_SIZE(s->regs)) { 649 s->regs[addr] = value; 650 } 651 break; 652 } 653 enet_update_irq(s); 654 } 655 656 static const MemoryRegionOps enet_ops = { 657 .read = enet_read, 658 .write = enet_write, 659 .endianness = DEVICE_LITTLE_ENDIAN, 660 }; 661 662 static int eth_can_rx(NetClientState *nc) 663 { 664 XilinxAXIEnet *s = qemu_get_nic_opaque(nc); 665 666 /* RX enabled? */ 667 return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s); 668 } 669 670 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) 671 { 672 int match = 1; 673 674 if (memcmp(buf, &f0, 4)) { 675 match = 0; 676 } 677 678 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { 679 match = 0; 680 } 681 682 return match; 683 } 684 685 static void axienet_eth_rx_notify(void *opaque) 686 { 687 XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); 688 689 while (s->rxappsize && stream_can_push(s->tx_control_dev, 690 axienet_eth_rx_notify, s)) { 691 size_t ret = stream_push(s->tx_control_dev, 692 (void *)s->rxapp + CONTROL_PAYLOAD_SIZE 693 - s->rxappsize, s->rxappsize); 694 s->rxappsize -= ret; 695 } 696 697 while (s->rxsize && stream_can_push(s->tx_data_dev, 698 axienet_eth_rx_notify, s)) { 699 size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, 700 s->rxsize); 701 s->rxsize -= ret; 702 s->rxpos += ret; 703 if (!s->rxsize) { 704 s->regs[R_IS] |= IS_RX_COMPLETE; 705 } 706 } 707 enet_update_irq(s); 708 } 709 710 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 711 { 712 XilinxAXIEnet *s = qemu_get_nic_opaque(nc); 713 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 714 0xff, 0xff, 0xff}; 715 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; 716 uint32_t app[CONTROL_PAYLOAD_WORDS] = {0}; 717 int promisc = s->fmi & (1 << 31); 718 int unicast, broadcast, multicast, ip_multicast = 0; 719 uint32_t csum32; 720 uint16_t csum16; 721 int i; 722 723 DENET(qemu_log("%s: %zd bytes\n", __func__, size)); 724 725 unicast = ~buf[0] & 0x1; 726 broadcast = memcmp(buf, sa_bcast, 6) == 0; 727 multicast = !unicast && !broadcast; 728 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { 729 ip_multicast = 1; 730 } 731 732 /* Jumbo or vlan sizes ? */ 733 if (!(s->rcw[1] & RCW1_JUM)) { 734 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { 735 return size; 736 } 737 } 738 739 /* Basic Address filters. If you want to use the extended filters 740 you'll generally have to place the ethernet mac into promiscuous mode 741 to avoid the basic filtering from dropping most frames. */ 742 if (!promisc) { 743 if (unicast) { 744 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { 745 return size; 746 } 747 } else { 748 if (broadcast) { 749 /* Broadcast. */ 750 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 751 return size; 752 } 753 } else { 754 int drop = 1; 755 756 /* Multicast. */ 757 if (s->regs[R_RAF] & RAF_MCAST_REJ) { 758 return size; 759 } 760 761 for (i = 0; i < 4; i++) { 762 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { 763 drop = 0; 764 break; 765 } 766 } 767 768 if (drop) { 769 return size; 770 } 771 } 772 } 773 } 774 775 /* Extended mcast filtering enabled? */ 776 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) { 777 if (unicast) { 778 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { 779 return size; 780 } 781 } else { 782 if (broadcast) { 783 /* Broadcast. ??? */ 784 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 785 return size; 786 } 787 } else { 788 int idx, bit; 789 790 /* Multicast. */ 791 if (!memcmp(buf, sa_ipmcast, 3)) { 792 return size; 793 } 794 795 idx = (buf[4] & 0x7f) << 8; 796 idx |= buf[5]; 797 798 bit = 1 << (idx & 0x1f); 799 idx >>= 5; 800 801 if (!(s->ext_mtable[idx] & bit)) { 802 return size; 803 } 804 } 805 } 806 } 807 808 if (size < 12) { 809 s->regs[R_IS] |= IS_RX_REJECT; 810 enet_update_irq(s); 811 return -1; 812 } 813 814 if (size > (s->c_rxmem - 4)) { 815 size = s->c_rxmem - 4; 816 } 817 818 memcpy(s->rxmem, buf, size); 819 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ 820 821 if (s->rcw[1] & RCW1_FCS) { 822 size += 4; /* fcs is inband. */ 823 } 824 825 app[0] = 5 << 28; 826 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); 827 /* Fold it once. */ 828 csum32 = (csum32 & 0xffff) + (csum32 >> 16); 829 /* And twice to get rid of possible carries. */ 830 csum16 = (csum32 & 0xffff) + (csum32 >> 16); 831 app[3] = csum16; 832 app[4] = size & 0xffff; 833 834 s->stats.rx_bytes += size; 835 s->stats.rx++; 836 if (multicast) { 837 s->stats.rx_mcast++; 838 app[2] |= 1 | (ip_multicast << 1); 839 } else if (broadcast) { 840 s->stats.rx_bcast++; 841 app[2] |= 1 << 3; 842 } 843 844 /* Good frame. */ 845 app[2] |= 1 << 6; 846 847 s->rxsize = size; 848 s->rxpos = 0; 849 for (i = 0; i < ARRAY_SIZE(app); ++i) { 850 app[i] = cpu_to_le32(app[i]); 851 } 852 s->rxappsize = CONTROL_PAYLOAD_SIZE; 853 memcpy(s->rxapp, app, s->rxappsize); 854 axienet_eth_rx_notify(s); 855 856 enet_update_irq(s); 857 return size; 858 } 859 860 static void eth_cleanup(NetClientState *nc) 861 { 862 /* FIXME. */ 863 XilinxAXIEnet *s = qemu_get_nic_opaque(nc); 864 g_free(s->rxmem); 865 g_free(s); 866 } 867 868 static size_t 869 xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len) 870 { 871 int i; 872 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); 873 XilinxAXIEnet *s = cs->enet; 874 875 if (len != CONTROL_PAYLOAD_SIZE) { 876 hw_error("AXI Enet requires %d byte control stream payload\n", 877 (int)CONTROL_PAYLOAD_SIZE); 878 } 879 880 memcpy(s->hdr, buf, len); 881 882 for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { 883 s->hdr[i] = le32_to_cpu(s->hdr[i]); 884 } 885 return len; 886 } 887 888 static size_t 889 xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size) 890 { 891 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); 892 XilinxAXIEnet *s = ds->enet; 893 894 /* TX enable ? */ 895 if (!(s->tc & TC_TX)) { 896 return size; 897 } 898 899 /* Jumbo or vlan sizes ? */ 900 if (!(s->tc & TC_JUM)) { 901 if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) { 902 return size; 903 } 904 } 905 906 if (s->hdr[0] & 1) { 907 unsigned int start_off = s->hdr[1] >> 16; 908 unsigned int write_off = s->hdr[1] & 0xffff; 909 uint32_t tmp_csum; 910 uint16_t csum; 911 912 tmp_csum = net_checksum_add(size - start_off, 913 (uint8_t *)buf + start_off); 914 /* Accumulate the seed. */ 915 tmp_csum += s->hdr[2] & 0xffff; 916 917 /* Fold the 32bit partial checksum. */ 918 csum = net_checksum_finish(tmp_csum); 919 920 /* Writeback. */ 921 buf[write_off] = csum >> 8; 922 buf[write_off + 1] = csum & 0xff; 923 } 924 925 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 926 927 s->stats.tx_bytes += size; 928 s->regs[R_IS] |= IS_TX_COMPLETE; 929 enet_update_irq(s); 930 931 return size; 932 } 933 934 static NetClientInfo net_xilinx_enet_info = { 935 .type = NET_CLIENT_OPTIONS_KIND_NIC, 936 .size = sizeof(NICState), 937 .can_receive = eth_can_rx, 938 .receive = eth_rx, 939 .cleanup = eth_cleanup, 940 }; 941 942 static void xilinx_enet_realize(DeviceState *dev, Error **errp) 943 { 944 XilinxAXIEnet *s = XILINX_AXI_ENET(dev); 945 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); 946 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM( 947 &s->rx_control_dev); 948 Error *local_err = NULL; 949 950 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", 951 (Object **) &ds->enet, 952 object_property_allow_set_link, 953 OBJ_PROP_LINK_UNREF_ON_RELEASE, 954 &local_err); 955 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", 956 (Object **) &cs->enet, 957 object_property_allow_set_link, 958 OBJ_PROP_LINK_UNREF_ON_RELEASE, 959 &local_err); 960 if (local_err) { 961 goto xilinx_enet_realize_fail; 962 } 963 object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_err); 964 object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_err); 965 if (local_err) { 966 goto xilinx_enet_realize_fail; 967 } 968 969 qemu_macaddr_default_if_unset(&s->conf.macaddr); 970 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, 971 object_get_typename(OBJECT(dev)), dev->id, s); 972 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 973 974 tdk_init(&s->TEMAC.phy); 975 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); 976 977 s->TEMAC.parent = s; 978 979 s->rxmem = g_malloc(s->c_rxmem); 980 return; 981 982 xilinx_enet_realize_fail: 983 if (!*errp) { 984 *errp = local_err; 985 } 986 } 987 988 static void xilinx_enet_init(Object *obj) 989 { 990 XilinxAXIEnet *s = XILINX_AXI_ENET(obj); 991 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 992 993 object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, 994 (Object **) &s->tx_data_dev, 995 qdev_prop_allow_set_link_before_realize, 996 OBJ_PROP_LINK_UNREF_ON_RELEASE, 997 &error_abort); 998 object_property_add_link(obj, "axistream-control-connected", 999 TYPE_STREAM_SLAVE, 1000 (Object **) &s->tx_control_dev, 1001 qdev_prop_allow_set_link_before_realize, 1002 OBJ_PROP_LINK_UNREF_ON_RELEASE, 1003 &error_abort); 1004 1005 object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), 1006 TYPE_XILINX_AXI_ENET_DATA_STREAM); 1007 object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), 1008 TYPE_XILINX_AXI_ENET_CONTROL_STREAM); 1009 object_property_add_child(OBJECT(s), "axistream-connected-target", 1010 (Object *)&s->rx_data_dev, &error_abort); 1011 object_property_add_child(OBJECT(s), "axistream-control-connected-target", 1012 (Object *)&s->rx_control_dev, &error_abort); 1013 1014 sysbus_init_irq(sbd, &s->irq); 1015 1016 memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); 1017 sysbus_init_mmio(sbd, &s->iomem); 1018 } 1019 1020 static Property xilinx_enet_properties[] = { 1021 DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), 1022 DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), 1023 DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), 1024 DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), 1025 DEFINE_PROP_END_OF_LIST(), 1026 }; 1027 1028 static void xilinx_enet_class_init(ObjectClass *klass, void *data) 1029 { 1030 DeviceClass *dc = DEVICE_CLASS(klass); 1031 1032 dc->realize = xilinx_enet_realize; 1033 dc->props = xilinx_enet_properties; 1034 dc->reset = xilinx_axienet_reset; 1035 } 1036 1037 static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data) 1038 { 1039 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); 1040 1041 ssc->push = data; 1042 } 1043 1044 static const TypeInfo xilinx_enet_info = { 1045 .name = TYPE_XILINX_AXI_ENET, 1046 .parent = TYPE_SYS_BUS_DEVICE, 1047 .instance_size = sizeof(XilinxAXIEnet), 1048 .class_init = xilinx_enet_class_init, 1049 .instance_init = xilinx_enet_init, 1050 }; 1051 1052 static const TypeInfo xilinx_enet_data_stream_info = { 1053 .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, 1054 .parent = TYPE_OBJECT, 1055 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), 1056 .class_init = xilinx_enet_stream_class_init, 1057 .class_data = xilinx_axienet_data_stream_push, 1058 .interfaces = (InterfaceInfo[]) { 1059 { TYPE_STREAM_SLAVE }, 1060 { } 1061 } 1062 }; 1063 1064 static const TypeInfo xilinx_enet_control_stream_info = { 1065 .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, 1066 .parent = TYPE_OBJECT, 1067 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), 1068 .class_init = xilinx_enet_stream_class_init, 1069 .class_data = xilinx_axienet_control_stream_push, 1070 .interfaces = (InterfaceInfo[]) { 1071 { TYPE_STREAM_SLAVE }, 1072 { } 1073 } 1074 }; 1075 1076 static void xilinx_enet_register_types(void) 1077 { 1078 type_register_static(&xilinx_enet_info); 1079 type_register_static(&xilinx_enet_data_stream_info); 1080 type_register_static(&xilinx_enet_control_stream_info); 1081 } 1082 1083 type_init(xilinx_enet_register_types) 1084