1 /* 2 * QEMU model of Xilinx AXI-Ethernet. 3 * 4 * Copyright (c) 2011 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/sysbus.h" 28 #include "qapi/error.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 #include "net/net.h" 32 #include "net/checksum.h" 33 34 #include "hw/hw.h" 35 #include "hw/irq.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/stream.h" 38 #include "qom/object.h" 39 40 #define DPHY(x) 41 42 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" 43 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream" 44 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream" 45 46 typedef struct XilinxAXIEnet XilinxAXIEnet; 47 DECLARE_INSTANCE_CHECKER(XilinxAXIEnet, XILINX_AXI_ENET, 48 TYPE_XILINX_AXI_ENET) 49 50 typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave; 51 DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave, XILINX_AXI_ENET_DATA_STREAM, 52 TYPE_XILINX_AXI_ENET_DATA_STREAM) 53 54 DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave, XILINX_AXI_ENET_CONTROL_STREAM, 55 TYPE_XILINX_AXI_ENET_CONTROL_STREAM) 56 57 /* Advertisement control register. */ 58 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 59 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 60 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 61 62 #define CONTROL_PAYLOAD_WORDS 5 63 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) 64 65 struct PHY { 66 uint32_t regs[32]; 67 68 int link; 69 70 unsigned int (*read)(struct PHY *phy, unsigned int req); 71 void (*write)(struct PHY *phy, unsigned int req, 72 unsigned int data); 73 }; 74 75 static unsigned int tdk_read(struct PHY *phy, unsigned int req) 76 { 77 int regnum; 78 unsigned r = 0; 79 80 regnum = req & 0x1f; 81 82 switch (regnum) { 83 case 1: 84 if (!phy->link) { 85 break; 86 } 87 /* MR1. */ 88 /* Speeds and modes. */ 89 r |= (1 << 13) | (1 << 14); 90 r |= (1 << 11) | (1 << 12); 91 r |= (1 << 5); /* Autoneg complete. */ 92 r |= (1 << 3); /* Autoneg able. */ 93 r |= (1 << 2); /* link. */ 94 r |= (1 << 1); /* link. */ 95 break; 96 case 5: 97 /* Link partner ability. 98 We are kind; always agree with whatever best mode 99 the guest advertises. */ 100 r = 1 << 14; /* Success. */ 101 /* Copy advertised modes. */ 102 r |= phy->regs[4] & (15 << 5); 103 /* Autoneg support. */ 104 r |= 1; 105 break; 106 case 17: 107 /* Marvell PHY on many xilinx boards. */ 108 r = 0x8000; /* 1000Mb */ 109 break; 110 case 18: 111 { 112 /* Diagnostics reg. */ 113 int duplex = 0; 114 int speed_100 = 0; 115 116 if (!phy->link) { 117 break; 118 } 119 120 /* Are we advertising 100 half or 100 duplex ? */ 121 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); 122 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); 123 124 /* Are we advertising 10 duplex or 100 duplex ? */ 125 duplex = !!(phy->regs[4] & ADVERTISE_100FULL); 126 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); 127 r = (speed_100 << 10) | (duplex << 11); 128 } 129 break; 130 131 default: 132 r = phy->regs[regnum]; 133 break; 134 } 135 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum)); 136 return r; 137 } 138 139 static void 140 tdk_write(struct PHY *phy, unsigned int req, unsigned int data) 141 { 142 int regnum; 143 144 regnum = req & 0x1f; 145 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data)); 146 switch (regnum) { 147 default: 148 phy->regs[regnum] = data; 149 break; 150 } 151 152 /* Unconditionally clear regs[BMCR][BMCR_RESET] and auto-neg */ 153 phy->regs[0] &= ~0x8200; 154 } 155 156 static void 157 tdk_init(struct PHY *phy) 158 { 159 phy->regs[0] = 0x3100; 160 /* PHY Id. */ 161 phy->regs[2] = 0x0300; 162 phy->regs[3] = 0xe400; 163 /* Autonegotiation advertisement reg. */ 164 phy->regs[4] = 0x01E1; 165 phy->link = 1; 166 167 phy->read = tdk_read; 168 phy->write = tdk_write; 169 } 170 171 struct MDIOBus { 172 struct PHY *devs[32]; 173 }; 174 175 static void 176 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 177 { 178 bus->devs[addr & 0x1f] = phy; 179 } 180 181 #ifdef USE_THIS_DEAD_CODE 182 static void 183 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 184 { 185 bus->devs[addr & 0x1f] = NULL; 186 } 187 #endif 188 189 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, 190 unsigned int reg) 191 { 192 struct PHY *phy; 193 uint16_t data; 194 195 phy = bus->devs[addr]; 196 if (phy && phy->read) { 197 data = phy->read(phy, reg); 198 } else { 199 data = 0xffff; 200 } 201 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 202 return data; 203 } 204 205 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, 206 unsigned int reg, uint16_t data) 207 { 208 struct PHY *phy; 209 210 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 211 phy = bus->devs[addr]; 212 if (phy && phy->write) { 213 phy->write(phy, reg, data); 214 } 215 } 216 217 #define DENET(x) 218 219 #define R_RAF (0x000 / 4) 220 enum { 221 RAF_MCAST_REJ = (1 << 1), 222 RAF_BCAST_REJ = (1 << 2), 223 RAF_EMCF_EN = (1 << 12), 224 RAF_NEWFUNC_EN = (1 << 11) 225 }; 226 227 #define R_IS (0x00C / 4) 228 enum { 229 IS_HARD_ACCESS_COMPLETE = 1, 230 IS_AUTONEG = (1 << 1), 231 IS_RX_COMPLETE = (1 << 2), 232 IS_RX_REJECT = (1 << 3), 233 IS_TX_COMPLETE = (1 << 5), 234 IS_RX_DCM_LOCK = (1 << 6), 235 IS_MGM_RDY = (1 << 7), 236 IS_PHY_RST_DONE = (1 << 8), 237 }; 238 239 #define R_IP (0x010 / 4) 240 #define R_IE (0x014 / 4) 241 #define R_UAWL (0x020 / 4) 242 #define R_UAWU (0x024 / 4) 243 #define R_PPST (0x030 / 4) 244 enum { 245 PPST_LINKSTATUS = (1 << 0), 246 PPST_PHY_LINKSTATUS = (1 << 7), 247 }; 248 249 #define R_STATS_RX_BYTESL (0x200 / 4) 250 #define R_STATS_RX_BYTESH (0x204 / 4) 251 #define R_STATS_TX_BYTESL (0x208 / 4) 252 #define R_STATS_TX_BYTESH (0x20C / 4) 253 #define R_STATS_RXL (0x290 / 4) 254 #define R_STATS_RXH (0x294 / 4) 255 #define R_STATS_RX_BCASTL (0x2a0 / 4) 256 #define R_STATS_RX_BCASTH (0x2a4 / 4) 257 #define R_STATS_RX_MCASTL (0x2a8 / 4) 258 #define R_STATS_RX_MCASTH (0x2ac / 4) 259 260 #define R_RCW0 (0x400 / 4) 261 #define R_RCW1 (0x404 / 4) 262 enum { 263 RCW1_VLAN = (1 << 27), 264 RCW1_RX = (1 << 28), 265 RCW1_FCS = (1 << 29), 266 RCW1_JUM = (1 << 30), 267 RCW1_RST = (1 << 31), 268 }; 269 270 #define R_TC (0x408 / 4) 271 enum { 272 TC_VLAN = (1 << 27), 273 TC_TX = (1 << 28), 274 TC_FCS = (1 << 29), 275 TC_JUM = (1 << 30), 276 TC_RST = (1 << 31), 277 }; 278 279 #define R_EMMC (0x410 / 4) 280 enum { 281 EMMC_LINKSPEED_10MB = (0 << 30), 282 EMMC_LINKSPEED_100MB = (1 << 30), 283 EMMC_LINKSPEED_1000MB = (2 << 30), 284 }; 285 286 #define R_PHYC (0x414 / 4) 287 288 #define R_MC (0x500 / 4) 289 #define MC_EN (1 << 6) 290 291 #define R_MCR (0x504 / 4) 292 #define R_MWD (0x508 / 4) 293 #define R_MRD (0x50c / 4) 294 #define R_MIS (0x600 / 4) 295 #define R_MIP (0x620 / 4) 296 #define R_MIE (0x640 / 4) 297 #define R_MIC (0x640 / 4) 298 299 #define R_UAW0 (0x700 / 4) 300 #define R_UAW1 (0x704 / 4) 301 #define R_FMI (0x708 / 4) 302 #define R_AF0 (0x710 / 4) 303 #define R_AF1 (0x714 / 4) 304 #define R_MAX (0x34 / 4) 305 306 /* Indirect registers. */ 307 struct TEMAC { 308 struct MDIOBus mdio_bus; 309 struct PHY phy; 310 311 void *parent; 312 }; 313 314 315 struct XilinxAXIEnetStreamSlave { 316 Object parent; 317 318 struct XilinxAXIEnet *enet; 319 } ; 320 321 struct XilinxAXIEnet { 322 SysBusDevice busdev; 323 MemoryRegion iomem; 324 qemu_irq irq; 325 StreamSlave *tx_data_dev; 326 StreamSlave *tx_control_dev; 327 XilinxAXIEnetStreamSlave rx_data_dev; 328 XilinxAXIEnetStreamSlave rx_control_dev; 329 NICState *nic; 330 NICConf conf; 331 332 333 uint32_t c_rxmem; 334 uint32_t c_txmem; 335 uint32_t c_phyaddr; 336 337 struct TEMAC TEMAC; 338 339 /* MII regs. */ 340 union { 341 uint32_t regs[4]; 342 struct { 343 uint32_t mc; 344 uint32_t mcr; 345 uint32_t mwd; 346 uint32_t mrd; 347 }; 348 } mii; 349 350 struct { 351 uint64_t rx_bytes; 352 uint64_t tx_bytes; 353 354 uint64_t rx; 355 uint64_t rx_bcast; 356 uint64_t rx_mcast; 357 } stats; 358 359 /* Receive configuration words. */ 360 uint32_t rcw[2]; 361 /* Transmit config. */ 362 uint32_t tc; 363 uint32_t emmc; 364 uint32_t phyc; 365 366 /* Unicast Address Word. */ 367 uint32_t uaw[2]; 368 /* Unicast address filter used with extended mcast. */ 369 uint32_t ext_uaw[2]; 370 uint32_t fmi; 371 372 uint32_t regs[R_MAX]; 373 374 /* Multicast filter addrs. */ 375 uint32_t maddr[4][2]; 376 /* 32K x 1 lookup filter. */ 377 uint32_t ext_mtable[1024]; 378 379 uint32_t hdr[CONTROL_PAYLOAD_WORDS]; 380 381 uint8_t *txmem; 382 uint32_t txpos; 383 384 uint8_t *rxmem; 385 uint32_t rxsize; 386 uint32_t rxpos; 387 388 uint8_t rxapp[CONTROL_PAYLOAD_SIZE]; 389 uint32_t rxappsize; 390 391 /* Whether axienet_eth_rx_notify should flush incoming queue. */ 392 bool need_flush; 393 }; 394 395 static void axienet_rx_reset(XilinxAXIEnet *s) 396 { 397 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; 398 } 399 400 static void axienet_tx_reset(XilinxAXIEnet *s) 401 { 402 s->tc = TC_JUM | TC_TX | TC_VLAN; 403 s->txpos = 0; 404 } 405 406 static inline int axienet_rx_resetting(XilinxAXIEnet *s) 407 { 408 return s->rcw[1] & RCW1_RST; 409 } 410 411 static inline int axienet_rx_enabled(XilinxAXIEnet *s) 412 { 413 return s->rcw[1] & RCW1_RX; 414 } 415 416 static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) 417 { 418 return !!(s->regs[R_RAF] & RAF_EMCF_EN); 419 } 420 421 static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) 422 { 423 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); 424 } 425 426 static void xilinx_axienet_reset(DeviceState *d) 427 { 428 XilinxAXIEnet *s = XILINX_AXI_ENET(d); 429 430 axienet_rx_reset(s); 431 axienet_tx_reset(s); 432 433 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; 434 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; 435 436 s->emmc = EMMC_LINKSPEED_100MB; 437 } 438 439 static void enet_update_irq(XilinxAXIEnet *s) 440 { 441 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; 442 qemu_set_irq(s->irq, !!s->regs[R_IP]); 443 } 444 445 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) 446 { 447 XilinxAXIEnet *s = opaque; 448 uint32_t r = 0; 449 addr >>= 2; 450 451 switch (addr) { 452 case R_RCW0: 453 case R_RCW1: 454 r = s->rcw[addr & 1]; 455 break; 456 457 case R_TC: 458 r = s->tc; 459 break; 460 461 case R_EMMC: 462 r = s->emmc; 463 break; 464 465 case R_PHYC: 466 r = s->phyc; 467 break; 468 469 case R_MCR: 470 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ 471 break; 472 473 case R_STATS_RX_BYTESL: 474 case R_STATS_RX_BYTESH: 475 r = s->stats.rx_bytes >> (32 * (addr & 1)); 476 break; 477 478 case R_STATS_TX_BYTESL: 479 case R_STATS_TX_BYTESH: 480 r = s->stats.tx_bytes >> (32 * (addr & 1)); 481 break; 482 483 case R_STATS_RXL: 484 case R_STATS_RXH: 485 r = s->stats.rx >> (32 * (addr & 1)); 486 break; 487 case R_STATS_RX_BCASTL: 488 case R_STATS_RX_BCASTH: 489 r = s->stats.rx_bcast >> (32 * (addr & 1)); 490 break; 491 case R_STATS_RX_MCASTL: 492 case R_STATS_RX_MCASTH: 493 r = s->stats.rx_mcast >> (32 * (addr & 1)); 494 break; 495 496 case R_MC: 497 case R_MWD: 498 case R_MRD: 499 r = s->mii.regs[addr & 3]; 500 break; 501 502 case R_UAW0: 503 case R_UAW1: 504 r = s->uaw[addr & 1]; 505 break; 506 507 case R_UAWU: 508 case R_UAWL: 509 r = s->ext_uaw[addr & 1]; 510 break; 511 512 case R_FMI: 513 r = s->fmi; 514 break; 515 516 case R_AF0: 517 case R_AF1: 518 r = s->maddr[s->fmi & 3][addr & 1]; 519 break; 520 521 case 0x8000 ... 0x83ff: 522 r = s->ext_mtable[addr - 0x8000]; 523 break; 524 525 default: 526 if (addr < ARRAY_SIZE(s->regs)) { 527 r = s->regs[addr]; 528 } 529 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 530 __func__, addr * 4, r)); 531 break; 532 } 533 return r; 534 } 535 536 static void enet_write(void *opaque, hwaddr addr, 537 uint64_t value, unsigned size) 538 { 539 XilinxAXIEnet *s = opaque; 540 struct TEMAC *t = &s->TEMAC; 541 542 addr >>= 2; 543 switch (addr) { 544 case R_RCW0: 545 case R_RCW1: 546 s->rcw[addr & 1] = value; 547 if ((addr & 1) && value & RCW1_RST) { 548 axienet_rx_reset(s); 549 } else { 550 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 551 } 552 break; 553 554 case R_TC: 555 s->tc = value; 556 if (value & TC_RST) { 557 axienet_tx_reset(s); 558 } 559 break; 560 561 case R_EMMC: 562 s->emmc = value; 563 break; 564 565 case R_PHYC: 566 s->phyc = value; 567 break; 568 569 case R_MC: 570 value &= ((1 << 7) - 1); 571 572 /* Enable the MII. */ 573 if (value & MC_EN) { 574 unsigned int miiclkdiv = value & ((1 << 6) - 1); 575 if (!miiclkdiv) { 576 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n"); 577 } 578 } 579 s->mii.mc = value; 580 break; 581 582 case R_MCR: { 583 unsigned int phyaddr = (value >> 24) & 0x1f; 584 unsigned int regaddr = (value >> 16) & 0x1f; 585 unsigned int op = (value >> 14) & 3; 586 unsigned int initiate = (value >> 11) & 1; 587 588 if (initiate) { 589 if (op == 1) { 590 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); 591 } else if (op == 2) { 592 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); 593 } else { 594 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op); 595 } 596 } 597 s->mii.mcr = value; 598 break; 599 } 600 601 case R_MWD: 602 case R_MRD: 603 s->mii.regs[addr & 3] = value; 604 break; 605 606 607 case R_UAW0: 608 case R_UAW1: 609 s->uaw[addr & 1] = value; 610 break; 611 612 case R_UAWL: 613 case R_UAWU: 614 s->ext_uaw[addr & 1] = value; 615 break; 616 617 case R_FMI: 618 s->fmi = value; 619 break; 620 621 case R_AF0: 622 case R_AF1: 623 s->maddr[s->fmi & 3][addr & 1] = value; 624 break; 625 626 case R_IS: 627 s->regs[addr] &= ~value; 628 break; 629 630 case 0x8000 ... 0x83ff: 631 s->ext_mtable[addr - 0x8000] = value; 632 break; 633 634 default: 635 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 636 __func__, addr * 4, (unsigned)value)); 637 if (addr < ARRAY_SIZE(s->regs)) { 638 s->regs[addr] = value; 639 } 640 break; 641 } 642 enet_update_irq(s); 643 } 644 645 static const MemoryRegionOps enet_ops = { 646 .read = enet_read, 647 .write = enet_write, 648 .endianness = DEVICE_LITTLE_ENDIAN, 649 }; 650 651 static int eth_can_rx(XilinxAXIEnet *s) 652 { 653 /* RX enabled? */ 654 return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s); 655 } 656 657 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) 658 { 659 int match = 1; 660 661 if (memcmp(buf, &f0, 4)) { 662 match = 0; 663 } 664 665 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { 666 match = 0; 667 } 668 669 return match; 670 } 671 672 static void axienet_eth_rx_notify(void *opaque) 673 { 674 XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); 675 676 while (s->rxappsize && stream_can_push(s->tx_control_dev, 677 axienet_eth_rx_notify, s)) { 678 size_t ret = stream_push(s->tx_control_dev, 679 (void *)s->rxapp + CONTROL_PAYLOAD_SIZE 680 - s->rxappsize, s->rxappsize, true); 681 s->rxappsize -= ret; 682 } 683 684 while (s->rxsize && stream_can_push(s->tx_data_dev, 685 axienet_eth_rx_notify, s)) { 686 size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, 687 s->rxsize, true); 688 s->rxsize -= ret; 689 s->rxpos += ret; 690 if (!s->rxsize) { 691 s->regs[R_IS] |= IS_RX_COMPLETE; 692 if (s->need_flush) { 693 s->need_flush = false; 694 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 695 } 696 } 697 } 698 enet_update_irq(s); 699 } 700 701 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 702 { 703 XilinxAXIEnet *s = qemu_get_nic_opaque(nc); 704 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 705 0xff, 0xff, 0xff}; 706 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; 707 uint32_t app[CONTROL_PAYLOAD_WORDS] = {0}; 708 int promisc = s->fmi & (1 << 31); 709 int unicast, broadcast, multicast, ip_multicast = 0; 710 uint32_t csum32; 711 uint16_t csum16; 712 int i; 713 714 DENET(qemu_log("%s: %zd bytes\n", __func__, size)); 715 716 if (!eth_can_rx(s)) { 717 s->need_flush = true; 718 return 0; 719 } 720 721 unicast = ~buf[0] & 0x1; 722 broadcast = memcmp(buf, sa_bcast, 6) == 0; 723 multicast = !unicast && !broadcast; 724 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { 725 ip_multicast = 1; 726 } 727 728 /* Jumbo or vlan sizes ? */ 729 if (!(s->rcw[1] & RCW1_JUM)) { 730 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { 731 return size; 732 } 733 } 734 735 /* Basic Address filters. If you want to use the extended filters 736 you'll generally have to place the ethernet mac into promiscuous mode 737 to avoid the basic filtering from dropping most frames. */ 738 if (!promisc) { 739 if (unicast) { 740 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { 741 return size; 742 } 743 } else { 744 if (broadcast) { 745 /* Broadcast. */ 746 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 747 return size; 748 } 749 } else { 750 int drop = 1; 751 752 /* Multicast. */ 753 if (s->regs[R_RAF] & RAF_MCAST_REJ) { 754 return size; 755 } 756 757 for (i = 0; i < 4; i++) { 758 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { 759 drop = 0; 760 break; 761 } 762 } 763 764 if (drop) { 765 return size; 766 } 767 } 768 } 769 } 770 771 /* Extended mcast filtering enabled? */ 772 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) { 773 if (unicast) { 774 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { 775 return size; 776 } 777 } else { 778 if (broadcast) { 779 /* Broadcast. ??? */ 780 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 781 return size; 782 } 783 } else { 784 int idx, bit; 785 786 /* Multicast. */ 787 if (!memcmp(buf, sa_ipmcast, 3)) { 788 return size; 789 } 790 791 idx = (buf[4] & 0x7f) << 8; 792 idx |= buf[5]; 793 794 bit = 1 << (idx & 0x1f); 795 idx >>= 5; 796 797 if (!(s->ext_mtable[idx] & bit)) { 798 return size; 799 } 800 } 801 } 802 } 803 804 if (size < 12) { 805 s->regs[R_IS] |= IS_RX_REJECT; 806 enet_update_irq(s); 807 return -1; 808 } 809 810 if (size > (s->c_rxmem - 4)) { 811 size = s->c_rxmem - 4; 812 } 813 814 memcpy(s->rxmem, buf, size); 815 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ 816 817 if (s->rcw[1] & RCW1_FCS) { 818 size += 4; /* fcs is inband. */ 819 } 820 821 app[0] = 5 << 28; 822 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); 823 /* Fold it once. */ 824 csum32 = (csum32 & 0xffff) + (csum32 >> 16); 825 /* And twice to get rid of possible carries. */ 826 csum16 = (csum32 & 0xffff) + (csum32 >> 16); 827 app[3] = csum16; 828 app[4] = size & 0xffff; 829 830 s->stats.rx_bytes += size; 831 s->stats.rx++; 832 if (multicast) { 833 s->stats.rx_mcast++; 834 app[2] |= 1 | (ip_multicast << 1); 835 } else if (broadcast) { 836 s->stats.rx_bcast++; 837 app[2] |= 1 << 3; 838 } 839 840 /* Good frame. */ 841 app[2] |= 1 << 6; 842 843 s->rxsize = size; 844 s->rxpos = 0; 845 for (i = 0; i < ARRAY_SIZE(app); ++i) { 846 app[i] = cpu_to_le32(app[i]); 847 } 848 s->rxappsize = CONTROL_PAYLOAD_SIZE; 849 memcpy(s->rxapp, app, s->rxappsize); 850 axienet_eth_rx_notify(s); 851 852 enet_update_irq(s); 853 return size; 854 } 855 856 static size_t 857 xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len, 858 bool eop) 859 { 860 int i; 861 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); 862 XilinxAXIEnet *s = cs->enet; 863 864 assert(eop); 865 if (len != CONTROL_PAYLOAD_SIZE) { 866 hw_error("AXI Enet requires %d byte control stream payload\n", 867 (int)CONTROL_PAYLOAD_SIZE); 868 } 869 870 memcpy(s->hdr, buf, len); 871 872 for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { 873 s->hdr[i] = le32_to_cpu(s->hdr[i]); 874 } 875 return len; 876 } 877 878 static size_t 879 xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, 880 bool eop) 881 { 882 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); 883 XilinxAXIEnet *s = ds->enet; 884 885 /* TX enable ? */ 886 if (!(s->tc & TC_TX)) { 887 return size; 888 } 889 890 if (s->txpos + size > s->c_txmem) { 891 qemu_log_mask(LOG_GUEST_ERROR, "%s: Packet larger than txmem\n", 892 TYPE_XILINX_AXI_ENET); 893 s->txpos = 0; 894 return size; 895 } 896 897 if (s->txpos == 0 && eop) { 898 /* Fast path single fragment. */ 899 s->txpos = size; 900 } else { 901 memcpy(s->txmem + s->txpos, buf, size); 902 buf = s->txmem; 903 s->txpos += size; 904 905 if (!eop) { 906 return size; 907 } 908 } 909 910 /* Jumbo or vlan sizes ? */ 911 if (!(s->tc & TC_JUM)) { 912 if (s->txpos > 1518 && s->txpos <= 1522 && !(s->tc & TC_VLAN)) { 913 s->txpos = 0; 914 return size; 915 } 916 } 917 918 if (s->hdr[0] & 1) { 919 unsigned int start_off = s->hdr[1] >> 16; 920 unsigned int write_off = s->hdr[1] & 0xffff; 921 uint32_t tmp_csum; 922 uint16_t csum; 923 924 tmp_csum = net_checksum_add(s->txpos - start_off, 925 buf + start_off); 926 /* Accumulate the seed. */ 927 tmp_csum += s->hdr[2] & 0xffff; 928 929 /* Fold the 32bit partial checksum. */ 930 csum = net_checksum_finish(tmp_csum); 931 932 /* Writeback. */ 933 buf[write_off] = csum >> 8; 934 buf[write_off + 1] = csum & 0xff; 935 } 936 937 qemu_send_packet(qemu_get_queue(s->nic), buf, s->txpos); 938 939 s->stats.tx_bytes += s->txpos; 940 s->regs[R_IS] |= IS_TX_COMPLETE; 941 enet_update_irq(s); 942 943 s->txpos = 0; 944 return size; 945 } 946 947 static NetClientInfo net_xilinx_enet_info = { 948 .type = NET_CLIENT_DRIVER_NIC, 949 .size = sizeof(NICState), 950 .receive = eth_rx, 951 }; 952 953 static void xilinx_enet_realize(DeviceState *dev, Error **errp) 954 { 955 XilinxAXIEnet *s = XILINX_AXI_ENET(dev); 956 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); 957 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM( 958 &s->rx_control_dev); 959 960 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", 961 (Object **) &ds->enet, 962 object_property_allow_set_link, 963 OBJ_PROP_LINK_STRONG); 964 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", 965 (Object **) &cs->enet, 966 object_property_allow_set_link, 967 OBJ_PROP_LINK_STRONG); 968 object_property_set_link(OBJECT(ds), "enet", OBJECT(s), &error_abort); 969 object_property_set_link(OBJECT(cs), "enet", OBJECT(s), &error_abort); 970 971 qemu_macaddr_default_if_unset(&s->conf.macaddr); 972 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, 973 object_get_typename(OBJECT(dev)), dev->id, s); 974 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 975 976 tdk_init(&s->TEMAC.phy); 977 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); 978 979 s->TEMAC.parent = s; 980 981 s->rxmem = g_malloc(s->c_rxmem); 982 s->txmem = g_malloc(s->c_txmem); 983 } 984 985 static void xilinx_enet_init(Object *obj) 986 { 987 XilinxAXIEnet *s = XILINX_AXI_ENET(obj); 988 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 989 990 object_initialize_child(OBJECT(s), "axistream-connected-target", 991 &s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM); 992 object_initialize_child(OBJECT(s), "axistream-control-connected-target", 993 &s->rx_control_dev, 994 TYPE_XILINX_AXI_ENET_CONTROL_STREAM); 995 sysbus_init_irq(sbd, &s->irq); 996 997 memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); 998 sysbus_init_mmio(sbd, &s->iomem); 999 } 1000 1001 static Property xilinx_enet_properties[] = { 1002 DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), 1003 DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), 1004 DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), 1005 DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), 1006 DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, 1007 tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), 1008 DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, 1009 tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), 1010 DEFINE_PROP_END_OF_LIST(), 1011 }; 1012 1013 static void xilinx_enet_class_init(ObjectClass *klass, void *data) 1014 { 1015 DeviceClass *dc = DEVICE_CLASS(klass); 1016 1017 dc->realize = xilinx_enet_realize; 1018 device_class_set_props(dc, xilinx_enet_properties); 1019 dc->reset = xilinx_axienet_reset; 1020 } 1021 1022 static void xilinx_enet_control_stream_class_init(ObjectClass *klass, 1023 void *data) 1024 { 1025 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); 1026 1027 ssc->push = xilinx_axienet_control_stream_push; 1028 } 1029 1030 static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data) 1031 { 1032 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); 1033 1034 ssc->push = xilinx_axienet_data_stream_push; 1035 } 1036 1037 static const TypeInfo xilinx_enet_info = { 1038 .name = TYPE_XILINX_AXI_ENET, 1039 .parent = TYPE_SYS_BUS_DEVICE, 1040 .instance_size = sizeof(XilinxAXIEnet), 1041 .class_init = xilinx_enet_class_init, 1042 .instance_init = xilinx_enet_init, 1043 }; 1044 1045 static const TypeInfo xilinx_enet_data_stream_info = { 1046 .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, 1047 .parent = TYPE_OBJECT, 1048 .instance_size = sizeof(XilinxAXIEnetStreamSlave), 1049 .class_init = xilinx_enet_data_stream_class_init, 1050 .interfaces = (InterfaceInfo[]) { 1051 { TYPE_STREAM_SLAVE }, 1052 { } 1053 } 1054 }; 1055 1056 static const TypeInfo xilinx_enet_control_stream_info = { 1057 .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, 1058 .parent = TYPE_OBJECT, 1059 .instance_size = sizeof(XilinxAXIEnetStreamSlave), 1060 .class_init = xilinx_enet_control_stream_class_init, 1061 .interfaces = (InterfaceInfo[]) { 1062 { TYPE_STREAM_SLAVE }, 1063 { } 1064 } 1065 }; 1066 1067 static void xilinx_enet_register_types(void) 1068 { 1069 type_register_static(&xilinx_enet_info); 1070 type_register_static(&xilinx_enet_data_stream_info); 1071 type_register_static(&xilinx_enet_control_stream_info); 1072 } 1073 1074 type_init(xilinx_enet_register_types) 1075