1 /* 2 * QEMU model of Xilinx AXI-Ethernet. 3 * 4 * Copyright (c) 2011 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "qapi/error.h" 28 #include "qemu/log.h" 29 #include "qemu/module.h" 30 #include "net/net.h" 31 #include "net/checksum.h" 32 33 #include "hw/irq.h" 34 #include "hw/stream.h" 35 36 #define DPHY(x) 37 38 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" 39 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream" 40 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream" 41 42 #define XILINX_AXI_ENET(obj) \ 43 OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET) 44 45 #define XILINX_AXI_ENET_DATA_STREAM(obj) \ 46 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ 47 TYPE_XILINX_AXI_ENET_DATA_STREAM) 48 49 #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \ 50 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ 51 TYPE_XILINX_AXI_ENET_CONTROL_STREAM) 52 53 /* Advertisement control register. */ 54 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 55 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 56 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 57 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 58 59 #define CONTROL_PAYLOAD_WORDS 5 60 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) 61 62 struct PHY { 63 uint32_t regs[32]; 64 65 int link; 66 67 unsigned int (*read)(struct PHY *phy, unsigned int req); 68 void (*write)(struct PHY *phy, unsigned int req, 69 unsigned int data); 70 }; 71 72 static unsigned int tdk_read(struct PHY *phy, unsigned int req) 73 { 74 int regnum; 75 unsigned r = 0; 76 77 regnum = req & 0x1f; 78 79 switch (regnum) { 80 case 1: 81 if (!phy->link) { 82 break; 83 } 84 /* MR1. */ 85 /* Speeds and modes. */ 86 r |= (1 << 13) | (1 << 14); 87 r |= (1 << 11) | (1 << 12); 88 r |= (1 << 5); /* Autoneg complete. */ 89 r |= (1 << 3); /* Autoneg able. */ 90 r |= (1 << 2); /* link. */ 91 r |= (1 << 1); /* link. */ 92 break; 93 case 5: 94 /* Link partner ability. 95 We are kind; always agree with whatever best mode 96 the guest advertises. */ 97 r = 1 << 14; /* Success. */ 98 /* Copy advertised modes. */ 99 r |= phy->regs[4] & (15 << 5); 100 /* Autoneg support. */ 101 r |= 1; 102 break; 103 case 17: 104 /* Marvell PHY on many xilinx boards. */ 105 r = 0x8000; /* 1000Mb */ 106 break; 107 case 18: 108 { 109 /* Diagnostics reg. */ 110 int duplex = 0; 111 int speed_100 = 0; 112 113 if (!phy->link) { 114 break; 115 } 116 117 /* Are we advertising 100 half or 100 duplex ? */ 118 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); 119 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); 120 121 /* Are we advertising 10 duplex or 100 duplex ? */ 122 duplex = !!(phy->regs[4] & ADVERTISE_100FULL); 123 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); 124 r = (speed_100 << 10) | (duplex << 11); 125 } 126 break; 127 128 default: 129 r = phy->regs[regnum]; 130 break; 131 } 132 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum)); 133 return r; 134 } 135 136 static void 137 tdk_write(struct PHY *phy, unsigned int req, unsigned int data) 138 { 139 int regnum; 140 141 regnum = req & 0x1f; 142 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data)); 143 switch (regnum) { 144 default: 145 phy->regs[regnum] = data; 146 break; 147 } 148 149 /* Unconditionally clear regs[BMCR][BMCR_RESET] */ 150 phy->regs[0] &= ~0x8000; 151 } 152 153 static void 154 tdk_init(struct PHY *phy) 155 { 156 phy->regs[0] = 0x3100; 157 /* PHY Id. */ 158 phy->regs[2] = 0x0300; 159 phy->regs[3] = 0xe400; 160 /* Autonegotiation advertisement reg. */ 161 phy->regs[4] = 0x01E1; 162 phy->link = 1; 163 164 phy->read = tdk_read; 165 phy->write = tdk_write; 166 } 167 168 struct MDIOBus { 169 /* bus. */ 170 int mdc; 171 int mdio; 172 173 /* decoder. */ 174 enum { 175 PREAMBLE, 176 SOF, 177 OPC, 178 ADDR, 179 REQ, 180 TURNAROUND, 181 DATA 182 } state; 183 unsigned int drive; 184 185 unsigned int cnt; 186 unsigned int addr; 187 unsigned int opc; 188 unsigned int req; 189 unsigned int data; 190 191 struct PHY *devs[32]; 192 }; 193 194 static void 195 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 196 { 197 bus->devs[addr & 0x1f] = phy; 198 } 199 200 #ifdef USE_THIS_DEAD_CODE 201 static void 202 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 203 { 204 bus->devs[addr & 0x1f] = NULL; 205 } 206 #endif 207 208 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, 209 unsigned int reg) 210 { 211 struct PHY *phy; 212 uint16_t data; 213 214 phy = bus->devs[addr]; 215 if (phy && phy->read) { 216 data = phy->read(phy, reg); 217 } else { 218 data = 0xffff; 219 } 220 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 221 return data; 222 } 223 224 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, 225 unsigned int reg, uint16_t data) 226 { 227 struct PHY *phy; 228 229 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 230 phy = bus->devs[addr]; 231 if (phy && phy->write) { 232 phy->write(phy, reg, data); 233 } 234 } 235 236 #define DENET(x) 237 238 #define R_RAF (0x000 / 4) 239 enum { 240 RAF_MCAST_REJ = (1 << 1), 241 RAF_BCAST_REJ = (1 << 2), 242 RAF_EMCF_EN = (1 << 12), 243 RAF_NEWFUNC_EN = (1 << 11) 244 }; 245 246 #define R_IS (0x00C / 4) 247 enum { 248 IS_HARD_ACCESS_COMPLETE = 1, 249 IS_AUTONEG = (1 << 1), 250 IS_RX_COMPLETE = (1 << 2), 251 IS_RX_REJECT = (1 << 3), 252 IS_TX_COMPLETE = (1 << 5), 253 IS_RX_DCM_LOCK = (1 << 6), 254 IS_MGM_RDY = (1 << 7), 255 IS_PHY_RST_DONE = (1 << 8), 256 }; 257 258 #define R_IP (0x010 / 4) 259 #define R_IE (0x014 / 4) 260 #define R_UAWL (0x020 / 4) 261 #define R_UAWU (0x024 / 4) 262 #define R_PPST (0x030 / 4) 263 enum { 264 PPST_LINKSTATUS = (1 << 0), 265 PPST_PHY_LINKSTATUS = (1 << 7), 266 }; 267 268 #define R_STATS_RX_BYTESL (0x200 / 4) 269 #define R_STATS_RX_BYTESH (0x204 / 4) 270 #define R_STATS_TX_BYTESL (0x208 / 4) 271 #define R_STATS_TX_BYTESH (0x20C / 4) 272 #define R_STATS_RXL (0x290 / 4) 273 #define R_STATS_RXH (0x294 / 4) 274 #define R_STATS_RX_BCASTL (0x2a0 / 4) 275 #define R_STATS_RX_BCASTH (0x2a4 / 4) 276 #define R_STATS_RX_MCASTL (0x2a8 / 4) 277 #define R_STATS_RX_MCASTH (0x2ac / 4) 278 279 #define R_RCW0 (0x400 / 4) 280 #define R_RCW1 (0x404 / 4) 281 enum { 282 RCW1_VLAN = (1 << 27), 283 RCW1_RX = (1 << 28), 284 RCW1_FCS = (1 << 29), 285 RCW1_JUM = (1 << 30), 286 RCW1_RST = (1 << 31), 287 }; 288 289 #define R_TC (0x408 / 4) 290 enum { 291 TC_VLAN = (1 << 27), 292 TC_TX = (1 << 28), 293 TC_FCS = (1 << 29), 294 TC_JUM = (1 << 30), 295 TC_RST = (1 << 31), 296 }; 297 298 #define R_EMMC (0x410 / 4) 299 enum { 300 EMMC_LINKSPEED_10MB = (0 << 30), 301 EMMC_LINKSPEED_100MB = (1 << 30), 302 EMMC_LINKSPEED_1000MB = (2 << 30), 303 }; 304 305 #define R_PHYC (0x414 / 4) 306 307 #define R_MC (0x500 / 4) 308 #define MC_EN (1 << 6) 309 310 #define R_MCR (0x504 / 4) 311 #define R_MWD (0x508 / 4) 312 #define R_MRD (0x50c / 4) 313 #define R_MIS (0x600 / 4) 314 #define R_MIP (0x620 / 4) 315 #define R_MIE (0x640 / 4) 316 #define R_MIC (0x640 / 4) 317 318 #define R_UAW0 (0x700 / 4) 319 #define R_UAW1 (0x704 / 4) 320 #define R_FMI (0x708 / 4) 321 #define R_AF0 (0x710 / 4) 322 #define R_AF1 (0x714 / 4) 323 #define R_MAX (0x34 / 4) 324 325 /* Indirect registers. */ 326 struct TEMAC { 327 struct MDIOBus mdio_bus; 328 struct PHY phy; 329 330 void *parent; 331 }; 332 333 typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave; 334 typedef struct XilinxAXIEnet XilinxAXIEnet; 335 336 struct XilinxAXIEnetStreamSlave { 337 Object parent; 338 339 struct XilinxAXIEnet *enet; 340 } ; 341 342 struct XilinxAXIEnet { 343 SysBusDevice busdev; 344 MemoryRegion iomem; 345 qemu_irq irq; 346 StreamSlave *tx_data_dev; 347 StreamSlave *tx_control_dev; 348 XilinxAXIEnetStreamSlave rx_data_dev; 349 XilinxAXIEnetStreamSlave rx_control_dev; 350 NICState *nic; 351 NICConf conf; 352 353 354 uint32_t c_rxmem; 355 uint32_t c_txmem; 356 uint32_t c_phyaddr; 357 358 struct TEMAC TEMAC; 359 360 /* MII regs. */ 361 union { 362 uint32_t regs[4]; 363 struct { 364 uint32_t mc; 365 uint32_t mcr; 366 uint32_t mwd; 367 uint32_t mrd; 368 }; 369 } mii; 370 371 struct { 372 uint64_t rx_bytes; 373 uint64_t tx_bytes; 374 375 uint64_t rx; 376 uint64_t rx_bcast; 377 uint64_t rx_mcast; 378 } stats; 379 380 /* Receive configuration words. */ 381 uint32_t rcw[2]; 382 /* Transmit config. */ 383 uint32_t tc; 384 uint32_t emmc; 385 uint32_t phyc; 386 387 /* Unicast Address Word. */ 388 uint32_t uaw[2]; 389 /* Unicast address filter used with extended mcast. */ 390 uint32_t ext_uaw[2]; 391 uint32_t fmi; 392 393 uint32_t regs[R_MAX]; 394 395 /* Multicast filter addrs. */ 396 uint32_t maddr[4][2]; 397 /* 32K x 1 lookup filter. */ 398 uint32_t ext_mtable[1024]; 399 400 uint32_t hdr[CONTROL_PAYLOAD_WORDS]; 401 402 uint8_t *rxmem; 403 uint32_t rxsize; 404 uint32_t rxpos; 405 406 uint8_t rxapp[CONTROL_PAYLOAD_SIZE]; 407 uint32_t rxappsize; 408 409 /* Whether axienet_eth_rx_notify should flush incoming queue. */ 410 bool need_flush; 411 }; 412 413 static void axienet_rx_reset(XilinxAXIEnet *s) 414 { 415 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; 416 } 417 418 static void axienet_tx_reset(XilinxAXIEnet *s) 419 { 420 s->tc = TC_JUM | TC_TX | TC_VLAN; 421 } 422 423 static inline int axienet_rx_resetting(XilinxAXIEnet *s) 424 { 425 return s->rcw[1] & RCW1_RST; 426 } 427 428 static inline int axienet_rx_enabled(XilinxAXIEnet *s) 429 { 430 return s->rcw[1] & RCW1_RX; 431 } 432 433 static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) 434 { 435 return !!(s->regs[R_RAF] & RAF_EMCF_EN); 436 } 437 438 static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) 439 { 440 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); 441 } 442 443 static void xilinx_axienet_reset(DeviceState *d) 444 { 445 XilinxAXIEnet *s = XILINX_AXI_ENET(d); 446 447 axienet_rx_reset(s); 448 axienet_tx_reset(s); 449 450 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; 451 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; 452 453 s->emmc = EMMC_LINKSPEED_100MB; 454 } 455 456 static void enet_update_irq(XilinxAXIEnet *s) 457 { 458 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; 459 qemu_set_irq(s->irq, !!s->regs[R_IP]); 460 } 461 462 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) 463 { 464 XilinxAXIEnet *s = opaque; 465 uint32_t r = 0; 466 addr >>= 2; 467 468 switch (addr) { 469 case R_RCW0: 470 case R_RCW1: 471 r = s->rcw[addr & 1]; 472 break; 473 474 case R_TC: 475 r = s->tc; 476 break; 477 478 case R_EMMC: 479 r = s->emmc; 480 break; 481 482 case R_PHYC: 483 r = s->phyc; 484 break; 485 486 case R_MCR: 487 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ 488 break; 489 490 case R_STATS_RX_BYTESL: 491 case R_STATS_RX_BYTESH: 492 r = s->stats.rx_bytes >> (32 * (addr & 1)); 493 break; 494 495 case R_STATS_TX_BYTESL: 496 case R_STATS_TX_BYTESH: 497 r = s->stats.tx_bytes >> (32 * (addr & 1)); 498 break; 499 500 case R_STATS_RXL: 501 case R_STATS_RXH: 502 r = s->stats.rx >> (32 * (addr & 1)); 503 break; 504 case R_STATS_RX_BCASTL: 505 case R_STATS_RX_BCASTH: 506 r = s->stats.rx_bcast >> (32 * (addr & 1)); 507 break; 508 case R_STATS_RX_MCASTL: 509 case R_STATS_RX_MCASTH: 510 r = s->stats.rx_mcast >> (32 * (addr & 1)); 511 break; 512 513 case R_MC: 514 case R_MWD: 515 case R_MRD: 516 r = s->mii.regs[addr & 3]; 517 break; 518 519 case R_UAW0: 520 case R_UAW1: 521 r = s->uaw[addr & 1]; 522 break; 523 524 case R_UAWU: 525 case R_UAWL: 526 r = s->ext_uaw[addr & 1]; 527 break; 528 529 case R_FMI: 530 r = s->fmi; 531 break; 532 533 case R_AF0: 534 case R_AF1: 535 r = s->maddr[s->fmi & 3][addr & 1]; 536 break; 537 538 case 0x8000 ... 0x83ff: 539 r = s->ext_mtable[addr - 0x8000]; 540 break; 541 542 default: 543 if (addr < ARRAY_SIZE(s->regs)) { 544 r = s->regs[addr]; 545 } 546 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 547 __func__, addr * 4, r)); 548 break; 549 } 550 return r; 551 } 552 553 static void enet_write(void *opaque, hwaddr addr, 554 uint64_t value, unsigned size) 555 { 556 XilinxAXIEnet *s = opaque; 557 struct TEMAC *t = &s->TEMAC; 558 559 addr >>= 2; 560 switch (addr) { 561 case R_RCW0: 562 case R_RCW1: 563 s->rcw[addr & 1] = value; 564 if ((addr & 1) && value & RCW1_RST) { 565 axienet_rx_reset(s); 566 } else { 567 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 568 } 569 break; 570 571 case R_TC: 572 s->tc = value; 573 if (value & TC_RST) { 574 axienet_tx_reset(s); 575 } 576 break; 577 578 case R_EMMC: 579 s->emmc = value; 580 break; 581 582 case R_PHYC: 583 s->phyc = value; 584 break; 585 586 case R_MC: 587 value &= ((1 << 7) - 1); 588 589 /* Enable the MII. */ 590 if (value & MC_EN) { 591 unsigned int miiclkdiv = value & ((1 << 6) - 1); 592 if (!miiclkdiv) { 593 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n"); 594 } 595 } 596 s->mii.mc = value; 597 break; 598 599 case R_MCR: { 600 unsigned int phyaddr = (value >> 24) & 0x1f; 601 unsigned int regaddr = (value >> 16) & 0x1f; 602 unsigned int op = (value >> 14) & 3; 603 unsigned int initiate = (value >> 11) & 1; 604 605 if (initiate) { 606 if (op == 1) { 607 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); 608 } else if (op == 2) { 609 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); 610 } else { 611 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op); 612 } 613 } 614 s->mii.mcr = value; 615 break; 616 } 617 618 case R_MWD: 619 case R_MRD: 620 s->mii.regs[addr & 3] = value; 621 break; 622 623 624 case R_UAW0: 625 case R_UAW1: 626 s->uaw[addr & 1] = value; 627 break; 628 629 case R_UAWL: 630 case R_UAWU: 631 s->ext_uaw[addr & 1] = value; 632 break; 633 634 case R_FMI: 635 s->fmi = value; 636 break; 637 638 case R_AF0: 639 case R_AF1: 640 s->maddr[s->fmi & 3][addr & 1] = value; 641 break; 642 643 case R_IS: 644 s->regs[addr] &= ~value; 645 break; 646 647 case 0x8000 ... 0x83ff: 648 s->ext_mtable[addr - 0x8000] = value; 649 break; 650 651 default: 652 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 653 __func__, addr * 4, (unsigned)value)); 654 if (addr < ARRAY_SIZE(s->regs)) { 655 s->regs[addr] = value; 656 } 657 break; 658 } 659 enet_update_irq(s); 660 } 661 662 static const MemoryRegionOps enet_ops = { 663 .read = enet_read, 664 .write = enet_write, 665 .endianness = DEVICE_LITTLE_ENDIAN, 666 }; 667 668 static int eth_can_rx(XilinxAXIEnet *s) 669 { 670 /* RX enabled? */ 671 return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s); 672 } 673 674 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) 675 { 676 int match = 1; 677 678 if (memcmp(buf, &f0, 4)) { 679 match = 0; 680 } 681 682 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { 683 match = 0; 684 } 685 686 return match; 687 } 688 689 static void axienet_eth_rx_notify(void *opaque) 690 { 691 XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); 692 693 while (s->rxappsize && stream_can_push(s->tx_control_dev, 694 axienet_eth_rx_notify, s)) { 695 size_t ret = stream_push(s->tx_control_dev, 696 (void *)s->rxapp + CONTROL_PAYLOAD_SIZE 697 - s->rxappsize, s->rxappsize); 698 s->rxappsize -= ret; 699 } 700 701 while (s->rxsize && stream_can_push(s->tx_data_dev, 702 axienet_eth_rx_notify, s)) { 703 size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, 704 s->rxsize); 705 s->rxsize -= ret; 706 s->rxpos += ret; 707 if (!s->rxsize) { 708 s->regs[R_IS] |= IS_RX_COMPLETE; 709 if (s->need_flush) { 710 s->need_flush = false; 711 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 712 } 713 } 714 } 715 enet_update_irq(s); 716 } 717 718 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 719 { 720 XilinxAXIEnet *s = qemu_get_nic_opaque(nc); 721 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 722 0xff, 0xff, 0xff}; 723 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; 724 uint32_t app[CONTROL_PAYLOAD_WORDS] = {0}; 725 int promisc = s->fmi & (1 << 31); 726 int unicast, broadcast, multicast, ip_multicast = 0; 727 uint32_t csum32; 728 uint16_t csum16; 729 int i; 730 731 DENET(qemu_log("%s: %zd bytes\n", __func__, size)); 732 733 if (!eth_can_rx(s)) { 734 s->need_flush = true; 735 return 0; 736 } 737 738 unicast = ~buf[0] & 0x1; 739 broadcast = memcmp(buf, sa_bcast, 6) == 0; 740 multicast = !unicast && !broadcast; 741 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { 742 ip_multicast = 1; 743 } 744 745 /* Jumbo or vlan sizes ? */ 746 if (!(s->rcw[1] & RCW1_JUM)) { 747 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { 748 return size; 749 } 750 } 751 752 /* Basic Address filters. If you want to use the extended filters 753 you'll generally have to place the ethernet mac into promiscuous mode 754 to avoid the basic filtering from dropping most frames. */ 755 if (!promisc) { 756 if (unicast) { 757 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { 758 return size; 759 } 760 } else { 761 if (broadcast) { 762 /* Broadcast. */ 763 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 764 return size; 765 } 766 } else { 767 int drop = 1; 768 769 /* Multicast. */ 770 if (s->regs[R_RAF] & RAF_MCAST_REJ) { 771 return size; 772 } 773 774 for (i = 0; i < 4; i++) { 775 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { 776 drop = 0; 777 break; 778 } 779 } 780 781 if (drop) { 782 return size; 783 } 784 } 785 } 786 } 787 788 /* Extended mcast filtering enabled? */ 789 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) { 790 if (unicast) { 791 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { 792 return size; 793 } 794 } else { 795 if (broadcast) { 796 /* Broadcast. ??? */ 797 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 798 return size; 799 } 800 } else { 801 int idx, bit; 802 803 /* Multicast. */ 804 if (!memcmp(buf, sa_ipmcast, 3)) { 805 return size; 806 } 807 808 idx = (buf[4] & 0x7f) << 8; 809 idx |= buf[5]; 810 811 bit = 1 << (idx & 0x1f); 812 idx >>= 5; 813 814 if (!(s->ext_mtable[idx] & bit)) { 815 return size; 816 } 817 } 818 } 819 } 820 821 if (size < 12) { 822 s->regs[R_IS] |= IS_RX_REJECT; 823 enet_update_irq(s); 824 return -1; 825 } 826 827 if (size > (s->c_rxmem - 4)) { 828 size = s->c_rxmem - 4; 829 } 830 831 memcpy(s->rxmem, buf, size); 832 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ 833 834 if (s->rcw[1] & RCW1_FCS) { 835 size += 4; /* fcs is inband. */ 836 } 837 838 app[0] = 5 << 28; 839 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); 840 /* Fold it once. */ 841 csum32 = (csum32 & 0xffff) + (csum32 >> 16); 842 /* And twice to get rid of possible carries. */ 843 csum16 = (csum32 & 0xffff) + (csum32 >> 16); 844 app[3] = csum16; 845 app[4] = size & 0xffff; 846 847 s->stats.rx_bytes += size; 848 s->stats.rx++; 849 if (multicast) { 850 s->stats.rx_mcast++; 851 app[2] |= 1 | (ip_multicast << 1); 852 } else if (broadcast) { 853 s->stats.rx_bcast++; 854 app[2] |= 1 << 3; 855 } 856 857 /* Good frame. */ 858 app[2] |= 1 << 6; 859 860 s->rxsize = size; 861 s->rxpos = 0; 862 for (i = 0; i < ARRAY_SIZE(app); ++i) { 863 app[i] = cpu_to_le32(app[i]); 864 } 865 s->rxappsize = CONTROL_PAYLOAD_SIZE; 866 memcpy(s->rxapp, app, s->rxappsize); 867 axienet_eth_rx_notify(s); 868 869 enet_update_irq(s); 870 return size; 871 } 872 873 static size_t 874 xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len) 875 { 876 int i; 877 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); 878 XilinxAXIEnet *s = cs->enet; 879 880 if (len != CONTROL_PAYLOAD_SIZE) { 881 hw_error("AXI Enet requires %d byte control stream payload\n", 882 (int)CONTROL_PAYLOAD_SIZE); 883 } 884 885 memcpy(s->hdr, buf, len); 886 887 for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { 888 s->hdr[i] = le32_to_cpu(s->hdr[i]); 889 } 890 return len; 891 } 892 893 static size_t 894 xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size) 895 { 896 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); 897 XilinxAXIEnet *s = ds->enet; 898 899 /* TX enable ? */ 900 if (!(s->tc & TC_TX)) { 901 return size; 902 } 903 904 /* Jumbo or vlan sizes ? */ 905 if (!(s->tc & TC_JUM)) { 906 if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) { 907 return size; 908 } 909 } 910 911 if (s->hdr[0] & 1) { 912 unsigned int start_off = s->hdr[1] >> 16; 913 unsigned int write_off = s->hdr[1] & 0xffff; 914 uint32_t tmp_csum; 915 uint16_t csum; 916 917 tmp_csum = net_checksum_add(size - start_off, 918 (uint8_t *)buf + start_off); 919 /* Accumulate the seed. */ 920 tmp_csum += s->hdr[2] & 0xffff; 921 922 /* Fold the 32bit partial checksum. */ 923 csum = net_checksum_finish(tmp_csum); 924 925 /* Writeback. */ 926 buf[write_off] = csum >> 8; 927 buf[write_off + 1] = csum & 0xff; 928 } 929 930 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 931 932 s->stats.tx_bytes += size; 933 s->regs[R_IS] |= IS_TX_COMPLETE; 934 enet_update_irq(s); 935 936 return size; 937 } 938 939 static NetClientInfo net_xilinx_enet_info = { 940 .type = NET_CLIENT_DRIVER_NIC, 941 .size = sizeof(NICState), 942 .receive = eth_rx, 943 }; 944 945 static void xilinx_enet_realize(DeviceState *dev, Error **errp) 946 { 947 XilinxAXIEnet *s = XILINX_AXI_ENET(dev); 948 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); 949 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM( 950 &s->rx_control_dev); 951 Error *local_err = NULL; 952 953 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", 954 (Object **) &ds->enet, 955 object_property_allow_set_link, 956 OBJ_PROP_LINK_STRONG, 957 &local_err); 958 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", 959 (Object **) &cs->enet, 960 object_property_allow_set_link, 961 OBJ_PROP_LINK_STRONG, 962 &local_err); 963 if (local_err) { 964 goto xilinx_enet_realize_fail; 965 } 966 object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_err); 967 object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_err); 968 if (local_err) { 969 goto xilinx_enet_realize_fail; 970 } 971 972 qemu_macaddr_default_if_unset(&s->conf.macaddr); 973 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, 974 object_get_typename(OBJECT(dev)), dev->id, s); 975 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 976 977 tdk_init(&s->TEMAC.phy); 978 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); 979 980 s->TEMAC.parent = s; 981 982 s->rxmem = g_malloc(s->c_rxmem); 983 return; 984 985 xilinx_enet_realize_fail: 986 error_propagate(errp, local_err); 987 } 988 989 static void xilinx_enet_init(Object *obj) 990 { 991 XilinxAXIEnet *s = XILINX_AXI_ENET(obj); 992 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 993 994 object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), 995 TYPE_XILINX_AXI_ENET_DATA_STREAM); 996 object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), 997 TYPE_XILINX_AXI_ENET_CONTROL_STREAM); 998 object_property_add_child(OBJECT(s), "axistream-connected-target", 999 (Object *)&s->rx_data_dev, &error_abort); 1000 object_property_add_child(OBJECT(s), "axistream-control-connected-target", 1001 (Object *)&s->rx_control_dev, &error_abort); 1002 1003 sysbus_init_irq(sbd, &s->irq); 1004 1005 memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); 1006 sysbus_init_mmio(sbd, &s->iomem); 1007 } 1008 1009 static Property xilinx_enet_properties[] = { 1010 DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), 1011 DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), 1012 DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), 1013 DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), 1014 DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, 1015 tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), 1016 DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, 1017 tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), 1018 DEFINE_PROP_END_OF_LIST(), 1019 }; 1020 1021 static void xilinx_enet_class_init(ObjectClass *klass, void *data) 1022 { 1023 DeviceClass *dc = DEVICE_CLASS(klass); 1024 1025 dc->realize = xilinx_enet_realize; 1026 dc->props = xilinx_enet_properties; 1027 dc->reset = xilinx_axienet_reset; 1028 } 1029 1030 static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data) 1031 { 1032 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); 1033 1034 ssc->push = data; 1035 } 1036 1037 static const TypeInfo xilinx_enet_info = { 1038 .name = TYPE_XILINX_AXI_ENET, 1039 .parent = TYPE_SYS_BUS_DEVICE, 1040 .instance_size = sizeof(XilinxAXIEnet), 1041 .class_init = xilinx_enet_class_init, 1042 .instance_init = xilinx_enet_init, 1043 }; 1044 1045 static const TypeInfo xilinx_enet_data_stream_info = { 1046 .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, 1047 .parent = TYPE_OBJECT, 1048 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), 1049 .class_init = xilinx_enet_stream_class_init, 1050 .class_data = xilinx_axienet_data_stream_push, 1051 .interfaces = (InterfaceInfo[]) { 1052 { TYPE_STREAM_SLAVE }, 1053 { } 1054 } 1055 }; 1056 1057 static const TypeInfo xilinx_enet_control_stream_info = { 1058 .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, 1059 .parent = TYPE_OBJECT, 1060 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), 1061 .class_init = xilinx_enet_stream_class_init, 1062 .class_data = xilinx_axienet_control_stream_push, 1063 .interfaces = (InterfaceInfo[]) { 1064 { TYPE_STREAM_SLAVE }, 1065 { } 1066 } 1067 }; 1068 1069 static void xilinx_enet_register_types(void) 1070 { 1071 type_register_static(&xilinx_enet_info); 1072 type_register_static(&xilinx_enet_data_stream_info); 1073 type_register_static(&xilinx_enet_control_stream_info); 1074 } 1075 1076 type_init(xilinx_enet_register_types) 1077