1 /* 2 * QEMU model of Xilinx AXI-Ethernet. 3 * 4 * Copyright (c) 2011 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "qapi/error.h" 28 #include "qemu/log.h" 29 #include "qemu/module.h" 30 #include "net/net.h" 31 #include "net/checksum.h" 32 33 #include "hw/hw.h" 34 #include "hw/irq.h" 35 #include "hw/stream.h" 36 37 #define DPHY(x) 38 39 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" 40 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream" 41 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream" 42 43 #define XILINX_AXI_ENET(obj) \ 44 OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET) 45 46 #define XILINX_AXI_ENET_DATA_STREAM(obj) \ 47 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ 48 TYPE_XILINX_AXI_ENET_DATA_STREAM) 49 50 #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \ 51 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ 52 TYPE_XILINX_AXI_ENET_CONTROL_STREAM) 53 54 /* Advertisement control register. */ 55 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 56 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 57 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 58 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 59 60 #define CONTROL_PAYLOAD_WORDS 5 61 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) 62 63 struct PHY { 64 uint32_t regs[32]; 65 66 int link; 67 68 unsigned int (*read)(struct PHY *phy, unsigned int req); 69 void (*write)(struct PHY *phy, unsigned int req, 70 unsigned int data); 71 }; 72 73 static unsigned int tdk_read(struct PHY *phy, unsigned int req) 74 { 75 int regnum; 76 unsigned r = 0; 77 78 regnum = req & 0x1f; 79 80 switch (regnum) { 81 case 1: 82 if (!phy->link) { 83 break; 84 } 85 /* MR1. */ 86 /* Speeds and modes. */ 87 r |= (1 << 13) | (1 << 14); 88 r |= (1 << 11) | (1 << 12); 89 r |= (1 << 5); /* Autoneg complete. */ 90 r |= (1 << 3); /* Autoneg able. */ 91 r |= (1 << 2); /* link. */ 92 r |= (1 << 1); /* link. */ 93 break; 94 case 5: 95 /* Link partner ability. 96 We are kind; always agree with whatever best mode 97 the guest advertises. */ 98 r = 1 << 14; /* Success. */ 99 /* Copy advertised modes. */ 100 r |= phy->regs[4] & (15 << 5); 101 /* Autoneg support. */ 102 r |= 1; 103 break; 104 case 17: 105 /* Marvell PHY on many xilinx boards. */ 106 r = 0x8000; /* 1000Mb */ 107 break; 108 case 18: 109 { 110 /* Diagnostics reg. */ 111 int duplex = 0; 112 int speed_100 = 0; 113 114 if (!phy->link) { 115 break; 116 } 117 118 /* Are we advertising 100 half or 100 duplex ? */ 119 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); 120 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); 121 122 /* Are we advertising 10 duplex or 100 duplex ? */ 123 duplex = !!(phy->regs[4] & ADVERTISE_100FULL); 124 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); 125 r = (speed_100 << 10) | (duplex << 11); 126 } 127 break; 128 129 default: 130 r = phy->regs[regnum]; 131 break; 132 } 133 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum)); 134 return r; 135 } 136 137 static void 138 tdk_write(struct PHY *phy, unsigned int req, unsigned int data) 139 { 140 int regnum; 141 142 regnum = req & 0x1f; 143 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data)); 144 switch (regnum) { 145 default: 146 phy->regs[regnum] = data; 147 break; 148 } 149 150 /* Unconditionally clear regs[BMCR][BMCR_RESET] */ 151 phy->regs[0] &= ~0x8000; 152 } 153 154 static void 155 tdk_init(struct PHY *phy) 156 { 157 phy->regs[0] = 0x3100; 158 /* PHY Id. */ 159 phy->regs[2] = 0x0300; 160 phy->regs[3] = 0xe400; 161 /* Autonegotiation advertisement reg. */ 162 phy->regs[4] = 0x01E1; 163 phy->link = 1; 164 165 phy->read = tdk_read; 166 phy->write = tdk_write; 167 } 168 169 struct MDIOBus { 170 /* bus. */ 171 int mdc; 172 int mdio; 173 174 /* decoder. */ 175 enum { 176 PREAMBLE, 177 SOF, 178 OPC, 179 ADDR, 180 REQ, 181 TURNAROUND, 182 DATA 183 } state; 184 unsigned int drive; 185 186 unsigned int cnt; 187 unsigned int addr; 188 unsigned int opc; 189 unsigned int req; 190 unsigned int data; 191 192 struct PHY *devs[32]; 193 }; 194 195 static void 196 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 197 { 198 bus->devs[addr & 0x1f] = phy; 199 } 200 201 #ifdef USE_THIS_DEAD_CODE 202 static void 203 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 204 { 205 bus->devs[addr & 0x1f] = NULL; 206 } 207 #endif 208 209 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, 210 unsigned int reg) 211 { 212 struct PHY *phy; 213 uint16_t data; 214 215 phy = bus->devs[addr]; 216 if (phy && phy->read) { 217 data = phy->read(phy, reg); 218 } else { 219 data = 0xffff; 220 } 221 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 222 return data; 223 } 224 225 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, 226 unsigned int reg, uint16_t data) 227 { 228 struct PHY *phy; 229 230 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 231 phy = bus->devs[addr]; 232 if (phy && phy->write) { 233 phy->write(phy, reg, data); 234 } 235 } 236 237 #define DENET(x) 238 239 #define R_RAF (0x000 / 4) 240 enum { 241 RAF_MCAST_REJ = (1 << 1), 242 RAF_BCAST_REJ = (1 << 2), 243 RAF_EMCF_EN = (1 << 12), 244 RAF_NEWFUNC_EN = (1 << 11) 245 }; 246 247 #define R_IS (0x00C / 4) 248 enum { 249 IS_HARD_ACCESS_COMPLETE = 1, 250 IS_AUTONEG = (1 << 1), 251 IS_RX_COMPLETE = (1 << 2), 252 IS_RX_REJECT = (1 << 3), 253 IS_TX_COMPLETE = (1 << 5), 254 IS_RX_DCM_LOCK = (1 << 6), 255 IS_MGM_RDY = (1 << 7), 256 IS_PHY_RST_DONE = (1 << 8), 257 }; 258 259 #define R_IP (0x010 / 4) 260 #define R_IE (0x014 / 4) 261 #define R_UAWL (0x020 / 4) 262 #define R_UAWU (0x024 / 4) 263 #define R_PPST (0x030 / 4) 264 enum { 265 PPST_LINKSTATUS = (1 << 0), 266 PPST_PHY_LINKSTATUS = (1 << 7), 267 }; 268 269 #define R_STATS_RX_BYTESL (0x200 / 4) 270 #define R_STATS_RX_BYTESH (0x204 / 4) 271 #define R_STATS_TX_BYTESL (0x208 / 4) 272 #define R_STATS_TX_BYTESH (0x20C / 4) 273 #define R_STATS_RXL (0x290 / 4) 274 #define R_STATS_RXH (0x294 / 4) 275 #define R_STATS_RX_BCASTL (0x2a0 / 4) 276 #define R_STATS_RX_BCASTH (0x2a4 / 4) 277 #define R_STATS_RX_MCASTL (0x2a8 / 4) 278 #define R_STATS_RX_MCASTH (0x2ac / 4) 279 280 #define R_RCW0 (0x400 / 4) 281 #define R_RCW1 (0x404 / 4) 282 enum { 283 RCW1_VLAN = (1 << 27), 284 RCW1_RX = (1 << 28), 285 RCW1_FCS = (1 << 29), 286 RCW1_JUM = (1 << 30), 287 RCW1_RST = (1 << 31), 288 }; 289 290 #define R_TC (0x408 / 4) 291 enum { 292 TC_VLAN = (1 << 27), 293 TC_TX = (1 << 28), 294 TC_FCS = (1 << 29), 295 TC_JUM = (1 << 30), 296 TC_RST = (1 << 31), 297 }; 298 299 #define R_EMMC (0x410 / 4) 300 enum { 301 EMMC_LINKSPEED_10MB = (0 << 30), 302 EMMC_LINKSPEED_100MB = (1 << 30), 303 EMMC_LINKSPEED_1000MB = (2 << 30), 304 }; 305 306 #define R_PHYC (0x414 / 4) 307 308 #define R_MC (0x500 / 4) 309 #define MC_EN (1 << 6) 310 311 #define R_MCR (0x504 / 4) 312 #define R_MWD (0x508 / 4) 313 #define R_MRD (0x50c / 4) 314 #define R_MIS (0x600 / 4) 315 #define R_MIP (0x620 / 4) 316 #define R_MIE (0x640 / 4) 317 #define R_MIC (0x640 / 4) 318 319 #define R_UAW0 (0x700 / 4) 320 #define R_UAW1 (0x704 / 4) 321 #define R_FMI (0x708 / 4) 322 #define R_AF0 (0x710 / 4) 323 #define R_AF1 (0x714 / 4) 324 #define R_MAX (0x34 / 4) 325 326 /* Indirect registers. */ 327 struct TEMAC { 328 struct MDIOBus mdio_bus; 329 struct PHY phy; 330 331 void *parent; 332 }; 333 334 typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave; 335 typedef struct XilinxAXIEnet XilinxAXIEnet; 336 337 struct XilinxAXIEnetStreamSlave { 338 Object parent; 339 340 struct XilinxAXIEnet *enet; 341 } ; 342 343 struct XilinxAXIEnet { 344 SysBusDevice busdev; 345 MemoryRegion iomem; 346 qemu_irq irq; 347 StreamSlave *tx_data_dev; 348 StreamSlave *tx_control_dev; 349 XilinxAXIEnetStreamSlave rx_data_dev; 350 XilinxAXIEnetStreamSlave rx_control_dev; 351 NICState *nic; 352 NICConf conf; 353 354 355 uint32_t c_rxmem; 356 uint32_t c_txmem; 357 uint32_t c_phyaddr; 358 359 struct TEMAC TEMAC; 360 361 /* MII regs. */ 362 union { 363 uint32_t regs[4]; 364 struct { 365 uint32_t mc; 366 uint32_t mcr; 367 uint32_t mwd; 368 uint32_t mrd; 369 }; 370 } mii; 371 372 struct { 373 uint64_t rx_bytes; 374 uint64_t tx_bytes; 375 376 uint64_t rx; 377 uint64_t rx_bcast; 378 uint64_t rx_mcast; 379 } stats; 380 381 /* Receive configuration words. */ 382 uint32_t rcw[2]; 383 /* Transmit config. */ 384 uint32_t tc; 385 uint32_t emmc; 386 uint32_t phyc; 387 388 /* Unicast Address Word. */ 389 uint32_t uaw[2]; 390 /* Unicast address filter used with extended mcast. */ 391 uint32_t ext_uaw[2]; 392 uint32_t fmi; 393 394 uint32_t regs[R_MAX]; 395 396 /* Multicast filter addrs. */ 397 uint32_t maddr[4][2]; 398 /* 32K x 1 lookup filter. */ 399 uint32_t ext_mtable[1024]; 400 401 uint32_t hdr[CONTROL_PAYLOAD_WORDS]; 402 403 uint8_t *rxmem; 404 uint32_t rxsize; 405 uint32_t rxpos; 406 407 uint8_t rxapp[CONTROL_PAYLOAD_SIZE]; 408 uint32_t rxappsize; 409 410 /* Whether axienet_eth_rx_notify should flush incoming queue. */ 411 bool need_flush; 412 }; 413 414 static void axienet_rx_reset(XilinxAXIEnet *s) 415 { 416 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; 417 } 418 419 static void axienet_tx_reset(XilinxAXIEnet *s) 420 { 421 s->tc = TC_JUM | TC_TX | TC_VLAN; 422 } 423 424 static inline int axienet_rx_resetting(XilinxAXIEnet *s) 425 { 426 return s->rcw[1] & RCW1_RST; 427 } 428 429 static inline int axienet_rx_enabled(XilinxAXIEnet *s) 430 { 431 return s->rcw[1] & RCW1_RX; 432 } 433 434 static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) 435 { 436 return !!(s->regs[R_RAF] & RAF_EMCF_EN); 437 } 438 439 static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) 440 { 441 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); 442 } 443 444 static void xilinx_axienet_reset(DeviceState *d) 445 { 446 XilinxAXIEnet *s = XILINX_AXI_ENET(d); 447 448 axienet_rx_reset(s); 449 axienet_tx_reset(s); 450 451 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; 452 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; 453 454 s->emmc = EMMC_LINKSPEED_100MB; 455 } 456 457 static void enet_update_irq(XilinxAXIEnet *s) 458 { 459 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; 460 qemu_set_irq(s->irq, !!s->regs[R_IP]); 461 } 462 463 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) 464 { 465 XilinxAXIEnet *s = opaque; 466 uint32_t r = 0; 467 addr >>= 2; 468 469 switch (addr) { 470 case R_RCW0: 471 case R_RCW1: 472 r = s->rcw[addr & 1]; 473 break; 474 475 case R_TC: 476 r = s->tc; 477 break; 478 479 case R_EMMC: 480 r = s->emmc; 481 break; 482 483 case R_PHYC: 484 r = s->phyc; 485 break; 486 487 case R_MCR: 488 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ 489 break; 490 491 case R_STATS_RX_BYTESL: 492 case R_STATS_RX_BYTESH: 493 r = s->stats.rx_bytes >> (32 * (addr & 1)); 494 break; 495 496 case R_STATS_TX_BYTESL: 497 case R_STATS_TX_BYTESH: 498 r = s->stats.tx_bytes >> (32 * (addr & 1)); 499 break; 500 501 case R_STATS_RXL: 502 case R_STATS_RXH: 503 r = s->stats.rx >> (32 * (addr & 1)); 504 break; 505 case R_STATS_RX_BCASTL: 506 case R_STATS_RX_BCASTH: 507 r = s->stats.rx_bcast >> (32 * (addr & 1)); 508 break; 509 case R_STATS_RX_MCASTL: 510 case R_STATS_RX_MCASTH: 511 r = s->stats.rx_mcast >> (32 * (addr & 1)); 512 break; 513 514 case R_MC: 515 case R_MWD: 516 case R_MRD: 517 r = s->mii.regs[addr & 3]; 518 break; 519 520 case R_UAW0: 521 case R_UAW1: 522 r = s->uaw[addr & 1]; 523 break; 524 525 case R_UAWU: 526 case R_UAWL: 527 r = s->ext_uaw[addr & 1]; 528 break; 529 530 case R_FMI: 531 r = s->fmi; 532 break; 533 534 case R_AF0: 535 case R_AF1: 536 r = s->maddr[s->fmi & 3][addr & 1]; 537 break; 538 539 case 0x8000 ... 0x83ff: 540 r = s->ext_mtable[addr - 0x8000]; 541 break; 542 543 default: 544 if (addr < ARRAY_SIZE(s->regs)) { 545 r = s->regs[addr]; 546 } 547 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 548 __func__, addr * 4, r)); 549 break; 550 } 551 return r; 552 } 553 554 static void enet_write(void *opaque, hwaddr addr, 555 uint64_t value, unsigned size) 556 { 557 XilinxAXIEnet *s = opaque; 558 struct TEMAC *t = &s->TEMAC; 559 560 addr >>= 2; 561 switch (addr) { 562 case R_RCW0: 563 case R_RCW1: 564 s->rcw[addr & 1] = value; 565 if ((addr & 1) && value & RCW1_RST) { 566 axienet_rx_reset(s); 567 } else { 568 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 569 } 570 break; 571 572 case R_TC: 573 s->tc = value; 574 if (value & TC_RST) { 575 axienet_tx_reset(s); 576 } 577 break; 578 579 case R_EMMC: 580 s->emmc = value; 581 break; 582 583 case R_PHYC: 584 s->phyc = value; 585 break; 586 587 case R_MC: 588 value &= ((1 << 7) - 1); 589 590 /* Enable the MII. */ 591 if (value & MC_EN) { 592 unsigned int miiclkdiv = value & ((1 << 6) - 1); 593 if (!miiclkdiv) { 594 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n"); 595 } 596 } 597 s->mii.mc = value; 598 break; 599 600 case R_MCR: { 601 unsigned int phyaddr = (value >> 24) & 0x1f; 602 unsigned int regaddr = (value >> 16) & 0x1f; 603 unsigned int op = (value >> 14) & 3; 604 unsigned int initiate = (value >> 11) & 1; 605 606 if (initiate) { 607 if (op == 1) { 608 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); 609 } else if (op == 2) { 610 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); 611 } else { 612 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op); 613 } 614 } 615 s->mii.mcr = value; 616 break; 617 } 618 619 case R_MWD: 620 case R_MRD: 621 s->mii.regs[addr & 3] = value; 622 break; 623 624 625 case R_UAW0: 626 case R_UAW1: 627 s->uaw[addr & 1] = value; 628 break; 629 630 case R_UAWL: 631 case R_UAWU: 632 s->ext_uaw[addr & 1] = value; 633 break; 634 635 case R_FMI: 636 s->fmi = value; 637 break; 638 639 case R_AF0: 640 case R_AF1: 641 s->maddr[s->fmi & 3][addr & 1] = value; 642 break; 643 644 case R_IS: 645 s->regs[addr] &= ~value; 646 break; 647 648 case 0x8000 ... 0x83ff: 649 s->ext_mtable[addr - 0x8000] = value; 650 break; 651 652 default: 653 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 654 __func__, addr * 4, (unsigned)value)); 655 if (addr < ARRAY_SIZE(s->regs)) { 656 s->regs[addr] = value; 657 } 658 break; 659 } 660 enet_update_irq(s); 661 } 662 663 static const MemoryRegionOps enet_ops = { 664 .read = enet_read, 665 .write = enet_write, 666 .endianness = DEVICE_LITTLE_ENDIAN, 667 }; 668 669 static int eth_can_rx(XilinxAXIEnet *s) 670 { 671 /* RX enabled? */ 672 return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s); 673 } 674 675 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) 676 { 677 int match = 1; 678 679 if (memcmp(buf, &f0, 4)) { 680 match = 0; 681 } 682 683 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { 684 match = 0; 685 } 686 687 return match; 688 } 689 690 static void axienet_eth_rx_notify(void *opaque) 691 { 692 XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); 693 694 while (s->rxappsize && stream_can_push(s->tx_control_dev, 695 axienet_eth_rx_notify, s)) { 696 size_t ret = stream_push(s->tx_control_dev, 697 (void *)s->rxapp + CONTROL_PAYLOAD_SIZE 698 - s->rxappsize, s->rxappsize); 699 s->rxappsize -= ret; 700 } 701 702 while (s->rxsize && stream_can_push(s->tx_data_dev, 703 axienet_eth_rx_notify, s)) { 704 size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, 705 s->rxsize); 706 s->rxsize -= ret; 707 s->rxpos += ret; 708 if (!s->rxsize) { 709 s->regs[R_IS] |= IS_RX_COMPLETE; 710 if (s->need_flush) { 711 s->need_flush = false; 712 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 713 } 714 } 715 } 716 enet_update_irq(s); 717 } 718 719 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 720 { 721 XilinxAXIEnet *s = qemu_get_nic_opaque(nc); 722 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 723 0xff, 0xff, 0xff}; 724 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; 725 uint32_t app[CONTROL_PAYLOAD_WORDS] = {0}; 726 int promisc = s->fmi & (1 << 31); 727 int unicast, broadcast, multicast, ip_multicast = 0; 728 uint32_t csum32; 729 uint16_t csum16; 730 int i; 731 732 DENET(qemu_log("%s: %zd bytes\n", __func__, size)); 733 734 if (!eth_can_rx(s)) { 735 s->need_flush = true; 736 return 0; 737 } 738 739 unicast = ~buf[0] & 0x1; 740 broadcast = memcmp(buf, sa_bcast, 6) == 0; 741 multicast = !unicast && !broadcast; 742 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { 743 ip_multicast = 1; 744 } 745 746 /* Jumbo or vlan sizes ? */ 747 if (!(s->rcw[1] & RCW1_JUM)) { 748 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { 749 return size; 750 } 751 } 752 753 /* Basic Address filters. If you want to use the extended filters 754 you'll generally have to place the ethernet mac into promiscuous mode 755 to avoid the basic filtering from dropping most frames. */ 756 if (!promisc) { 757 if (unicast) { 758 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { 759 return size; 760 } 761 } else { 762 if (broadcast) { 763 /* Broadcast. */ 764 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 765 return size; 766 } 767 } else { 768 int drop = 1; 769 770 /* Multicast. */ 771 if (s->regs[R_RAF] & RAF_MCAST_REJ) { 772 return size; 773 } 774 775 for (i = 0; i < 4; i++) { 776 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { 777 drop = 0; 778 break; 779 } 780 } 781 782 if (drop) { 783 return size; 784 } 785 } 786 } 787 } 788 789 /* Extended mcast filtering enabled? */ 790 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) { 791 if (unicast) { 792 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { 793 return size; 794 } 795 } else { 796 if (broadcast) { 797 /* Broadcast. ??? */ 798 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 799 return size; 800 } 801 } else { 802 int idx, bit; 803 804 /* Multicast. */ 805 if (!memcmp(buf, sa_ipmcast, 3)) { 806 return size; 807 } 808 809 idx = (buf[4] & 0x7f) << 8; 810 idx |= buf[5]; 811 812 bit = 1 << (idx & 0x1f); 813 idx >>= 5; 814 815 if (!(s->ext_mtable[idx] & bit)) { 816 return size; 817 } 818 } 819 } 820 } 821 822 if (size < 12) { 823 s->regs[R_IS] |= IS_RX_REJECT; 824 enet_update_irq(s); 825 return -1; 826 } 827 828 if (size > (s->c_rxmem - 4)) { 829 size = s->c_rxmem - 4; 830 } 831 832 memcpy(s->rxmem, buf, size); 833 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ 834 835 if (s->rcw[1] & RCW1_FCS) { 836 size += 4; /* fcs is inband. */ 837 } 838 839 app[0] = 5 << 28; 840 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); 841 /* Fold it once. */ 842 csum32 = (csum32 & 0xffff) + (csum32 >> 16); 843 /* And twice to get rid of possible carries. */ 844 csum16 = (csum32 & 0xffff) + (csum32 >> 16); 845 app[3] = csum16; 846 app[4] = size & 0xffff; 847 848 s->stats.rx_bytes += size; 849 s->stats.rx++; 850 if (multicast) { 851 s->stats.rx_mcast++; 852 app[2] |= 1 | (ip_multicast << 1); 853 } else if (broadcast) { 854 s->stats.rx_bcast++; 855 app[2] |= 1 << 3; 856 } 857 858 /* Good frame. */ 859 app[2] |= 1 << 6; 860 861 s->rxsize = size; 862 s->rxpos = 0; 863 for (i = 0; i < ARRAY_SIZE(app); ++i) { 864 app[i] = cpu_to_le32(app[i]); 865 } 866 s->rxappsize = CONTROL_PAYLOAD_SIZE; 867 memcpy(s->rxapp, app, s->rxappsize); 868 axienet_eth_rx_notify(s); 869 870 enet_update_irq(s); 871 return size; 872 } 873 874 static size_t 875 xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len) 876 { 877 int i; 878 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); 879 XilinxAXIEnet *s = cs->enet; 880 881 if (len != CONTROL_PAYLOAD_SIZE) { 882 hw_error("AXI Enet requires %d byte control stream payload\n", 883 (int)CONTROL_PAYLOAD_SIZE); 884 } 885 886 memcpy(s->hdr, buf, len); 887 888 for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { 889 s->hdr[i] = le32_to_cpu(s->hdr[i]); 890 } 891 return len; 892 } 893 894 static size_t 895 xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size) 896 { 897 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); 898 XilinxAXIEnet *s = ds->enet; 899 900 /* TX enable ? */ 901 if (!(s->tc & TC_TX)) { 902 return size; 903 } 904 905 /* Jumbo or vlan sizes ? */ 906 if (!(s->tc & TC_JUM)) { 907 if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) { 908 return size; 909 } 910 } 911 912 if (s->hdr[0] & 1) { 913 unsigned int start_off = s->hdr[1] >> 16; 914 unsigned int write_off = s->hdr[1] & 0xffff; 915 uint32_t tmp_csum; 916 uint16_t csum; 917 918 tmp_csum = net_checksum_add(size - start_off, 919 (uint8_t *)buf + start_off); 920 /* Accumulate the seed. */ 921 tmp_csum += s->hdr[2] & 0xffff; 922 923 /* Fold the 32bit partial checksum. */ 924 csum = net_checksum_finish(tmp_csum); 925 926 /* Writeback. */ 927 buf[write_off] = csum >> 8; 928 buf[write_off + 1] = csum & 0xff; 929 } 930 931 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 932 933 s->stats.tx_bytes += size; 934 s->regs[R_IS] |= IS_TX_COMPLETE; 935 enet_update_irq(s); 936 937 return size; 938 } 939 940 static NetClientInfo net_xilinx_enet_info = { 941 .type = NET_CLIENT_DRIVER_NIC, 942 .size = sizeof(NICState), 943 .receive = eth_rx, 944 }; 945 946 static void xilinx_enet_realize(DeviceState *dev, Error **errp) 947 { 948 XilinxAXIEnet *s = XILINX_AXI_ENET(dev); 949 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); 950 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM( 951 &s->rx_control_dev); 952 Error *local_err = NULL; 953 954 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", 955 (Object **) &ds->enet, 956 object_property_allow_set_link, 957 OBJ_PROP_LINK_STRONG, 958 &local_err); 959 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", 960 (Object **) &cs->enet, 961 object_property_allow_set_link, 962 OBJ_PROP_LINK_STRONG, 963 &local_err); 964 if (local_err) { 965 goto xilinx_enet_realize_fail; 966 } 967 object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_err); 968 object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_err); 969 if (local_err) { 970 goto xilinx_enet_realize_fail; 971 } 972 973 qemu_macaddr_default_if_unset(&s->conf.macaddr); 974 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, 975 object_get_typename(OBJECT(dev)), dev->id, s); 976 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 977 978 tdk_init(&s->TEMAC.phy); 979 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); 980 981 s->TEMAC.parent = s; 982 983 s->rxmem = g_malloc(s->c_rxmem); 984 return; 985 986 xilinx_enet_realize_fail: 987 error_propagate(errp, local_err); 988 } 989 990 static void xilinx_enet_init(Object *obj) 991 { 992 XilinxAXIEnet *s = XILINX_AXI_ENET(obj); 993 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 994 995 object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), 996 TYPE_XILINX_AXI_ENET_DATA_STREAM); 997 object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), 998 TYPE_XILINX_AXI_ENET_CONTROL_STREAM); 999 object_property_add_child(OBJECT(s), "axistream-connected-target", 1000 (Object *)&s->rx_data_dev, &error_abort); 1001 object_property_add_child(OBJECT(s), "axistream-control-connected-target", 1002 (Object *)&s->rx_control_dev, &error_abort); 1003 1004 sysbus_init_irq(sbd, &s->irq); 1005 1006 memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); 1007 sysbus_init_mmio(sbd, &s->iomem); 1008 } 1009 1010 static Property xilinx_enet_properties[] = { 1011 DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), 1012 DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), 1013 DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), 1014 DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), 1015 DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, 1016 tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), 1017 DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, 1018 tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), 1019 DEFINE_PROP_END_OF_LIST(), 1020 }; 1021 1022 static void xilinx_enet_class_init(ObjectClass *klass, void *data) 1023 { 1024 DeviceClass *dc = DEVICE_CLASS(klass); 1025 1026 dc->realize = xilinx_enet_realize; 1027 dc->props = xilinx_enet_properties; 1028 dc->reset = xilinx_axienet_reset; 1029 } 1030 1031 static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data) 1032 { 1033 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); 1034 1035 ssc->push = data; 1036 } 1037 1038 static const TypeInfo xilinx_enet_info = { 1039 .name = TYPE_XILINX_AXI_ENET, 1040 .parent = TYPE_SYS_BUS_DEVICE, 1041 .instance_size = sizeof(XilinxAXIEnet), 1042 .class_init = xilinx_enet_class_init, 1043 .instance_init = xilinx_enet_init, 1044 }; 1045 1046 static const TypeInfo xilinx_enet_data_stream_info = { 1047 .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, 1048 .parent = TYPE_OBJECT, 1049 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), 1050 .class_init = xilinx_enet_stream_class_init, 1051 .class_data = xilinx_axienet_data_stream_push, 1052 .interfaces = (InterfaceInfo[]) { 1053 { TYPE_STREAM_SLAVE }, 1054 { } 1055 } 1056 }; 1057 1058 static const TypeInfo xilinx_enet_control_stream_info = { 1059 .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, 1060 .parent = TYPE_OBJECT, 1061 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), 1062 .class_init = xilinx_enet_stream_class_init, 1063 .class_data = xilinx_axienet_control_stream_push, 1064 .interfaces = (InterfaceInfo[]) { 1065 { TYPE_STREAM_SLAVE }, 1066 { } 1067 } 1068 }; 1069 1070 static void xilinx_enet_register_types(void) 1071 { 1072 type_register_static(&xilinx_enet_info); 1073 type_register_static(&xilinx_enet_data_stream_info); 1074 type_register_static(&xilinx_enet_control_stream_info); 1075 } 1076 1077 type_init(xilinx_enet_register_types) 1078