1 /* 2 * QEMU model of XGMAC Ethernet. 3 * 4 * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias. 5 * 6 * Copyright (c) 2011 Calxeda, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/irq.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/sysbus.h" 31 #include "migration/vmstate.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 #include "net/net.h" 35 #include "qom/object.h" 36 37 #ifdef DEBUG_XGMAC 38 #define DEBUGF_BRK(message, args...) do { \ 39 fprintf(stderr, (message), ## args); \ 40 } while (0) 41 #else 42 #define DEBUGF_BRK(message, args...) do { } while (0) 43 #endif 44 45 #define XGMAC_CONTROL 0x00000000 /* MAC Configuration */ 46 #define XGMAC_FRAME_FILTER 0x00000001 /* MAC Frame Filter */ 47 #define XGMAC_FLOW_CTRL 0x00000006 /* MAC Flow Control */ 48 #define XGMAC_VLAN_TAG 0x00000007 /* VLAN Tags */ 49 #define XGMAC_VERSION 0x00000008 /* Version */ 50 /* VLAN tag for insertion or replacement into tx frames */ 51 #define XGMAC_VLAN_INCL 0x00000009 52 #define XGMAC_LPI_CTRL 0x0000000a /* LPI Control and Status */ 53 #define XGMAC_LPI_TIMER 0x0000000b /* LPI Timers Control */ 54 #define XGMAC_TX_PACE 0x0000000c /* Transmit Pace and Stretch */ 55 #define XGMAC_VLAN_HASH 0x0000000d /* VLAN Hash Table */ 56 #define XGMAC_DEBUG 0x0000000e /* Debug */ 57 #define XGMAC_INT_STATUS 0x0000000f /* Interrupt and Control */ 58 /* HASH table registers */ 59 #define XGMAC_HASH(n) ((0x00000300/4) + (n)) 60 #define XGMAC_NUM_HASH 16 61 /* Operation Mode */ 62 #define XGMAC_OPMODE (0x00000400/4) 63 /* Remote Wake-Up Frame Filter */ 64 #define XGMAC_REMOTE_WAKE (0x00000700/4) 65 /* PMT Control and Status */ 66 #define XGMAC_PMT (0x00000704/4) 67 68 #define XGMAC_ADDR_HIGH(reg) (0x00000010+((reg) * 2)) 69 #define XGMAC_ADDR_LOW(reg) (0x00000011+((reg) * 2)) 70 71 #define DMA_BUS_MODE 0x000003c0 /* Bus Mode */ 72 #define DMA_XMT_POLL_DEMAND 0x000003c1 /* Transmit Poll Demand */ 73 #define DMA_RCV_POLL_DEMAND 0x000003c2 /* Received Poll Demand */ 74 #define DMA_RCV_BASE_ADDR 0x000003c3 /* Receive List Base */ 75 #define DMA_TX_BASE_ADDR 0x000003c4 /* Transmit List Base */ 76 #define DMA_STATUS 0x000003c5 /* Status Register */ 77 #define DMA_CONTROL 0x000003c6 /* Ctrl (Operational Mode) */ 78 #define DMA_INTR_ENA 0x000003c7 /* Interrupt Enable */ 79 #define DMA_MISSED_FRAME_CTR 0x000003c8 /* Missed Frame Counter */ 80 /* Receive Interrupt Watchdog Timer */ 81 #define DMA_RI_WATCHDOG_TIMER 0x000003c9 82 #define DMA_AXI_BUS 0x000003ca /* AXI Bus Mode */ 83 #define DMA_AXI_STATUS 0x000003cb /* AXI Status */ 84 #define DMA_CUR_TX_DESC_ADDR 0x000003d2 /* Current Host Tx Descriptor */ 85 #define DMA_CUR_RX_DESC_ADDR 0x000003d3 /* Current Host Rx Descriptor */ 86 #define DMA_CUR_TX_BUF_ADDR 0x000003d4 /* Current Host Tx Buffer */ 87 #define DMA_CUR_RX_BUF_ADDR 0x000003d5 /* Current Host Rx Buffer */ 88 #define DMA_HW_FEATURE 0x000003d6 /* Enabled Hardware Features */ 89 90 /* DMA Status register defines */ 91 #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */ 92 #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */ 93 #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */ 94 #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */ 95 #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */ 96 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */ 97 #define DMA_STATUS_TS_SHIFT 20 98 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */ 99 #define DMA_STATUS_RS_SHIFT 17 100 #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */ 101 #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */ 102 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */ 103 #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */ 104 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */ 105 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */ 106 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */ 107 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */ 108 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */ 109 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */ 110 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */ 111 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */ 112 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */ 113 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */ 114 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ 115 116 /* DMA Control register defines */ 117 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */ 118 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */ 119 #define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */ 120 121 struct desc { 122 uint32_t ctl_stat; 123 uint16_t buffer1_size; 124 uint16_t buffer2_size; 125 uint32_t buffer1_addr; 126 uint32_t buffer2_addr; 127 uint32_t ext_stat; 128 uint32_t res[3]; 129 }; 130 131 #define R_MAX 0x400 132 133 typedef struct RxTxStats { 134 uint64_t rx_bytes; 135 uint64_t tx_bytes; 136 137 uint64_t rx; 138 uint64_t rx_bcast; 139 uint64_t rx_mcast; 140 } RxTxStats; 141 142 #define TYPE_XGMAC "xgmac" 143 typedef struct XgmacState XgmacState; 144 DECLARE_INSTANCE_CHECKER(XgmacState, XGMAC, 145 TYPE_XGMAC) 146 147 struct XgmacState { 148 SysBusDevice parent_obj; 149 150 MemoryRegion iomem; 151 qemu_irq sbd_irq; 152 qemu_irq pmt_irq; 153 qemu_irq mci_irq; 154 NICState *nic; 155 NICConf conf; 156 157 struct RxTxStats stats; 158 uint32_t regs[R_MAX]; 159 }; 160 161 static const VMStateDescription vmstate_rxtx_stats = { 162 .name = "xgmac_stats", 163 .version_id = 1, 164 .minimum_version_id = 1, 165 .fields = (VMStateField[]) { 166 VMSTATE_UINT64(rx_bytes, RxTxStats), 167 VMSTATE_UINT64(tx_bytes, RxTxStats), 168 VMSTATE_UINT64(rx, RxTxStats), 169 VMSTATE_UINT64(rx_bcast, RxTxStats), 170 VMSTATE_UINT64(rx_mcast, RxTxStats), 171 VMSTATE_END_OF_LIST() 172 } 173 }; 174 175 static const VMStateDescription vmstate_xgmac = { 176 .name = "xgmac", 177 .version_id = 1, 178 .minimum_version_id = 1, 179 .fields = (VMStateField[]) { 180 VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats), 181 VMSTATE_UINT32_ARRAY(regs, XgmacState, R_MAX), 182 VMSTATE_END_OF_LIST() 183 } 184 }; 185 186 static void xgmac_read_desc(XgmacState *s, struct desc *d, int rx) 187 { 188 uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] : 189 s->regs[DMA_CUR_TX_DESC_ADDR]; 190 cpu_physical_memory_read(addr, d, sizeof(*d)); 191 } 192 193 static void xgmac_write_desc(XgmacState *s, struct desc *d, int rx) 194 { 195 int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR; 196 uint32_t addr = s->regs[reg]; 197 198 if (!rx && (d->ctl_stat & 0x00200000)) { 199 s->regs[reg] = s->regs[DMA_TX_BASE_ADDR]; 200 } else if (rx && (d->buffer1_size & 0x8000)) { 201 s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR]; 202 } else { 203 s->regs[reg] += sizeof(*d); 204 } 205 cpu_physical_memory_write(addr, d, sizeof(*d)); 206 } 207 208 static void xgmac_enet_send(XgmacState *s) 209 { 210 struct desc bd; 211 int frame_size; 212 int len; 213 uint8_t frame[8192]; 214 uint8_t *ptr; 215 216 ptr = frame; 217 frame_size = 0; 218 while (1) { 219 xgmac_read_desc(s, &bd, 0); 220 if ((bd.ctl_stat & 0x80000000) == 0) { 221 /* Run out of descriptors to transmit. */ 222 break; 223 } 224 len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff); 225 226 /* 227 * FIXME: these cases of malformed tx descriptors (bad sizes) 228 * should probably be reported back to the guest somehow 229 * rather than simply silently stopping processing, but we 230 * don't know what the hardware does in this situation. 231 * This will only happen for buggy guests anyway. 232 */ 233 if ((bd.buffer1_size & 0xfff) > 2048) { 234 DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- " 235 "xgmac buffer 1 len on send > 2048 (0x%x)\n", 236 __func__, bd.buffer1_size & 0xfff); 237 break; 238 } 239 if ((bd.buffer2_size & 0xfff) != 0) { 240 DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- " 241 "xgmac buffer 2 len on send != 0 (0x%x)\n", 242 __func__, bd.buffer2_size & 0xfff); 243 break; 244 } 245 if (frame_size + len >= sizeof(frame)) { 246 DEBUGF_BRK("qemu:%s: buffer overflow %d read into %zu " 247 "buffer\n" , __func__, frame_size + len, sizeof(frame)); 248 DEBUGF_BRK("qemu:%s: buffer1.size=%d; buffer2.size=%d\n", 249 __func__, bd.buffer1_size, bd.buffer2_size); 250 break; 251 } 252 253 cpu_physical_memory_read(bd.buffer1_addr, ptr, len); 254 ptr += len; 255 frame_size += len; 256 if (bd.ctl_stat & 0x20000000) { 257 /* Last buffer in frame. */ 258 qemu_send_packet(qemu_get_queue(s->nic), frame, len); 259 ptr = frame; 260 frame_size = 0; 261 s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS; 262 } 263 bd.ctl_stat &= ~0x80000000; 264 /* Write back the modified descriptor. */ 265 xgmac_write_desc(s, &bd, 0); 266 } 267 } 268 269 static void enet_update_irq(XgmacState *s) 270 { 271 int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA]; 272 qemu_set_irq(s->sbd_irq, !!stat); 273 } 274 275 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) 276 { 277 XgmacState *s = opaque; 278 uint64_t r = 0; 279 addr >>= 2; 280 281 switch (addr) { 282 case XGMAC_VERSION: 283 r = 0x1012; 284 break; 285 default: 286 if (addr < ARRAY_SIZE(s->regs)) { 287 r = s->regs[addr]; 288 } 289 break; 290 } 291 return r; 292 } 293 294 static void enet_write(void *opaque, hwaddr addr, 295 uint64_t value, unsigned size) 296 { 297 XgmacState *s = opaque; 298 299 addr >>= 2; 300 switch (addr) { 301 case DMA_BUS_MODE: 302 s->regs[DMA_BUS_MODE] = value & ~0x1; 303 break; 304 case DMA_XMT_POLL_DEMAND: 305 xgmac_enet_send(s); 306 break; 307 case DMA_STATUS: 308 s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value; 309 break; 310 case DMA_RCV_BASE_ADDR: 311 s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value; 312 break; 313 case DMA_TX_BASE_ADDR: 314 s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value; 315 break; 316 default: 317 if (addr < ARRAY_SIZE(s->regs)) { 318 s->regs[addr] = value; 319 } 320 break; 321 } 322 enet_update_irq(s); 323 } 324 325 static const MemoryRegionOps enet_mem_ops = { 326 .read = enet_read, 327 .write = enet_write, 328 .endianness = DEVICE_LITTLE_ENDIAN, 329 }; 330 331 static int eth_can_rx(XgmacState *s) 332 { 333 /* RX enabled? */ 334 return s->regs[DMA_CONTROL] & DMA_CONTROL_SR; 335 } 336 337 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 338 { 339 XgmacState *s = qemu_get_nic_opaque(nc); 340 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 341 0xff, 0xff, 0xff}; 342 int unicast, broadcast, multicast; 343 struct desc bd; 344 ssize_t ret; 345 346 if (!eth_can_rx(s)) { 347 return -1; 348 } 349 unicast = ~buf[0] & 0x1; 350 broadcast = memcmp(buf, sa_bcast, 6) == 0; 351 multicast = !unicast && !broadcast; 352 if (size < 12) { 353 s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS; 354 ret = -1; 355 goto out; 356 } 357 358 xgmac_read_desc(s, &bd, 1); 359 if ((bd.ctl_stat & 0x80000000) == 0) { 360 s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS; 361 ret = size; 362 goto out; 363 } 364 365 cpu_physical_memory_write(bd.buffer1_addr, buf, size); 366 367 /* Add in the 4 bytes for crc (the real hw returns length incl crc) */ 368 size += 4; 369 bd.ctl_stat = (size << 16) | 0x300; 370 xgmac_write_desc(s, &bd, 1); 371 372 s->stats.rx_bytes += size; 373 s->stats.rx++; 374 if (multicast) { 375 s->stats.rx_mcast++; 376 } else if (broadcast) { 377 s->stats.rx_bcast++; 378 } 379 380 s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS; 381 ret = size; 382 383 out: 384 enet_update_irq(s); 385 return ret; 386 } 387 388 static NetClientInfo net_xgmac_enet_info = { 389 .type = NET_CLIENT_DRIVER_NIC, 390 .size = sizeof(NICState), 391 .receive = eth_rx, 392 }; 393 394 static void xgmac_enet_realize(DeviceState *dev, Error **errp) 395 { 396 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 397 XgmacState *s = XGMAC(dev); 398 399 memory_region_init_io(&s->iomem, OBJECT(s), &enet_mem_ops, s, 400 "xgmac", 0x1000); 401 sysbus_init_mmio(sbd, &s->iomem); 402 sysbus_init_irq(sbd, &s->sbd_irq); 403 sysbus_init_irq(sbd, &s->pmt_irq); 404 sysbus_init_irq(sbd, &s->mci_irq); 405 406 qemu_macaddr_default_if_unset(&s->conf.macaddr); 407 s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf, 408 object_get_typename(OBJECT(dev)), dev->id, s); 409 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 410 411 s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) | 412 s->conf.macaddr.a[4]; 413 s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) | 414 (s->conf.macaddr.a[2] << 16) | 415 (s->conf.macaddr.a[1] << 8) | 416 s->conf.macaddr.a[0]; 417 } 418 419 static Property xgmac_properties[] = { 420 DEFINE_NIC_PROPERTIES(XgmacState, conf), 421 DEFINE_PROP_END_OF_LIST(), 422 }; 423 424 static void xgmac_enet_class_init(ObjectClass *klass, void *data) 425 { 426 DeviceClass *dc = DEVICE_CLASS(klass); 427 428 dc->realize = xgmac_enet_realize; 429 dc->vmsd = &vmstate_xgmac; 430 device_class_set_props(dc, xgmac_properties); 431 } 432 433 static const TypeInfo xgmac_enet_info = { 434 .name = TYPE_XGMAC, 435 .parent = TYPE_SYS_BUS_DEVICE, 436 .instance_size = sizeof(XgmacState), 437 .class_init = xgmac_enet_class_init, 438 }; 439 440 static void xgmac_enet_register_types(void) 441 { 442 type_register_static(&xgmac_enet_info); 443 } 444 445 type_init(xgmac_enet_register_types) 446