1 /* 2 * QEMU model of XGMAC Ethernet. 3 * 4 * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias. 5 * 6 * Copyright (c) 2011 Calxeda, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "hw/sysbus.h" 28 #include "sysemu/char.h" 29 #include "qemu/log.h" 30 #include "net/net.h" 31 #include "net/checksum.h" 32 33 #ifdef DEBUG_XGMAC 34 #define DEBUGF_BRK(message, args...) do { \ 35 fprintf(stderr, (message), ## args); \ 36 } while (0) 37 #else 38 #define DEBUGF_BRK(message, args...) do { } while (0) 39 #endif 40 41 #define XGMAC_CONTROL 0x00000000 /* MAC Configuration */ 42 #define XGMAC_FRAME_FILTER 0x00000001 /* MAC Frame Filter */ 43 #define XGMAC_FLOW_CTRL 0x00000006 /* MAC Flow Control */ 44 #define XGMAC_VLAN_TAG 0x00000007 /* VLAN Tags */ 45 #define XGMAC_VERSION 0x00000008 /* Version */ 46 /* VLAN tag for insertion or replacement into tx frames */ 47 #define XGMAC_VLAN_INCL 0x00000009 48 #define XGMAC_LPI_CTRL 0x0000000a /* LPI Control and Status */ 49 #define XGMAC_LPI_TIMER 0x0000000b /* LPI Timers Control */ 50 #define XGMAC_TX_PACE 0x0000000c /* Transmit Pace and Stretch */ 51 #define XGMAC_VLAN_HASH 0x0000000d /* VLAN Hash Table */ 52 #define XGMAC_DEBUG 0x0000000e /* Debug */ 53 #define XGMAC_INT_STATUS 0x0000000f /* Interrupt and Control */ 54 /* HASH table registers */ 55 #define XGMAC_HASH(n) ((0x00000300/4) + (n)) 56 #define XGMAC_NUM_HASH 16 57 /* Operation Mode */ 58 #define XGMAC_OPMODE (0x00000400/4) 59 /* Remote Wake-Up Frame Filter */ 60 #define XGMAC_REMOTE_WAKE (0x00000700/4) 61 /* PMT Control and Status */ 62 #define XGMAC_PMT (0x00000704/4) 63 64 #define XGMAC_ADDR_HIGH(reg) (0x00000010+((reg) * 2)) 65 #define XGMAC_ADDR_LOW(reg) (0x00000011+((reg) * 2)) 66 67 #define DMA_BUS_MODE 0x000003c0 /* Bus Mode */ 68 #define DMA_XMT_POLL_DEMAND 0x000003c1 /* Transmit Poll Demand */ 69 #define DMA_RCV_POLL_DEMAND 0x000003c2 /* Received Poll Demand */ 70 #define DMA_RCV_BASE_ADDR 0x000003c3 /* Receive List Base */ 71 #define DMA_TX_BASE_ADDR 0x000003c4 /* Transmit List Base */ 72 #define DMA_STATUS 0x000003c5 /* Status Register */ 73 #define DMA_CONTROL 0x000003c6 /* Ctrl (Operational Mode) */ 74 #define DMA_INTR_ENA 0x000003c7 /* Interrupt Enable */ 75 #define DMA_MISSED_FRAME_CTR 0x000003c8 /* Missed Frame Counter */ 76 /* Receive Interrupt Watchdog Timer */ 77 #define DMA_RI_WATCHDOG_TIMER 0x000003c9 78 #define DMA_AXI_BUS 0x000003ca /* AXI Bus Mode */ 79 #define DMA_AXI_STATUS 0x000003cb /* AXI Status */ 80 #define DMA_CUR_TX_DESC_ADDR 0x000003d2 /* Current Host Tx Descriptor */ 81 #define DMA_CUR_RX_DESC_ADDR 0x000003d3 /* Current Host Rx Descriptor */ 82 #define DMA_CUR_TX_BUF_ADDR 0x000003d4 /* Current Host Tx Buffer */ 83 #define DMA_CUR_RX_BUF_ADDR 0x000003d5 /* Current Host Rx Buffer */ 84 #define DMA_HW_FEATURE 0x000003d6 /* Enabled Hardware Features */ 85 86 /* DMA Status register defines */ 87 #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */ 88 #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */ 89 #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */ 90 #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */ 91 #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */ 92 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */ 93 #define DMA_STATUS_TS_SHIFT 20 94 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */ 95 #define DMA_STATUS_RS_SHIFT 17 96 #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */ 97 #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */ 98 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */ 99 #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */ 100 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */ 101 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */ 102 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */ 103 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */ 104 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */ 105 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */ 106 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */ 107 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */ 108 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */ 109 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */ 110 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ 111 112 /* DMA Control register defines */ 113 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */ 114 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */ 115 #define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */ 116 117 struct desc { 118 uint32_t ctl_stat; 119 uint16_t buffer1_size; 120 uint16_t buffer2_size; 121 uint32_t buffer1_addr; 122 uint32_t buffer2_addr; 123 uint32_t ext_stat; 124 uint32_t res[3]; 125 }; 126 127 #define R_MAX 0x400 128 129 typedef struct RxTxStats { 130 uint64_t rx_bytes; 131 uint64_t tx_bytes; 132 133 uint64_t rx; 134 uint64_t rx_bcast; 135 uint64_t rx_mcast; 136 } RxTxStats; 137 138 #define TYPE_XGMAC "xgmac" 139 #define XGMAC(obj) OBJECT_CHECK(XgmacState, (obj), TYPE_XGMAC) 140 141 typedef struct XgmacState { 142 SysBusDevice parent_obj; 143 144 MemoryRegion iomem; 145 qemu_irq sbd_irq; 146 qemu_irq pmt_irq; 147 qemu_irq mci_irq; 148 NICState *nic; 149 NICConf conf; 150 151 struct RxTxStats stats; 152 uint32_t regs[R_MAX]; 153 } XgmacState; 154 155 const VMStateDescription vmstate_rxtx_stats = { 156 .name = "xgmac_stats", 157 .version_id = 1, 158 .minimum_version_id = 1, 159 .fields = (VMStateField[]) { 160 VMSTATE_UINT64(rx_bytes, RxTxStats), 161 VMSTATE_UINT64(tx_bytes, RxTxStats), 162 VMSTATE_UINT64(rx, RxTxStats), 163 VMSTATE_UINT64(rx_bcast, RxTxStats), 164 VMSTATE_UINT64(rx_mcast, RxTxStats), 165 VMSTATE_END_OF_LIST() 166 } 167 }; 168 169 static const VMStateDescription vmstate_xgmac = { 170 .name = "xgmac", 171 .version_id = 1, 172 .minimum_version_id = 1, 173 .fields = (VMStateField[]) { 174 VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats), 175 VMSTATE_UINT32_ARRAY(regs, XgmacState, R_MAX), 176 VMSTATE_END_OF_LIST() 177 } 178 }; 179 180 static void xgmac_read_desc(XgmacState *s, struct desc *d, int rx) 181 { 182 uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] : 183 s->regs[DMA_CUR_TX_DESC_ADDR]; 184 cpu_physical_memory_read(addr, d, sizeof(*d)); 185 } 186 187 static void xgmac_write_desc(XgmacState *s, struct desc *d, int rx) 188 { 189 int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR; 190 uint32_t addr = s->regs[reg]; 191 192 if (!rx && (d->ctl_stat & 0x00200000)) { 193 s->regs[reg] = s->regs[DMA_TX_BASE_ADDR]; 194 } else if (rx && (d->buffer1_size & 0x8000)) { 195 s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR]; 196 } else { 197 s->regs[reg] += sizeof(*d); 198 } 199 cpu_physical_memory_write(addr, d, sizeof(*d)); 200 } 201 202 static void xgmac_enet_send(XgmacState *s) 203 { 204 struct desc bd; 205 int frame_size; 206 int len; 207 uint8_t frame[8192]; 208 uint8_t *ptr; 209 210 ptr = frame; 211 frame_size = 0; 212 while (1) { 213 xgmac_read_desc(s, &bd, 0); 214 if ((bd.ctl_stat & 0x80000000) == 0) { 215 /* Run out of descriptors to transmit. */ 216 break; 217 } 218 len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff); 219 220 if ((bd.buffer1_size & 0xfff) > 2048) { 221 DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- " 222 "xgmac buffer 1 len on send > 2048 (0x%x)\n", 223 __func__, bd.buffer1_size & 0xfff); 224 } 225 if ((bd.buffer2_size & 0xfff) != 0) { 226 DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- " 227 "xgmac buffer 2 len on send != 0 (0x%x)\n", 228 __func__, bd.buffer2_size & 0xfff); 229 } 230 if (len >= sizeof(frame)) { 231 DEBUGF_BRK("qemu:%s: buffer overflow %d read into %zu " 232 "buffer\n" , __func__, len, sizeof(frame)); 233 DEBUGF_BRK("qemu:%s: buffer1.size=%d; buffer2.size=%d\n", 234 __func__, bd.buffer1_size, bd.buffer2_size); 235 } 236 237 cpu_physical_memory_read(bd.buffer1_addr, ptr, len); 238 ptr += len; 239 frame_size += len; 240 if (bd.ctl_stat & 0x20000000) { 241 /* Last buffer in frame. */ 242 qemu_send_packet(qemu_get_queue(s->nic), frame, len); 243 ptr = frame; 244 frame_size = 0; 245 s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS; 246 } 247 bd.ctl_stat &= ~0x80000000; 248 /* Write back the modified descriptor. */ 249 xgmac_write_desc(s, &bd, 0); 250 } 251 } 252 253 static void enet_update_irq(XgmacState *s) 254 { 255 int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA]; 256 qemu_set_irq(s->sbd_irq, !!stat); 257 } 258 259 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) 260 { 261 XgmacState *s = opaque; 262 uint64_t r = 0; 263 addr >>= 2; 264 265 switch (addr) { 266 case XGMAC_VERSION: 267 r = 0x1012; 268 break; 269 default: 270 if (addr < ARRAY_SIZE(s->regs)) { 271 r = s->regs[addr]; 272 } 273 break; 274 } 275 return r; 276 } 277 278 static void enet_write(void *opaque, hwaddr addr, 279 uint64_t value, unsigned size) 280 { 281 XgmacState *s = opaque; 282 283 addr >>= 2; 284 switch (addr) { 285 case DMA_BUS_MODE: 286 s->regs[DMA_BUS_MODE] = value & ~0x1; 287 break; 288 case DMA_XMT_POLL_DEMAND: 289 xgmac_enet_send(s); 290 break; 291 case DMA_STATUS: 292 s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value; 293 break; 294 case DMA_RCV_BASE_ADDR: 295 s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value; 296 break; 297 case DMA_TX_BASE_ADDR: 298 s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value; 299 break; 300 default: 301 if (addr < ARRAY_SIZE(s->regs)) { 302 s->regs[addr] = value; 303 } 304 break; 305 } 306 enet_update_irq(s); 307 } 308 309 static const MemoryRegionOps enet_mem_ops = { 310 .read = enet_read, 311 .write = enet_write, 312 .endianness = DEVICE_LITTLE_ENDIAN, 313 }; 314 315 static int eth_can_rx(NetClientState *nc) 316 { 317 XgmacState *s = qemu_get_nic_opaque(nc); 318 319 /* RX enabled? */ 320 return s->regs[DMA_CONTROL] & DMA_CONTROL_SR; 321 } 322 323 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 324 { 325 XgmacState *s = qemu_get_nic_opaque(nc); 326 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 327 0xff, 0xff, 0xff}; 328 int unicast, broadcast, multicast; 329 struct desc bd; 330 ssize_t ret; 331 332 unicast = ~buf[0] & 0x1; 333 broadcast = memcmp(buf, sa_bcast, 6) == 0; 334 multicast = !unicast && !broadcast; 335 if (size < 12) { 336 s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS; 337 ret = -1; 338 goto out; 339 } 340 341 xgmac_read_desc(s, &bd, 1); 342 if ((bd.ctl_stat & 0x80000000) == 0) { 343 s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS; 344 ret = size; 345 goto out; 346 } 347 348 cpu_physical_memory_write(bd.buffer1_addr, buf, size); 349 350 /* Add in the 4 bytes for crc (the real hw returns length incl crc) */ 351 size += 4; 352 bd.ctl_stat = (size << 16) | 0x300; 353 xgmac_write_desc(s, &bd, 1); 354 355 s->stats.rx_bytes += size; 356 s->stats.rx++; 357 if (multicast) { 358 s->stats.rx_mcast++; 359 } else if (broadcast) { 360 s->stats.rx_bcast++; 361 } 362 363 s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS; 364 ret = size; 365 366 out: 367 enet_update_irq(s); 368 return ret; 369 } 370 371 static void eth_cleanup(NetClientState *nc) 372 { 373 XgmacState *s = qemu_get_nic_opaque(nc); 374 375 s->nic = NULL; 376 } 377 378 static NetClientInfo net_xgmac_enet_info = { 379 .type = NET_CLIENT_OPTIONS_KIND_NIC, 380 .size = sizeof(NICState), 381 .can_receive = eth_can_rx, 382 .receive = eth_rx, 383 .cleanup = eth_cleanup, 384 }; 385 386 static int xgmac_enet_init(SysBusDevice *sbd) 387 { 388 DeviceState *dev = DEVICE(sbd); 389 XgmacState *s = XGMAC(dev); 390 391 memory_region_init_io(&s->iomem, OBJECT(s), &enet_mem_ops, s, 392 "xgmac", 0x1000); 393 sysbus_init_mmio(sbd, &s->iomem); 394 sysbus_init_irq(sbd, &s->sbd_irq); 395 sysbus_init_irq(sbd, &s->pmt_irq); 396 sysbus_init_irq(sbd, &s->mci_irq); 397 398 qemu_macaddr_default_if_unset(&s->conf.macaddr); 399 s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf, 400 object_get_typename(OBJECT(dev)), dev->id, s); 401 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 402 403 s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) | 404 s->conf.macaddr.a[4]; 405 s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) | 406 (s->conf.macaddr.a[2] << 16) | 407 (s->conf.macaddr.a[1] << 8) | 408 s->conf.macaddr.a[0]; 409 410 return 0; 411 } 412 413 static Property xgmac_properties[] = { 414 DEFINE_NIC_PROPERTIES(XgmacState, conf), 415 DEFINE_PROP_END_OF_LIST(), 416 }; 417 418 static void xgmac_enet_class_init(ObjectClass *klass, void *data) 419 { 420 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 421 DeviceClass *dc = DEVICE_CLASS(klass); 422 423 sbc->init = xgmac_enet_init; 424 dc->vmsd = &vmstate_xgmac; 425 dc->props = xgmac_properties; 426 } 427 428 static const TypeInfo xgmac_enet_info = { 429 .name = TYPE_XGMAC, 430 .parent = TYPE_SYS_BUS_DEVICE, 431 .instance_size = sizeof(XgmacState), 432 .class_init = xgmac_enet_class_init, 433 }; 434 435 static void xgmac_enet_register_types(void) 436 { 437 type_register_static(&xgmac_enet_info); 438 } 439 440 type_init(xgmac_enet_register_types) 441