1 /* 2 * QEMU VMWARE VMXNET3 paravirtual NIC interface definitions 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: 9 * Dmitry Fleytman <dmitry@daynix.com> 10 * Tamir Shomer <tamirs@daynix.com> 11 * Yan Vugenfirer <yan@daynix.com> 12 * 13 * This work is licensed under the terms of the GNU GPL, version 2. 14 * See the COPYING file in the top-level directory. 15 * 16 */ 17 18 #ifndef _QEMU_VMXNET3_H 19 #define _QEMU_VMXNET3_H 20 21 #define VMXNET3_DEVICE_MAX_TX_QUEUES 8 22 #define VMXNET3_DEVICE_MAX_RX_QUEUES 8 /* Keep this value as a power of 2 */ 23 24 /* 25 * VMWARE headers we got from Linux kernel do not fully comply QEMU coding 26 * standards in sense of types and defines used. 27 * Since we didn't want to change VMWARE code, following set of typedefs 28 * and defines needed to compile these headers with QEMU introduced. 29 */ 30 #define u64 uint64_t 31 #define u32 uint32_t 32 #define u16 uint16_t 33 #define u8 uint8_t 34 #define __le16 uint16_t 35 #define __le32 uint32_t 36 #define __le64 uint64_t 37 #define __packed QEMU_PACKED 38 39 #if defined(HOST_WORDS_BIGENDIAN) 40 #define const_cpu_to_le64(x) bswap_64(x) 41 #define __BIG_ENDIAN_BITFIELD 42 #else 43 #define const_cpu_to_le64(x) (x) 44 #endif 45 46 /* 47 * Following is an interface definition for 48 * VMXNET3 device as provided by VMWARE 49 * See original copyright from Linux kernel v3.2.8 50 * header file drivers/net/vmxnet3/vmxnet3_defs.h below. 51 */ 52 53 /* 54 * Linux driver for VMware's vmxnet3 ethernet NIC. 55 * 56 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved. 57 * 58 * This program is free software; you can redistribute it and/or modify it 59 * under the terms of the GNU General Public License as published by the 60 * Free Software Foundation; version 2 of the License and no later version. 61 * 62 * This program is distributed in the hope that it will be useful, but 63 * WITHOUT ANY WARRANTY; without even the implied warranty of 64 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 65 * NON INFRINGEMENT. See the GNU General Public License for more 66 * details. 67 * 68 * You should have received a copy of the GNU General Public License 69 * along with this program; if not, write to the Free Software 70 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 71 * 72 * The full GNU General Public License is included in this distribution in 73 * the file called "COPYING". 74 * 75 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com> 76 * 77 */ 78 79 struct UPT1_TxStats { 80 u64 TSOPktsTxOK; /* TSO pkts post-segmentation */ 81 u64 TSOBytesTxOK; 82 u64 ucastPktsTxOK; 83 u64 ucastBytesTxOK; 84 u64 mcastPktsTxOK; 85 u64 mcastBytesTxOK; 86 u64 bcastPktsTxOK; 87 u64 bcastBytesTxOK; 88 u64 pktsTxError; 89 u64 pktsTxDiscard; 90 }; 91 92 struct UPT1_RxStats { 93 u64 LROPktsRxOK; /* LRO pkts */ 94 u64 LROBytesRxOK; /* bytes from LRO pkts */ 95 /* the following counters are for pkts from the wire, i.e., pre-LRO */ 96 u64 ucastPktsRxOK; 97 u64 ucastBytesRxOK; 98 u64 mcastPktsRxOK; 99 u64 mcastBytesRxOK; 100 u64 bcastPktsRxOK; 101 u64 bcastBytesRxOK; 102 u64 pktsRxOutOfBuf; 103 u64 pktsRxError; 104 }; 105 106 /* interrupt moderation level */ 107 enum { 108 UPT1_IML_NONE = 0, /* no interrupt moderation */ 109 UPT1_IML_HIGHEST = 7, /* least intr generated */ 110 UPT1_IML_ADAPTIVE = 8, /* adpative intr moderation */ 111 }; 112 /* values for UPT1_RSSConf.hashFunc */ 113 enum { 114 UPT1_RSS_HASH_TYPE_NONE = 0x0, 115 UPT1_RSS_HASH_TYPE_IPV4 = 0x01, 116 UPT1_RSS_HASH_TYPE_TCP_IPV4 = 0x02, 117 UPT1_RSS_HASH_TYPE_IPV6 = 0x04, 118 UPT1_RSS_HASH_TYPE_TCP_IPV6 = 0x08, 119 }; 120 121 enum { 122 UPT1_RSS_HASH_FUNC_NONE = 0x0, 123 UPT1_RSS_HASH_FUNC_TOEPLITZ = 0x01, 124 }; 125 126 #define UPT1_RSS_MAX_KEY_SIZE 40 127 #define UPT1_RSS_MAX_IND_TABLE_SIZE 128 128 129 struct UPT1_RSSConf { 130 u16 hashType; 131 u16 hashFunc; 132 u16 hashKeySize; 133 u16 indTableSize; 134 u8 hashKey[UPT1_RSS_MAX_KEY_SIZE]; 135 u8 indTable[UPT1_RSS_MAX_IND_TABLE_SIZE]; 136 }; 137 138 /* features */ 139 enum { 140 UPT1_F_RXCSUM = const_cpu_to_le64(0x0001), /* rx csum verification */ 141 UPT1_F_RSS = const_cpu_to_le64(0x0002), 142 UPT1_F_RXVLAN = const_cpu_to_le64(0x0004), /* VLAN tag stripping */ 143 UPT1_F_LRO = const_cpu_to_le64(0x0008), 144 }; 145 146 /* all registers are 32 bit wide */ 147 /* BAR 1 */ 148 enum { 149 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */ 150 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */ 151 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */ 152 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */ 153 VMXNET3_REG_CMD = 0x20, /* Command */ 154 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */ 155 VMXNET3_REG_MACH = 0x30, /* MAC Address High */ 156 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */ 157 VMXNET3_REG_ECR = 0x40 /* Event Cause Register */ 158 }; 159 160 /* BAR 0 */ 161 enum { 162 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */ 163 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */ 164 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */ 165 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */ 166 }; 167 168 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ 169 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ 170 171 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 172 #define VMXNET3_REG_ALIGN_MASK 0x7 173 174 /* I/O Mapped access to registers */ 175 #define VMXNET3_IO_TYPE_PT 0 176 #define VMXNET3_IO_TYPE_VD 1 177 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) 178 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24) 179 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) 180 181 enum { 182 VMXNET3_CMD_FIRST_SET = 0xCAFE0000, 183 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, /* 0xCAFE0000 */ 184 VMXNET3_CMD_QUIESCE_DEV, /* 0xCAFE0001 */ 185 VMXNET3_CMD_RESET_DEV, /* 0xCAFE0002 */ 186 VMXNET3_CMD_UPDATE_RX_MODE, /* 0xCAFE0003 */ 187 VMXNET3_CMD_UPDATE_MAC_FILTERS, /* 0xCAFE0004 */ 188 VMXNET3_CMD_UPDATE_VLAN_FILTERS, /* 0xCAFE0005 */ 189 VMXNET3_CMD_UPDATE_RSSIDT, /* 0xCAFE0006 */ 190 VMXNET3_CMD_UPDATE_IML, /* 0xCAFE0007 */ 191 VMXNET3_CMD_UPDATE_PMCFG, /* 0xCAFE0008 */ 192 VMXNET3_CMD_UPDATE_FEATURE, /* 0xCAFE0009 */ 193 VMXNET3_CMD_LOAD_PLUGIN, /* 0xCAFE000A */ 194 195 VMXNET3_CMD_FIRST_GET = 0xF00D0000, 196 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, /* 0xF00D0000 */ 197 VMXNET3_CMD_GET_STATS, /* 0xF00D0001 */ 198 VMXNET3_CMD_GET_LINK, /* 0xF00D0002 */ 199 VMXNET3_CMD_GET_PERM_MAC_LO, /* 0xF00D0003 */ 200 VMXNET3_CMD_GET_PERM_MAC_HI, /* 0xF00D0004 */ 201 VMXNET3_CMD_GET_DID_LO, /* 0xF00D0005 */ 202 VMXNET3_CMD_GET_DID_HI, /* 0xF00D0006 */ 203 VMXNET3_CMD_GET_DEV_EXTRA_INFO, /* 0xF00D0007 */ 204 VMXNET3_CMD_GET_CONF_INTR /* 0xF00D0008 */ 205 }; 206 207 /* 208 * Little Endian layout of bitfields - 209 * Byte 0 : 7.....len.....0 210 * Byte 1 : rsvd gen 13.len.8 211 * Byte 2 : 5.msscof.0 ext1 dtype 212 * Byte 3 : 13...msscof...6 213 * 214 * Big Endian layout of bitfields - 215 * Byte 0: 13...msscof...6 216 * Byte 1 : 5.msscof.0 ext1 dtype 217 * Byte 2 : rsvd gen 13.len.8 218 * Byte 3 : 7.....len.....0 219 * 220 * Thus, le32_to_cpu on the dword will allow the big endian driver to read 221 * the bit fields correctly. And cpu_to_le32 will convert bitfields 222 * bit fields written by big endian driver to format required by device. 223 */ 224 225 struct Vmxnet3_TxDesc { 226 __le64 addr; 227 228 #ifdef __BIG_ENDIAN_BITFIELD 229 u32 msscof:14; /* MSS, checksum offset, flags */ 230 u32 ext1:1; 231 u32 dtype:1; /* descriptor type */ 232 u32 rsvd:1; 233 u32 gen:1; /* generation bit */ 234 u32 len:14; 235 #else 236 u32 len:14; 237 u32 gen:1; /* generation bit */ 238 u32 rsvd:1; 239 u32 dtype:1; /* descriptor type */ 240 u32 ext1:1; 241 u32 msscof:14; /* MSS, checksum offset, flags */ 242 #endif /* __BIG_ENDIAN_BITFIELD */ 243 244 #ifdef __BIG_ENDIAN_BITFIELD 245 u32 tci:16; /* Tag to Insert */ 246 u32 ti:1; /* VLAN Tag Insertion */ 247 u32 ext2:1; 248 u32 cq:1; /* completion request */ 249 u32 eop:1; /* End Of Packet */ 250 u32 om:2; /* offload mode */ 251 u32 hlen:10; /* header len */ 252 #else 253 u32 hlen:10; /* header len */ 254 u32 om:2; /* offload mode */ 255 u32 eop:1; /* End Of Packet */ 256 u32 cq:1; /* completion request */ 257 u32 ext2:1; 258 u32 ti:1; /* VLAN Tag Insertion */ 259 u32 tci:16; /* Tag to Insert */ 260 #endif /* __BIG_ENDIAN_BITFIELD */ 261 }; 262 263 /* TxDesc.OM values */ 264 #define VMXNET3_OM_NONE 0 265 #define VMXNET3_OM_CSUM 2 266 #define VMXNET3_OM_TSO 3 267 268 /* fields in TxDesc we access w/o using bit fields */ 269 #define VMXNET3_TXD_EOP_SHIFT 12 270 #define VMXNET3_TXD_CQ_SHIFT 13 271 #define VMXNET3_TXD_GEN_SHIFT 14 272 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3 273 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2 274 275 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) 276 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) 277 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) 278 279 #define VMXNET3_HDR_COPY_SIZE 128 280 281 282 struct Vmxnet3_TxDataDesc { 283 u8 data[VMXNET3_HDR_COPY_SIZE]; 284 }; 285 286 #define VMXNET3_TCD_GEN_SHIFT 31 287 #define VMXNET3_TCD_GEN_SIZE 1 288 #define VMXNET3_TCD_TXIDX_SHIFT 0 289 #define VMXNET3_TCD_TXIDX_SIZE 12 290 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3 291 292 struct Vmxnet3_TxCompDesc { 293 u32 txdIdx:12; /* Index of the EOP TxDesc */ 294 u32 ext1:20; 295 296 __le32 ext2; 297 __le32 ext3; 298 299 u32 rsvd:24; 300 u32 type:7; /* completion type */ 301 u32 gen:1; /* generation bit */ 302 }; 303 304 struct Vmxnet3_RxDesc { 305 __le64 addr; 306 307 #ifdef __BIG_ENDIAN_BITFIELD 308 u32 gen:1; /* Generation bit */ 309 u32 rsvd:15; 310 u32 dtype:1; /* Descriptor type */ 311 u32 btype:1; /* Buffer Type */ 312 u32 len:14; 313 #else 314 u32 len:14; 315 u32 btype:1; /* Buffer Type */ 316 u32 dtype:1; /* Descriptor type */ 317 u32 rsvd:15; 318 u32 gen:1; /* Generation bit */ 319 #endif 320 u32 ext1; 321 }; 322 323 /* values of RXD.BTYPE */ 324 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ 325 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ 326 327 /* fields in RxDesc we access w/o using bit fields */ 328 #define VMXNET3_RXD_BTYPE_SHIFT 14 329 #define VMXNET3_RXD_GEN_SHIFT 31 330 331 struct Vmxnet3_RxCompDesc { 332 #ifdef __BIG_ENDIAN_BITFIELD 333 u32 ext2:1; 334 u32 cnc:1; /* Checksum Not Calculated */ 335 u32 rssType:4; /* RSS hash type used */ 336 u32 rqID:10; /* rx queue/ring ID */ 337 u32 sop:1; /* Start of Packet */ 338 u32 eop:1; /* End of Packet */ 339 u32 ext1:2; 340 u32 rxdIdx:12; /* Index of the RxDesc */ 341 #else 342 u32 rxdIdx:12; /* Index of the RxDesc */ 343 u32 ext1:2; 344 u32 eop:1; /* End of Packet */ 345 u32 sop:1; /* Start of Packet */ 346 u32 rqID:10; /* rx queue/ring ID */ 347 u32 rssType:4; /* RSS hash type used */ 348 u32 cnc:1; /* Checksum Not Calculated */ 349 u32 ext2:1; 350 #endif /* __BIG_ENDIAN_BITFIELD */ 351 352 __le32 rssHash; /* RSS hash value */ 353 354 #ifdef __BIG_ENDIAN_BITFIELD 355 u32 tci:16; /* Tag stripped */ 356 u32 ts:1; /* Tag is stripped */ 357 u32 err:1; /* Error */ 358 u32 len:14; /* data length */ 359 #else 360 u32 len:14; /* data length */ 361 u32 err:1; /* Error */ 362 u32 ts:1; /* Tag is stripped */ 363 u32 tci:16; /* Tag stripped */ 364 #endif /* __BIG_ENDIAN_BITFIELD */ 365 366 367 #ifdef __BIG_ENDIAN_BITFIELD 368 u32 gen:1; /* generation bit */ 369 u32 type:7; /* completion type */ 370 u32 fcs:1; /* Frame CRC correct */ 371 u32 frg:1; /* IP Fragment */ 372 u32 v4:1; /* IPv4 */ 373 u32 v6:1; /* IPv6 */ 374 u32 ipc:1; /* IP Checksum Correct */ 375 u32 tcp:1; /* TCP packet */ 376 u32 udp:1; /* UDP packet */ 377 u32 tuc:1; /* TCP/UDP Checksum Correct */ 378 u32 csum:16; 379 #else 380 u32 csum:16; 381 u32 tuc:1; /* TCP/UDP Checksum Correct */ 382 u32 udp:1; /* UDP packet */ 383 u32 tcp:1; /* TCP packet */ 384 u32 ipc:1; /* IP Checksum Correct */ 385 u32 v6:1; /* IPv6 */ 386 u32 v4:1; /* IPv4 */ 387 u32 frg:1; /* IP Fragment */ 388 u32 fcs:1; /* Frame CRC correct */ 389 u32 type:7; /* completion type */ 390 u32 gen:1; /* generation bit */ 391 #endif /* __BIG_ENDIAN_BITFIELD */ 392 }; 393 394 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ 395 #define VMXNET3_RCD_TUC_SHIFT 16 396 #define VMXNET3_RCD_IPC_SHIFT 19 397 398 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ 399 #define VMXNET3_RCD_TYPE_SHIFT 56 400 #define VMXNET3_RCD_GEN_SHIFT 63 401 402 /* csum OK for TCP/UDP pkts over IP */ 403 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \ 404 1 << VMXNET3_RCD_IPC_SHIFT) 405 #define VMXNET3_TXD_GEN_SIZE 1 406 #define VMXNET3_TXD_EOP_SIZE 1 407 408 /* value of RxCompDesc.rssType */ 409 enum { 410 VMXNET3_RCD_RSS_TYPE_NONE = 0, 411 VMXNET3_RCD_RSS_TYPE_IPV4 = 1, 412 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2, 413 VMXNET3_RCD_RSS_TYPE_IPV6 = 3, 414 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4, 415 }; 416 417 418 /* a union for accessing all cmd/completion descriptors */ 419 union Vmxnet3_GenericDesc { 420 __le64 qword[2]; 421 __le32 dword[4]; 422 __le16 word[8]; 423 struct Vmxnet3_TxDesc txd; 424 struct Vmxnet3_RxDesc rxd; 425 struct Vmxnet3_TxCompDesc tcd; 426 struct Vmxnet3_RxCompDesc rcd; 427 }; 428 429 #define VMXNET3_INIT_GEN 1 430 431 /* Max size of a single tx buffer */ 432 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) 433 434 /* # of tx desc needed for a tx buffer size */ 435 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \ 436 VMXNET3_MAX_TX_BUF_SIZE) 437 438 /* max # of tx descs for a non-tso pkt */ 439 #define VMXNET3_MAX_TXD_PER_PKT 16 440 441 /* Max size of a single rx buffer */ 442 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) 443 /* Minimum size of a type 0 buffer */ 444 #define VMXNET3_MIN_T0_BUF_SIZE 128 445 #define VMXNET3_MAX_CSUM_OFFSET 1024 446 447 /* Ring base address alignment */ 448 #define VMXNET3_RING_BA_ALIGN 512 449 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) 450 451 /* Ring size must be a multiple of 32 */ 452 #define VMXNET3_RING_SIZE_ALIGN 32 453 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) 454 455 /* Max ring size */ 456 #define VMXNET3_TX_RING_MAX_SIZE 4096 457 #define VMXNET3_TC_RING_MAX_SIZE 4096 458 #define VMXNET3_RX_RING_MAX_SIZE 4096 459 #define VMXNET3_RC_RING_MAX_SIZE 8192 460 461 /* a list of reasons for queue stop */ 462 463 enum { 464 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */ 465 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */ 466 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */ 467 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */ 468 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */ 469 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */ 470 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */ 471 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */ 472 }; 473 474 /* completion descriptor types */ 475 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ 476 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ 477 478 enum { 479 VMXNET3_GOS_BITS_UNK = 0, /* unknown */ 480 VMXNET3_GOS_BITS_32 = 1, 481 VMXNET3_GOS_BITS_64 = 2, 482 }; 483 484 #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */ 485 #define VMXNET3_GOS_TYPE_LINUX 1 486 #define VMXNET3_GOS_TYPE_WIN 2 487 #define VMXNET3_GOS_TYPE_SOLARIS 3 488 #define VMXNET3_GOS_TYPE_FREEBSD 4 489 #define VMXNET3_GOS_TYPE_PXE 5 490 491 struct Vmxnet3_GOSInfo { 492 #ifdef __BIG_ENDIAN_BITFIELD 493 u32 gosMisc:10; /* other info about gos */ 494 u32 gosVer:16; /* gos version */ 495 u32 gosType:4; /* which guest */ 496 u32 gosBits:2; /* 32-bit or 64-bit? */ 497 #else 498 u32 gosBits:2; /* 32-bit or 64-bit? */ 499 u32 gosType:4; /* which guest */ 500 u32 gosVer:16; /* gos version */ 501 u32 gosMisc:10; /* other info about gos */ 502 #endif /* __BIG_ENDIAN_BITFIELD */ 503 }; 504 505 struct Vmxnet3_DriverInfo { 506 __le32 version; 507 struct Vmxnet3_GOSInfo gos; 508 __le32 vmxnet3RevSpt; 509 __le32 uptVerSpt; 510 }; 511 512 513 #define VMXNET3_REV1_MAGIC 0xbabefee1 514 515 /* 516 * QueueDescPA must be 128 bytes aligned. It points to an array of 517 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. 518 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by 519 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. 520 */ 521 #define VMXNET3_QUEUE_DESC_ALIGN 128 522 523 524 struct Vmxnet3_MiscConf { 525 struct Vmxnet3_DriverInfo driverInfo; 526 __le64 uptFeatures; 527 __le64 ddPA; /* driver data PA */ 528 __le64 queueDescPA; /* queue descriptor table PA */ 529 __le32 ddLen; /* driver data len */ 530 __le32 queueDescLen; /* queue desc. table len in bytes */ 531 __le32 mtu; 532 __le16 maxNumRxSG; 533 u8 numTxQueues; 534 u8 numRxQueues; 535 __le32 reserved[4]; 536 }; 537 538 539 struct Vmxnet3_TxQueueConf { 540 __le64 txRingBasePA; 541 __le64 dataRingBasePA; 542 __le64 compRingBasePA; 543 __le64 ddPA; /* driver data */ 544 __le64 reserved; 545 __le32 txRingSize; /* # of tx desc */ 546 __le32 dataRingSize; /* # of data desc */ 547 __le32 compRingSize; /* # of comp desc */ 548 __le32 ddLen; /* size of driver data */ 549 u8 intrIdx; 550 u8 _pad[7]; 551 }; 552 553 554 struct Vmxnet3_RxQueueConf { 555 __le64 rxRingBasePA[2]; 556 __le64 compRingBasePA; 557 __le64 ddPA; /* driver data */ 558 __le64 reserved; 559 __le32 rxRingSize[2]; /* # of rx desc */ 560 __le32 compRingSize; /* # of rx comp desc */ 561 __le32 ddLen; /* size of driver data */ 562 u8 intrIdx; 563 u8 _pad[7]; 564 }; 565 566 567 enum vmxnet3_intr_mask_mode { 568 VMXNET3_IMM_AUTO = 0, 569 VMXNET3_IMM_ACTIVE = 1, 570 VMXNET3_IMM_LAZY = 2 571 }; 572 573 enum vmxnet3_intr_type { 574 VMXNET3_IT_AUTO = 0, 575 VMXNET3_IT_INTX = 1, 576 VMXNET3_IT_MSI = 2, 577 VMXNET3_IT_MSIX = 3 578 }; 579 580 #define VMXNET3_MAX_TX_QUEUES 8 581 #define VMXNET3_MAX_RX_QUEUES 16 582 /* addition 1 for events */ 583 #define VMXNET3_MAX_INTRS 25 584 585 /* value of intrCtrl */ 586 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ 587 588 589 struct Vmxnet3_IntrConf { 590 bool autoMask; 591 u8 numIntrs; /* # of interrupts */ 592 u8 eventIntrIdx; 593 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for 594 * each intr */ 595 __le32 intrCtrl; 596 __le32 reserved[2]; 597 }; 598 599 /* one bit per VLAN ID, the size is in the units of u32 */ 600 #define VMXNET3_VFT_SIZE (4096/(sizeof(uint32_t)*8)) 601 602 603 struct Vmxnet3_QueueStatus { 604 bool stopped; 605 u8 _pad[3]; 606 __le32 error; 607 }; 608 609 610 struct Vmxnet3_TxQueueCtrl { 611 __le32 txNumDeferred; 612 __le32 txThreshold; 613 __le64 reserved; 614 }; 615 616 617 struct Vmxnet3_RxQueueCtrl { 618 bool updateRxProd; 619 u8 _pad[7]; 620 __le64 reserved; 621 }; 622 623 enum { 624 VMXNET3_RXM_UCAST = 0x01, /* unicast only */ 625 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */ 626 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */ 627 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */ 628 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */ 629 }; 630 631 struct Vmxnet3_RxFilterConf { 632 __le32 rxMode; /* VMXNET3_RXM_xxx */ 633 __le16 mfTableLen; /* size of the multicast filter table */ 634 __le16 _pad1; 635 __le64 mfTablePA; /* PA of the multicast filters table */ 636 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ 637 }; 638 639 640 #define VMXNET3_PM_MAX_FILTERS 6 641 #define VMXNET3_PM_MAX_PATTERN_SIZE 128 642 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) 643 644 #define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */ 645 #define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching 646 * filters */ 647 648 649 struct Vmxnet3_PM_PktFilter { 650 u8 maskSize; 651 u8 patternSize; 652 u8 mask[VMXNET3_PM_MAX_MASK_SIZE]; 653 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; 654 u8 pad[6]; 655 }; 656 657 658 struct Vmxnet3_PMConf { 659 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ 660 u8 numFilters; 661 u8 pad[5]; 662 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; 663 }; 664 665 666 struct Vmxnet3_VariableLenConfDesc { 667 __le32 confVer; 668 __le32 confLen; 669 __le64 confPA; 670 }; 671 672 673 struct Vmxnet3_TxQueueDesc { 674 struct Vmxnet3_TxQueueCtrl ctrl; 675 struct Vmxnet3_TxQueueConf conf; 676 677 /* Driver read after a GET command */ 678 struct Vmxnet3_QueueStatus status; 679 struct UPT1_TxStats stats; 680 u8 _pad[88]; /* 128 aligned */ 681 }; 682 683 684 struct Vmxnet3_RxQueueDesc { 685 struct Vmxnet3_RxQueueCtrl ctrl; 686 struct Vmxnet3_RxQueueConf conf; 687 /* Driver read after a GET commad */ 688 struct Vmxnet3_QueueStatus status; 689 struct UPT1_RxStats stats; 690 u8 __pad[88]; /* 128 aligned */ 691 }; 692 693 694 struct Vmxnet3_DSDevRead { 695 /* read-only region for device, read by dev in response to a SET cmd */ 696 struct Vmxnet3_MiscConf misc; 697 struct Vmxnet3_IntrConf intrConf; 698 struct Vmxnet3_RxFilterConf rxFilterConf; 699 struct Vmxnet3_VariableLenConfDesc rssConfDesc; 700 struct Vmxnet3_VariableLenConfDesc pmConfDesc; 701 struct Vmxnet3_VariableLenConfDesc pluginConfDesc; 702 }; 703 704 /* All structures in DriverShared are padded to multiples of 8 bytes */ 705 struct Vmxnet3_DriverShared { 706 __le32 magic; 707 /* make devRead start at 64bit boundaries */ 708 __le32 pad; 709 struct Vmxnet3_DSDevRead devRead; 710 __le32 ecr; 711 __le32 reserved[5]; 712 }; 713 714 715 #define VMXNET3_ECR_RQERR (1 << 0) 716 #define VMXNET3_ECR_TQERR (1 << 1) 717 #define VMXNET3_ECR_LINK (1 << 2) 718 #define VMXNET3_ECR_DIC (1 << 3) 719 #define VMXNET3_ECR_DEBUG (1 << 4) 720 721 /* flip the gen bit of a ring */ 722 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) 723 724 /* only use this if moving the idx won't affect the gen bit */ 725 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \ 726 do {\ 727 (idx)++;\ 728 if (unlikely((idx) == (ring_size))) {\ 729 (idx) = 0;\ 730 } \ 731 } while (0) 732 733 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ 734 (vfTable[vid >> 5] |= (1 << (vid & 31))) 735 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ 736 (vfTable[vid >> 5] &= ~(1 << (vid & 31))) 737 738 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ 739 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) 740 741 #define VMXNET3_MAX_MTU 9000 742 #define VMXNET3_MIN_MTU 60 743 744 #define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */ 745 #define VMXNET3_LINK_DOWN 0 746 747 #undef u64 748 #undef u32 749 #undef u16 750 #undef u8 751 #undef __le16 752 #undef __le32 753 #undef __le64 754 #undef __packed 755 #undef const_cpu_to_le64 756 #if defined(HOST_WORDS_BIGENDIAN) 757 #undef __BIG_ENDIAN_BITFIELD 758 #endif 759 760 #endif 761