1 /* 2 * QEMU VMWARE VMXNET3 paravirtual NIC interface definitions 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: 9 * Dmitry Fleytman <dmitry@daynix.com> 10 * Tamir Shomer <tamirs@daynix.com> 11 * Yan Vugenfirer <yan@daynix.com> 12 * 13 * This work is licensed under the terms of the GNU GPL, version 2. 14 * See the COPYING file in the top-level directory. 15 * 16 */ 17 18 #ifndef _QEMU_VMXNET3_H 19 #define _QEMU_VMXNET3_H 20 21 #define VMXNET3_DEVICE_MAX_TX_QUEUES 8 22 #define VMXNET3_DEVICE_MAX_RX_QUEUES 8 /* Keep this value as a power of 2 */ 23 24 /* 25 * VMWARE headers we got from Linux kernel do not fully comply QEMU coding 26 * standards in sense of types and defines used. 27 * Since we didn't want to change VMWARE code, following set of typedefs 28 * and defines needed to compile these headers with QEMU introduced. 29 */ 30 #define u64 uint64_t 31 #define u32 uint32_t 32 #define u16 uint16_t 33 #define u8 uint8_t 34 #define __le16 uint16_t 35 #define __le32 uint32_t 36 #define __le64 uint64_t 37 #define __packed QEMU_PACKED 38 39 #if defined(HOST_WORDS_BIGENDIAN) 40 #define __BIG_ENDIAN_BITFIELD 41 #else 42 #endif 43 44 /* 45 * Following is an interface definition for 46 * VMXNET3 device as provided by VMWARE 47 * See original copyright from Linux kernel v3.2.8 48 * header file drivers/net/vmxnet3/vmxnet3_defs.h below. 49 */ 50 51 /* 52 * Linux driver for VMware's vmxnet3 ethernet NIC. 53 * 54 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved. 55 * 56 * This program is free software; you can redistribute it and/or modify it 57 * under the terms of the GNU General Public License as published by the 58 * Free Software Foundation; version 2 of the License and no later version. 59 * 60 * This program is distributed in the hope that it will be useful, but 61 * WITHOUT ANY WARRANTY; without even the implied warranty of 62 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 63 * NON INFRINGEMENT. See the GNU General Public License for more 64 * details. 65 * 66 * You should have received a copy of the GNU General Public License 67 * along with this program; if not, write to the Free Software 68 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 69 * 70 * The full GNU General Public License is included in this distribution in 71 * the file called "COPYING". 72 * 73 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com> 74 * 75 */ 76 77 struct UPT1_TxStats { 78 u64 TSOPktsTxOK; /* TSO pkts post-segmentation */ 79 u64 TSOBytesTxOK; 80 u64 ucastPktsTxOK; 81 u64 ucastBytesTxOK; 82 u64 mcastPktsTxOK; 83 u64 mcastBytesTxOK; 84 u64 bcastPktsTxOK; 85 u64 bcastBytesTxOK; 86 u64 pktsTxError; 87 u64 pktsTxDiscard; 88 }; 89 90 struct UPT1_RxStats { 91 u64 LROPktsRxOK; /* LRO pkts */ 92 u64 LROBytesRxOK; /* bytes from LRO pkts */ 93 /* the following counters are for pkts from the wire, i.e., pre-LRO */ 94 u64 ucastPktsRxOK; 95 u64 ucastBytesRxOK; 96 u64 mcastPktsRxOK; 97 u64 mcastBytesRxOK; 98 u64 bcastPktsRxOK; 99 u64 bcastBytesRxOK; 100 u64 pktsRxOutOfBuf; 101 u64 pktsRxError; 102 }; 103 104 /* interrupt moderation level */ 105 enum { 106 UPT1_IML_NONE = 0, /* no interrupt moderation */ 107 UPT1_IML_HIGHEST = 7, /* least intr generated */ 108 UPT1_IML_ADAPTIVE = 8, /* adpative intr moderation */ 109 }; 110 /* values for UPT1_RSSConf.hashFunc */ 111 enum { 112 UPT1_RSS_HASH_TYPE_NONE = 0x0, 113 UPT1_RSS_HASH_TYPE_IPV4 = 0x01, 114 UPT1_RSS_HASH_TYPE_TCP_IPV4 = 0x02, 115 UPT1_RSS_HASH_TYPE_IPV6 = 0x04, 116 UPT1_RSS_HASH_TYPE_TCP_IPV6 = 0x08, 117 }; 118 119 enum { 120 UPT1_RSS_HASH_FUNC_NONE = 0x0, 121 UPT1_RSS_HASH_FUNC_TOEPLITZ = 0x01, 122 }; 123 124 #define UPT1_RSS_MAX_KEY_SIZE 40 125 #define UPT1_RSS_MAX_IND_TABLE_SIZE 128 126 127 struct UPT1_RSSConf { 128 u16 hashType; 129 u16 hashFunc; 130 u16 hashKeySize; 131 u16 indTableSize; 132 u8 hashKey[UPT1_RSS_MAX_KEY_SIZE]; 133 u8 indTable[UPT1_RSS_MAX_IND_TABLE_SIZE]; 134 }; 135 136 /* features */ 137 enum { 138 UPT1_F_RXCSUM = 0x0001, /* rx csum verification */ 139 UPT1_F_RSS = 0x0002, 140 UPT1_F_RXVLAN = 0x0004, /* VLAN tag stripping */ 141 UPT1_F_LRO = 0x0008, 142 }; 143 144 /* all registers are 32 bit wide */ 145 /* BAR 1 */ 146 enum { 147 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */ 148 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */ 149 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */ 150 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */ 151 VMXNET3_REG_CMD = 0x20, /* Command */ 152 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */ 153 VMXNET3_REG_MACH = 0x30, /* MAC Address High */ 154 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */ 155 VMXNET3_REG_ECR = 0x40 /* Event Cause Register */ 156 }; 157 158 /* BAR 0 */ 159 enum { 160 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */ 161 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */ 162 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */ 163 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */ 164 }; 165 166 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ 167 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ 168 169 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 170 #define VMXNET3_REG_ALIGN_MASK 0x7 171 172 /* I/O Mapped access to registers */ 173 #define VMXNET3_IO_TYPE_PT 0 174 #define VMXNET3_IO_TYPE_VD 1 175 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) 176 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24) 177 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) 178 179 enum { 180 VMXNET3_CMD_FIRST_SET = 0xCAFE0000, 181 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, /* 0xCAFE0000 */ 182 VMXNET3_CMD_QUIESCE_DEV, /* 0xCAFE0001 */ 183 VMXNET3_CMD_RESET_DEV, /* 0xCAFE0002 */ 184 VMXNET3_CMD_UPDATE_RX_MODE, /* 0xCAFE0003 */ 185 VMXNET3_CMD_UPDATE_MAC_FILTERS, /* 0xCAFE0004 */ 186 VMXNET3_CMD_UPDATE_VLAN_FILTERS, /* 0xCAFE0005 */ 187 VMXNET3_CMD_UPDATE_RSSIDT, /* 0xCAFE0006 */ 188 VMXNET3_CMD_UPDATE_IML, /* 0xCAFE0007 */ 189 VMXNET3_CMD_UPDATE_PMCFG, /* 0xCAFE0008 */ 190 VMXNET3_CMD_UPDATE_FEATURE, /* 0xCAFE0009 */ 191 VMXNET3_CMD_LOAD_PLUGIN, /* 0xCAFE000A */ 192 193 VMXNET3_CMD_FIRST_GET = 0xF00D0000, 194 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, /* 0xF00D0000 */ 195 VMXNET3_CMD_GET_STATS, /* 0xF00D0001 */ 196 VMXNET3_CMD_GET_LINK, /* 0xF00D0002 */ 197 VMXNET3_CMD_GET_PERM_MAC_LO, /* 0xF00D0003 */ 198 VMXNET3_CMD_GET_PERM_MAC_HI, /* 0xF00D0004 */ 199 VMXNET3_CMD_GET_DID_LO, /* 0xF00D0005 */ 200 VMXNET3_CMD_GET_DID_HI, /* 0xF00D0006 */ 201 VMXNET3_CMD_GET_DEV_EXTRA_INFO, /* 0xF00D0007 */ 202 VMXNET3_CMD_GET_CONF_INTR /* 0xF00D0008 */ 203 }; 204 205 /* 206 * Little Endian layout of bitfields - 207 * Byte 0 : 7.....len.....0 208 * Byte 1 : rsvd gen 13.len.8 209 * Byte 2 : 5.msscof.0 ext1 dtype 210 * Byte 3 : 13...msscof...6 211 * 212 * Big Endian layout of bitfields - 213 * Byte 0: 13...msscof...6 214 * Byte 1 : 5.msscof.0 ext1 dtype 215 * Byte 2 : rsvd gen 13.len.8 216 * Byte 3 : 7.....len.....0 217 * 218 * Thus, le32_to_cpu on the dword will allow the big endian driver to read 219 * the bit fields correctly. And cpu_to_le32 will convert bitfields 220 * bit fields written by big endian driver to format required by device. 221 */ 222 223 struct Vmxnet3_TxDesc { 224 __le64 addr; 225 226 #ifdef __BIG_ENDIAN_BITFIELD 227 u32 msscof:14; /* MSS, checksum offset, flags */ 228 u32 ext1:1; 229 u32 dtype:1; /* descriptor type */ 230 u32 rsvd:1; 231 u32 gen:1; /* generation bit */ 232 u32 len:14; 233 #else 234 u32 len:14; 235 u32 gen:1; /* generation bit */ 236 u32 rsvd:1; 237 u32 dtype:1; /* descriptor type */ 238 u32 ext1:1; 239 u32 msscof:14; /* MSS, checksum offset, flags */ 240 #endif /* __BIG_ENDIAN_BITFIELD */ 241 242 #ifdef __BIG_ENDIAN_BITFIELD 243 u32 tci:16; /* Tag to Insert */ 244 u32 ti:1; /* VLAN Tag Insertion */ 245 u32 ext2:1; 246 u32 cq:1; /* completion request */ 247 u32 eop:1; /* End Of Packet */ 248 u32 om:2; /* offload mode */ 249 u32 hlen:10; /* header len */ 250 #else 251 u32 hlen:10; /* header len */ 252 u32 om:2; /* offload mode */ 253 u32 eop:1; /* End Of Packet */ 254 u32 cq:1; /* completion request */ 255 u32 ext2:1; 256 u32 ti:1; /* VLAN Tag Insertion */ 257 u32 tci:16; /* Tag to Insert */ 258 #endif /* __BIG_ENDIAN_BITFIELD */ 259 }; 260 261 /* TxDesc.OM values */ 262 #define VMXNET3_OM_NONE 0 263 #define VMXNET3_OM_CSUM 2 264 #define VMXNET3_OM_TSO 3 265 266 /* fields in TxDesc we access w/o using bit fields */ 267 #define VMXNET3_TXD_EOP_SHIFT 12 268 #define VMXNET3_TXD_CQ_SHIFT 13 269 #define VMXNET3_TXD_GEN_SHIFT 14 270 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3 271 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2 272 273 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) 274 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) 275 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) 276 277 #define VMXNET3_HDR_COPY_SIZE 128 278 279 280 struct Vmxnet3_TxDataDesc { 281 u8 data[VMXNET3_HDR_COPY_SIZE]; 282 }; 283 284 #define VMXNET3_TCD_GEN_SHIFT 31 285 #define VMXNET3_TCD_GEN_SIZE 1 286 #define VMXNET3_TCD_TXIDX_SHIFT 0 287 #define VMXNET3_TCD_TXIDX_SIZE 12 288 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3 289 290 struct Vmxnet3_TxCompDesc { 291 u32 txdIdx:12; /* Index of the EOP TxDesc */ 292 u32 ext1:20; 293 294 __le32 ext2; 295 __le32 ext3; 296 297 u32 rsvd:24; 298 u32 type:7; /* completion type */ 299 u32 gen:1; /* generation bit */ 300 }; 301 302 struct Vmxnet3_RxDesc { 303 __le64 addr; 304 305 #ifdef __BIG_ENDIAN_BITFIELD 306 u32 gen:1; /* Generation bit */ 307 u32 rsvd:15; 308 u32 dtype:1; /* Descriptor type */ 309 u32 btype:1; /* Buffer Type */ 310 u32 len:14; 311 #else 312 u32 len:14; 313 u32 btype:1; /* Buffer Type */ 314 u32 dtype:1; /* Descriptor type */ 315 u32 rsvd:15; 316 u32 gen:1; /* Generation bit */ 317 #endif 318 u32 ext1; 319 }; 320 321 /* values of RXD.BTYPE */ 322 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ 323 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ 324 325 /* fields in RxDesc we access w/o using bit fields */ 326 #define VMXNET3_RXD_BTYPE_SHIFT 14 327 #define VMXNET3_RXD_GEN_SHIFT 31 328 329 struct Vmxnet3_RxCompDesc { 330 #ifdef __BIG_ENDIAN_BITFIELD 331 u32 ext2:1; 332 u32 cnc:1; /* Checksum Not Calculated */ 333 u32 rssType:4; /* RSS hash type used */ 334 u32 rqID:10; /* rx queue/ring ID */ 335 u32 sop:1; /* Start of Packet */ 336 u32 eop:1; /* End of Packet */ 337 u32 ext1:2; 338 u32 rxdIdx:12; /* Index of the RxDesc */ 339 #else 340 u32 rxdIdx:12; /* Index of the RxDesc */ 341 u32 ext1:2; 342 u32 eop:1; /* End of Packet */ 343 u32 sop:1; /* Start of Packet */ 344 u32 rqID:10; /* rx queue/ring ID */ 345 u32 rssType:4; /* RSS hash type used */ 346 u32 cnc:1; /* Checksum Not Calculated */ 347 u32 ext2:1; 348 #endif /* __BIG_ENDIAN_BITFIELD */ 349 350 __le32 rssHash; /* RSS hash value */ 351 352 #ifdef __BIG_ENDIAN_BITFIELD 353 u32 tci:16; /* Tag stripped */ 354 u32 ts:1; /* Tag is stripped */ 355 u32 err:1; /* Error */ 356 u32 len:14; /* data length */ 357 #else 358 u32 len:14; /* data length */ 359 u32 err:1; /* Error */ 360 u32 ts:1; /* Tag is stripped */ 361 u32 tci:16; /* Tag stripped */ 362 #endif /* __BIG_ENDIAN_BITFIELD */ 363 364 365 #ifdef __BIG_ENDIAN_BITFIELD 366 u32 gen:1; /* generation bit */ 367 u32 type:7; /* completion type */ 368 u32 fcs:1; /* Frame CRC correct */ 369 u32 frg:1; /* IP Fragment */ 370 u32 v4:1; /* IPv4 */ 371 u32 v6:1; /* IPv6 */ 372 u32 ipc:1; /* IP Checksum Correct */ 373 u32 tcp:1; /* TCP packet */ 374 u32 udp:1; /* UDP packet */ 375 u32 tuc:1; /* TCP/UDP Checksum Correct */ 376 u32 csum:16; 377 #else 378 u32 csum:16; 379 u32 tuc:1; /* TCP/UDP Checksum Correct */ 380 u32 udp:1; /* UDP packet */ 381 u32 tcp:1; /* TCP packet */ 382 u32 ipc:1; /* IP Checksum Correct */ 383 u32 v6:1; /* IPv6 */ 384 u32 v4:1; /* IPv4 */ 385 u32 frg:1; /* IP Fragment */ 386 u32 fcs:1; /* Frame CRC correct */ 387 u32 type:7; /* completion type */ 388 u32 gen:1; /* generation bit */ 389 #endif /* __BIG_ENDIAN_BITFIELD */ 390 }; 391 392 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ 393 #define VMXNET3_RCD_TUC_SHIFT 16 394 #define VMXNET3_RCD_IPC_SHIFT 19 395 396 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ 397 #define VMXNET3_RCD_TYPE_SHIFT 56 398 #define VMXNET3_RCD_GEN_SHIFT 63 399 400 /* csum OK for TCP/UDP pkts over IP */ 401 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \ 402 1 << VMXNET3_RCD_IPC_SHIFT) 403 #define VMXNET3_TXD_GEN_SIZE 1 404 #define VMXNET3_TXD_EOP_SIZE 1 405 406 /* value of RxCompDesc.rssType */ 407 enum { 408 VMXNET3_RCD_RSS_TYPE_NONE = 0, 409 VMXNET3_RCD_RSS_TYPE_IPV4 = 1, 410 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2, 411 VMXNET3_RCD_RSS_TYPE_IPV6 = 3, 412 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4, 413 }; 414 415 416 /* a union for accessing all cmd/completion descriptors */ 417 union Vmxnet3_GenericDesc { 418 __le64 qword[2]; 419 __le32 dword[4]; 420 __le16 word[8]; 421 struct Vmxnet3_TxDesc txd; 422 struct Vmxnet3_RxDesc rxd; 423 struct Vmxnet3_TxCompDesc tcd; 424 struct Vmxnet3_RxCompDesc rcd; 425 }; 426 427 #define VMXNET3_INIT_GEN 1 428 429 /* Max size of a single tx buffer */ 430 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) 431 432 /* # of tx desc needed for a tx buffer size */ 433 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \ 434 VMXNET3_MAX_TX_BUF_SIZE) 435 436 /* max # of tx descs for a non-tso pkt */ 437 #define VMXNET3_MAX_TXD_PER_PKT 16 438 439 /* Max size of a single rx buffer */ 440 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) 441 /* Minimum size of a type 0 buffer */ 442 #define VMXNET3_MIN_T0_BUF_SIZE 128 443 #define VMXNET3_MAX_CSUM_OFFSET 1024 444 445 /* Ring base address alignment */ 446 #define VMXNET3_RING_BA_ALIGN 512 447 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) 448 449 /* Ring size must be a multiple of 32 */ 450 #define VMXNET3_RING_SIZE_ALIGN 32 451 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) 452 453 /* Max ring size */ 454 #define VMXNET3_TX_RING_MAX_SIZE 4096 455 #define VMXNET3_TC_RING_MAX_SIZE 4096 456 #define VMXNET3_RX_RING_MAX_SIZE 4096 457 #define VMXNET3_RC_RING_MAX_SIZE 8192 458 459 /* a list of reasons for queue stop */ 460 461 enum { 462 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */ 463 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */ 464 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */ 465 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */ 466 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */ 467 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */ 468 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */ 469 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */ 470 }; 471 472 /* completion descriptor types */ 473 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ 474 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ 475 476 enum { 477 VMXNET3_GOS_BITS_UNK = 0, /* unknown */ 478 VMXNET3_GOS_BITS_32 = 1, 479 VMXNET3_GOS_BITS_64 = 2, 480 }; 481 482 #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */ 483 #define VMXNET3_GOS_TYPE_LINUX 1 484 #define VMXNET3_GOS_TYPE_WIN 2 485 #define VMXNET3_GOS_TYPE_SOLARIS 3 486 #define VMXNET3_GOS_TYPE_FREEBSD 4 487 #define VMXNET3_GOS_TYPE_PXE 5 488 489 struct Vmxnet3_GOSInfo { 490 #ifdef __BIG_ENDIAN_BITFIELD 491 u32 gosMisc:10; /* other info about gos */ 492 u32 gosVer:16; /* gos version */ 493 u32 gosType:4; /* which guest */ 494 u32 gosBits:2; /* 32-bit or 64-bit? */ 495 #else 496 u32 gosBits:2; /* 32-bit or 64-bit? */ 497 u32 gosType:4; /* which guest */ 498 u32 gosVer:16; /* gos version */ 499 u32 gosMisc:10; /* other info about gos */ 500 #endif /* __BIG_ENDIAN_BITFIELD */ 501 }; 502 503 struct Vmxnet3_DriverInfo { 504 __le32 version; 505 struct Vmxnet3_GOSInfo gos; 506 __le32 vmxnet3RevSpt; 507 __le32 uptVerSpt; 508 }; 509 510 511 #define VMXNET3_REV1_MAGIC 0xbabefee1 512 513 /* 514 * QueueDescPA must be 128 bytes aligned. It points to an array of 515 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. 516 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by 517 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. 518 */ 519 #define VMXNET3_QUEUE_DESC_ALIGN 128 520 521 522 struct Vmxnet3_MiscConf { 523 struct Vmxnet3_DriverInfo driverInfo; 524 __le64 uptFeatures; 525 __le64 ddPA; /* driver data PA */ 526 __le64 queueDescPA; /* queue descriptor table PA */ 527 __le32 ddLen; /* driver data len */ 528 __le32 queueDescLen; /* queue desc. table len in bytes */ 529 __le32 mtu; 530 __le16 maxNumRxSG; 531 u8 numTxQueues; 532 u8 numRxQueues; 533 __le32 reserved[4]; 534 }; 535 536 537 struct Vmxnet3_TxQueueConf { 538 __le64 txRingBasePA; 539 __le64 dataRingBasePA; 540 __le64 compRingBasePA; 541 __le64 ddPA; /* driver data */ 542 __le64 reserved; 543 __le32 txRingSize; /* # of tx desc */ 544 __le32 dataRingSize; /* # of data desc */ 545 __le32 compRingSize; /* # of comp desc */ 546 __le32 ddLen; /* size of driver data */ 547 u8 intrIdx; 548 u8 _pad[7]; 549 }; 550 551 552 struct Vmxnet3_RxQueueConf { 553 __le64 rxRingBasePA[2]; 554 __le64 compRingBasePA; 555 __le64 ddPA; /* driver data */ 556 __le64 reserved; 557 __le32 rxRingSize[2]; /* # of rx desc */ 558 __le32 compRingSize; /* # of rx comp desc */ 559 __le32 ddLen; /* size of driver data */ 560 u8 intrIdx; 561 u8 _pad[7]; 562 }; 563 564 565 enum vmxnet3_intr_mask_mode { 566 VMXNET3_IMM_AUTO = 0, 567 VMXNET3_IMM_ACTIVE = 1, 568 VMXNET3_IMM_LAZY = 2 569 }; 570 571 enum vmxnet3_intr_type { 572 VMXNET3_IT_AUTO = 0, 573 VMXNET3_IT_INTX = 1, 574 VMXNET3_IT_MSI = 2, 575 VMXNET3_IT_MSIX = 3 576 }; 577 578 #define VMXNET3_MAX_TX_QUEUES 8 579 #define VMXNET3_MAX_RX_QUEUES 16 580 /* addition 1 for events */ 581 #define VMXNET3_MAX_INTRS 25 582 583 /* value of intrCtrl */ 584 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ 585 586 587 struct Vmxnet3_IntrConf { 588 bool autoMask; 589 u8 numIntrs; /* # of interrupts */ 590 u8 eventIntrIdx; 591 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for 592 * each intr */ 593 __le32 intrCtrl; 594 __le32 reserved[2]; 595 }; 596 597 /* one bit per VLAN ID, the size is in the units of u32 */ 598 #define VMXNET3_VFT_SIZE (4096/(sizeof(uint32_t)*8)) 599 600 601 struct Vmxnet3_QueueStatus { 602 bool stopped; 603 u8 _pad[3]; 604 __le32 error; 605 }; 606 607 608 struct Vmxnet3_TxQueueCtrl { 609 __le32 txNumDeferred; 610 __le32 txThreshold; 611 __le64 reserved; 612 }; 613 614 615 struct Vmxnet3_RxQueueCtrl { 616 bool updateRxProd; 617 u8 _pad[7]; 618 __le64 reserved; 619 }; 620 621 enum { 622 VMXNET3_RXM_UCAST = 0x01, /* unicast only */ 623 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */ 624 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */ 625 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */ 626 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */ 627 }; 628 629 struct Vmxnet3_RxFilterConf { 630 __le32 rxMode; /* VMXNET3_RXM_xxx */ 631 __le16 mfTableLen; /* size of the multicast filter table */ 632 __le16 _pad1; 633 __le64 mfTablePA; /* PA of the multicast filters table */ 634 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ 635 }; 636 637 638 #define VMXNET3_PM_MAX_FILTERS 6 639 #define VMXNET3_PM_MAX_PATTERN_SIZE 128 640 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) 641 642 #define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */ 643 #define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching 644 * filters */ 645 646 647 struct Vmxnet3_PM_PktFilter { 648 u8 maskSize; 649 u8 patternSize; 650 u8 mask[VMXNET3_PM_MAX_MASK_SIZE]; 651 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; 652 u8 pad[6]; 653 }; 654 655 656 struct Vmxnet3_PMConf { 657 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ 658 u8 numFilters; 659 u8 pad[5]; 660 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; 661 }; 662 663 664 struct Vmxnet3_VariableLenConfDesc { 665 __le32 confVer; 666 __le32 confLen; 667 __le64 confPA; 668 }; 669 670 671 struct Vmxnet3_TxQueueDesc { 672 struct Vmxnet3_TxQueueCtrl ctrl; 673 struct Vmxnet3_TxQueueConf conf; 674 675 /* Driver read after a GET command */ 676 struct Vmxnet3_QueueStatus status; 677 struct UPT1_TxStats stats; 678 u8 _pad[88]; /* 128 aligned */ 679 }; 680 681 682 struct Vmxnet3_RxQueueDesc { 683 struct Vmxnet3_RxQueueCtrl ctrl; 684 struct Vmxnet3_RxQueueConf conf; 685 /* Driver read after a GET commad */ 686 struct Vmxnet3_QueueStatus status; 687 struct UPT1_RxStats stats; 688 u8 __pad[88]; /* 128 aligned */ 689 }; 690 691 692 struct Vmxnet3_DSDevRead { 693 /* read-only region for device, read by dev in response to a SET cmd */ 694 struct Vmxnet3_MiscConf misc; 695 struct Vmxnet3_IntrConf intrConf; 696 struct Vmxnet3_RxFilterConf rxFilterConf; 697 struct Vmxnet3_VariableLenConfDesc rssConfDesc; 698 struct Vmxnet3_VariableLenConfDesc pmConfDesc; 699 struct Vmxnet3_VariableLenConfDesc pluginConfDesc; 700 }; 701 702 /* All structures in DriverShared are padded to multiples of 8 bytes */ 703 struct Vmxnet3_DriverShared { 704 __le32 magic; 705 /* make devRead start at 64bit boundaries */ 706 __le32 pad; 707 struct Vmxnet3_DSDevRead devRead; 708 __le32 ecr; 709 __le32 reserved[5]; 710 }; 711 712 713 #define VMXNET3_ECR_RQERR (1 << 0) 714 #define VMXNET3_ECR_TQERR (1 << 1) 715 #define VMXNET3_ECR_LINK (1 << 2) 716 #define VMXNET3_ECR_DIC (1 << 3) 717 #define VMXNET3_ECR_DEBUG (1 << 4) 718 719 /* flip the gen bit of a ring */ 720 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) 721 722 /* only use this if moving the idx won't affect the gen bit */ 723 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \ 724 do {\ 725 (idx)++;\ 726 if (unlikely((idx) == (ring_size))) {\ 727 (idx) = 0;\ 728 } \ 729 } while (0) 730 731 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ 732 (vfTable[vid >> 5] |= (1 << (vid & 31))) 733 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ 734 (vfTable[vid >> 5] &= ~(1 << (vid & 31))) 735 736 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ 737 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) 738 739 #define VMXNET3_MAX_MTU 9000 740 #define VMXNET3_MIN_MTU 60 741 742 #define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */ 743 #define VMXNET3_LINK_DOWN 0 744 745 #undef u64 746 #undef u32 747 #undef u16 748 #undef u8 749 #undef __le16 750 #undef __le32 751 #undef __le64 752 #undef __packed 753 #if defined(HOST_WORDS_BIGENDIAN) 754 #undef __BIG_ENDIAN_BITFIELD 755 #endif 756 757 #endif 758