1 /* 2 * QEMU VMWARE VMXNET3 paravirtual NIC 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: 9 * Dmitry Fleytman <dmitry@daynix.com> 10 * Tamir Shomer <tamirs@daynix.com> 11 * Yan Vugenfirer <yan@daynix.com> 12 * 13 * This work is licensed under the terms of the GNU GPL, version 2. 14 * See the COPYING file in the top-level directory. 15 * 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/hw.h" 20 #include "hw/pci/pci.h" 21 #include "net/net.h" 22 #include "net/tap.h" 23 #include "net/checksum.h" 24 #include "sysemu/sysemu.h" 25 #include "qemu-common.h" 26 #include "qemu/bswap.h" 27 #include "hw/pci/msix.h" 28 #include "hw/pci/msi.h" 29 #include "migration/register.h" 30 31 #include "vmxnet3.h" 32 #include "vmxnet_debug.h" 33 #include "vmware_utils.h" 34 #include "net_tx_pkt.h" 35 #include "net_rx_pkt.h" 36 37 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1 38 #define VMXNET3_MSIX_BAR_SIZE 0x2000 39 #define MIN_BUF_SIZE 60 40 41 /* Compatibility flags for migration */ 42 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0 43 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \ 44 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT) 45 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1 46 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \ 47 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT) 48 49 #define VMXNET3_EXP_EP_OFFSET (0x48) 50 #define VMXNET3_MSI_OFFSET(s) \ 51 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84) 52 #define VMXNET3_MSIX_OFFSET(s) \ 53 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c) 54 #define VMXNET3_DSN_OFFSET (0x100) 55 56 #define VMXNET3_BAR0_IDX (0) 57 #define VMXNET3_BAR1_IDX (1) 58 #define VMXNET3_MSIX_BAR_IDX (2) 59 60 #define VMXNET3_OFF_MSIX_TABLE (0x000) 61 #define VMXNET3_OFF_MSIX_PBA(s) \ 62 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000) 63 64 /* Link speed in Mbps should be shifted by 16 */ 65 #define VMXNET3_LINK_SPEED (1000 << 16) 66 67 /* Link status: 1 - up, 0 - down. */ 68 #define VMXNET3_LINK_STATUS_UP 0x1 69 70 /* Least significant bit should be set for revision and version */ 71 #define VMXNET3_UPT_REVISION 0x1 72 #define VMXNET3_DEVICE_REVISION 0x1 73 74 /* Number of interrupt vectors for non-MSIx modes */ 75 #define VMXNET3_MAX_NMSIX_INTRS (1) 76 77 /* Macros for rings descriptors access */ 78 #define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \ 79 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 80 81 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \ 82 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value))) 83 84 #define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \ 85 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 86 87 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \ 88 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 89 90 #define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \ 91 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 92 93 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \ 94 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 95 96 #define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \ 97 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 98 99 #define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \ 100 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 101 102 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \ 103 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 104 105 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \ 106 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 107 108 /* Macros for guest driver shared area access */ 109 #define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \ 110 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 111 112 #define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \ 113 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 114 115 #define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \ 116 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val)) 117 118 #define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \ 119 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 120 121 #define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \ 122 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 123 124 #define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \ 125 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l)) 126 127 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag)) 128 129 typedef struct VMXNET3Class { 130 PCIDeviceClass parent_class; 131 DeviceRealize parent_dc_realize; 132 } VMXNET3Class; 133 134 #define TYPE_VMXNET3 "vmxnet3" 135 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3) 136 137 #define VMXNET3_DEVICE_CLASS(klass) \ 138 OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3) 139 #define VMXNET3_DEVICE_GET_CLASS(obj) \ 140 OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3) 141 142 /* Cyclic ring abstraction */ 143 typedef struct { 144 hwaddr pa; 145 uint32_t size; 146 uint32_t cell_size; 147 uint32_t next; 148 uint8_t gen; 149 } Vmxnet3Ring; 150 151 static inline void vmxnet3_ring_init(PCIDevice *d, 152 Vmxnet3Ring *ring, 153 hwaddr pa, 154 uint32_t size, 155 uint32_t cell_size, 156 bool zero_region) 157 { 158 ring->pa = pa; 159 ring->size = size; 160 ring->cell_size = cell_size; 161 ring->gen = VMXNET3_INIT_GEN; 162 ring->next = 0; 163 164 if (zero_region) { 165 vmw_shmem_set(d, pa, 0, size * cell_size); 166 } 167 } 168 169 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \ 170 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \ 171 (ring_name), (ridx), \ 172 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next) 173 174 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring) 175 { 176 if (++ring->next >= ring->size) { 177 ring->next = 0; 178 ring->gen ^= 1; 179 } 180 } 181 182 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring) 183 { 184 if (ring->next-- == 0) { 185 ring->next = ring->size - 1; 186 ring->gen ^= 1; 187 } 188 } 189 190 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring) 191 { 192 return ring->pa + ring->next * ring->cell_size; 193 } 194 195 static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring, 196 void *buff) 197 { 198 vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 199 } 200 201 static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring, 202 void *buff) 203 { 204 vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 205 } 206 207 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring) 208 { 209 return ring->next; 210 } 211 212 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring) 213 { 214 return ring->gen; 215 } 216 217 /* Debug trace-related functions */ 218 static inline void 219 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr) 220 { 221 VMW_PKPRN("TX DESCR: " 222 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 223 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, " 224 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d", 225 descr->addr, descr->len, descr->gen, descr->rsvd, 226 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om, 227 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci); 228 } 229 230 static inline void 231 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr) 232 { 233 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, " 234 "csum_start: %d, csum_offset: %d", 235 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size, 236 vhdr->csum_start, vhdr->csum_offset); 237 } 238 239 static inline void 240 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr) 241 { 242 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 243 "dtype: %d, ext1: %d, btype: %d", 244 descr->addr, descr->len, descr->gen, 245 descr->rsvd, descr->dtype, descr->ext1, descr->btype); 246 } 247 248 /* Device state and helper functions */ 249 #define VMXNET3_RX_RINGS_PER_QUEUE (2) 250 251 typedef struct { 252 Vmxnet3Ring tx_ring; 253 Vmxnet3Ring comp_ring; 254 255 uint8_t intr_idx; 256 hwaddr tx_stats_pa; 257 struct UPT1_TxStats txq_stats; 258 } Vmxnet3TxqDescr; 259 260 typedef struct { 261 Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE]; 262 Vmxnet3Ring comp_ring; 263 uint8_t intr_idx; 264 hwaddr rx_stats_pa; 265 struct UPT1_RxStats rxq_stats; 266 } Vmxnet3RxqDescr; 267 268 typedef struct { 269 bool is_masked; 270 bool is_pending; 271 bool is_asserted; 272 } Vmxnet3IntState; 273 274 typedef struct { 275 PCIDevice parent_obj; 276 NICState *nic; 277 NICConf conf; 278 MemoryRegion bar0; 279 MemoryRegion bar1; 280 MemoryRegion msix_bar; 281 282 Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES]; 283 Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES]; 284 285 /* Whether MSI-X support was installed successfully */ 286 bool msix_used; 287 hwaddr drv_shmem; 288 hwaddr temp_shared_guest_driver_memory; 289 290 uint8_t txq_num; 291 292 /* This boolean tells whether RX packet being indicated has to */ 293 /* be split into head and body chunks from different RX rings */ 294 bool rx_packets_compound; 295 296 bool rx_vlan_stripping; 297 bool lro_supported; 298 299 uint8_t rxq_num; 300 301 /* Network MTU */ 302 uint32_t mtu; 303 304 /* Maximum number of fragments for indicated TX packets */ 305 uint32_t max_tx_frags; 306 307 /* Maximum number of fragments for indicated RX packets */ 308 uint16_t max_rx_frags; 309 310 /* Index for events interrupt */ 311 uint8_t event_int_idx; 312 313 /* Whether automatic interrupts masking enabled */ 314 bool auto_int_masking; 315 316 bool peer_has_vhdr; 317 318 /* TX packets to QEMU interface */ 319 struct NetTxPkt *tx_pkt; 320 uint32_t offload_mode; 321 uint32_t cso_or_gso_size; 322 uint16_t tci; 323 bool needs_vlan; 324 325 struct NetRxPkt *rx_pkt; 326 327 bool tx_sop; 328 bool skip_current_tx_pkt; 329 330 uint32_t device_active; 331 uint32_t last_command; 332 333 uint32_t link_status_and_speed; 334 335 Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS]; 336 337 uint32_t temp_mac; /* To store the low part first */ 338 339 MACAddr perm_mac; 340 uint32_t vlan_table[VMXNET3_VFT_SIZE]; 341 uint32_t rx_mode; 342 MACAddr *mcast_list; 343 uint32_t mcast_list_len; 344 uint32_t mcast_list_buff_size; /* needed for live migration. */ 345 346 /* Compatibility flags for migration */ 347 uint32_t compat_flags; 348 } VMXNET3State; 349 350 /* Interrupt management */ 351 352 /* 353 * This function returns sign whether interrupt line is in asserted state 354 * This depends on the type of interrupt used. For INTX interrupt line will 355 * be asserted until explicit deassertion, for MSI(X) interrupt line will 356 * be deasserted automatically due to notification semantics of the MSI(X) 357 * interrupts 358 */ 359 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx) 360 { 361 PCIDevice *d = PCI_DEVICE(s); 362 363 if (s->msix_used && msix_enabled(d)) { 364 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx); 365 msix_notify(d, int_idx); 366 return false; 367 } 368 if (msi_enabled(d)) { 369 VMW_IRPRN("Sending MSI notification for vector %u", int_idx); 370 msi_notify(d, int_idx); 371 return false; 372 } 373 374 VMW_IRPRN("Asserting line for interrupt %u", int_idx); 375 pci_irq_assert(d); 376 return true; 377 } 378 379 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx) 380 { 381 PCIDevice *d = PCI_DEVICE(s); 382 383 /* 384 * This function should never be called for MSI(X) interrupts 385 * because deassertion never required for message interrupts 386 */ 387 assert(!s->msix_used || !msix_enabled(d)); 388 /* 389 * This function should never be called for MSI(X) interrupts 390 * because deassertion never required for message interrupts 391 */ 392 assert(!msi_enabled(d)); 393 394 VMW_IRPRN("Deasserting line for interrupt %u", lidx); 395 pci_irq_deassert(d); 396 } 397 398 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx) 399 { 400 if (!s->interrupt_states[lidx].is_pending && 401 s->interrupt_states[lidx].is_asserted) { 402 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx); 403 _vmxnet3_deassert_interrupt_line(s, lidx); 404 s->interrupt_states[lidx].is_asserted = false; 405 return; 406 } 407 408 if (s->interrupt_states[lidx].is_pending && 409 !s->interrupt_states[lidx].is_masked && 410 !s->interrupt_states[lidx].is_asserted) { 411 VMW_IRPRN("New interrupt line state for index %d is UP", lidx); 412 s->interrupt_states[lidx].is_asserted = 413 _vmxnet3_assert_interrupt_line(s, lidx); 414 s->interrupt_states[lidx].is_pending = false; 415 return; 416 } 417 } 418 419 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx) 420 { 421 PCIDevice *d = PCI_DEVICE(s); 422 s->interrupt_states[lidx].is_pending = true; 423 vmxnet3_update_interrupt_line_state(s, lidx); 424 425 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) { 426 goto do_automask; 427 } 428 429 if (msi_enabled(d) && s->auto_int_masking) { 430 goto do_automask; 431 } 432 433 return; 434 435 do_automask: 436 s->interrupt_states[lidx].is_masked = true; 437 vmxnet3_update_interrupt_line_state(s, lidx); 438 } 439 440 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx) 441 { 442 return s->interrupt_states[lidx].is_asserted; 443 } 444 445 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx) 446 { 447 s->interrupt_states[int_idx].is_pending = false; 448 if (s->auto_int_masking) { 449 s->interrupt_states[int_idx].is_masked = true; 450 } 451 vmxnet3_update_interrupt_line_state(s, int_idx); 452 } 453 454 static void 455 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked) 456 { 457 s->interrupt_states[lidx].is_masked = is_masked; 458 vmxnet3_update_interrupt_line_state(s, lidx); 459 } 460 461 static bool vmxnet3_verify_driver_magic(PCIDevice *d, hwaddr dshmem) 462 { 463 return (VMXNET3_READ_DRV_SHARED32(d, dshmem, magic) == VMXNET3_REV1_MAGIC); 464 } 465 466 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF) 467 #define VMXNET3_MAKE_BYTE(byte_num, val) \ 468 (((uint32_t)((val) & 0xFF)) << (byte_num)*8) 469 470 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l) 471 { 472 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0); 473 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1); 474 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2); 475 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3); 476 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0); 477 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1); 478 479 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 480 481 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 482 } 483 484 static uint64_t vmxnet3_get_mac_low(MACAddr *addr) 485 { 486 return VMXNET3_MAKE_BYTE(0, addr->a[0]) | 487 VMXNET3_MAKE_BYTE(1, addr->a[1]) | 488 VMXNET3_MAKE_BYTE(2, addr->a[2]) | 489 VMXNET3_MAKE_BYTE(3, addr->a[3]); 490 } 491 492 static uint64_t vmxnet3_get_mac_high(MACAddr *addr) 493 { 494 return VMXNET3_MAKE_BYTE(0, addr->a[4]) | 495 VMXNET3_MAKE_BYTE(1, addr->a[5]); 496 } 497 498 static void 499 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx) 500 { 501 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring); 502 } 503 504 static inline void 505 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx) 506 { 507 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]); 508 } 509 510 static inline void 511 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx) 512 { 513 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring); 514 } 515 516 static void 517 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx) 518 { 519 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring); 520 } 521 522 static void 523 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx) 524 { 525 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring); 526 } 527 528 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx) 529 { 530 struct Vmxnet3_TxCompDesc txcq_descr; 531 PCIDevice *d = PCI_DEVICE(s); 532 533 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring); 534 535 memset(&txcq_descr, 0, sizeof(txcq_descr)); 536 txcq_descr.txdIdx = tx_ridx; 537 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring); 538 txcq_descr.val1 = cpu_to_le32(txcq_descr.val1); 539 txcq_descr.val2 = cpu_to_le32(txcq_descr.val2); 540 vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr); 541 542 /* Flush changes in TX descriptor before changing the counter value */ 543 smp_wmb(); 544 545 vmxnet3_inc_tx_completion_counter(s, qidx); 546 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx); 547 } 548 549 static bool 550 vmxnet3_setup_tx_offloads(VMXNET3State *s) 551 { 552 switch (s->offload_mode) { 553 case VMXNET3_OM_NONE: 554 net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0); 555 break; 556 557 case VMXNET3_OM_CSUM: 558 net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0); 559 VMW_PKPRN("L4 CSO requested\n"); 560 break; 561 562 case VMXNET3_OM_TSO: 563 net_tx_pkt_build_vheader(s->tx_pkt, true, true, 564 s->cso_or_gso_size); 565 net_tx_pkt_update_ip_checksums(s->tx_pkt); 566 VMW_PKPRN("GSO offload requested."); 567 break; 568 569 default: 570 g_assert_not_reached(); 571 return false; 572 } 573 574 return true; 575 } 576 577 static void 578 vmxnet3_tx_retrieve_metadata(VMXNET3State *s, 579 const struct Vmxnet3_TxDesc *txd) 580 { 581 s->offload_mode = txd->om; 582 s->cso_or_gso_size = txd->msscof; 583 s->tci = txd->tci; 584 s->needs_vlan = txd->ti; 585 } 586 587 typedef enum { 588 VMXNET3_PKT_STATUS_OK, 589 VMXNET3_PKT_STATUS_ERROR, 590 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */ 591 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */ 592 } Vmxnet3PktStatus; 593 594 static void 595 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx, 596 Vmxnet3PktStatus status) 597 { 598 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt); 599 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats; 600 601 switch (status) { 602 case VMXNET3_PKT_STATUS_OK: 603 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) { 604 case ETH_PKT_BCAST: 605 stats->bcastPktsTxOK++; 606 stats->bcastBytesTxOK += tot_len; 607 break; 608 case ETH_PKT_MCAST: 609 stats->mcastPktsTxOK++; 610 stats->mcastBytesTxOK += tot_len; 611 break; 612 case ETH_PKT_UCAST: 613 stats->ucastPktsTxOK++; 614 stats->ucastBytesTxOK += tot_len; 615 break; 616 default: 617 g_assert_not_reached(); 618 } 619 620 if (s->offload_mode == VMXNET3_OM_TSO) { 621 /* 622 * According to VMWARE headers this statistic is a number 623 * of packets after segmentation but since we don't have 624 * this information in QEMU model, the best we can do is to 625 * provide number of non-segmented packets 626 */ 627 stats->TSOPktsTxOK++; 628 stats->TSOBytesTxOK += tot_len; 629 } 630 break; 631 632 case VMXNET3_PKT_STATUS_DISCARD: 633 stats->pktsTxDiscard++; 634 break; 635 636 case VMXNET3_PKT_STATUS_ERROR: 637 stats->pktsTxError++; 638 break; 639 640 default: 641 g_assert_not_reached(); 642 } 643 } 644 645 static void 646 vmxnet3_on_rx_done_update_stats(VMXNET3State *s, 647 int qidx, 648 Vmxnet3PktStatus status) 649 { 650 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats; 651 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt); 652 653 switch (status) { 654 case VMXNET3_PKT_STATUS_OUT_OF_BUF: 655 stats->pktsRxOutOfBuf++; 656 break; 657 658 case VMXNET3_PKT_STATUS_ERROR: 659 stats->pktsRxError++; 660 break; 661 case VMXNET3_PKT_STATUS_OK: 662 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 663 case ETH_PKT_BCAST: 664 stats->bcastPktsRxOK++; 665 stats->bcastBytesRxOK += tot_len; 666 break; 667 case ETH_PKT_MCAST: 668 stats->mcastPktsRxOK++; 669 stats->mcastBytesRxOK += tot_len; 670 break; 671 case ETH_PKT_UCAST: 672 stats->ucastPktsRxOK++; 673 stats->ucastBytesRxOK += tot_len; 674 break; 675 default: 676 g_assert_not_reached(); 677 } 678 679 if (tot_len > s->mtu) { 680 stats->LROPktsRxOK++; 681 stats->LROBytesRxOK += tot_len; 682 } 683 break; 684 default: 685 g_assert_not_reached(); 686 } 687 } 688 689 static inline void 690 vmxnet3_ring_read_curr_txdesc(PCIDevice *pcidev, Vmxnet3Ring *ring, 691 struct Vmxnet3_TxDesc *txd) 692 { 693 vmxnet3_ring_read_curr_cell(pcidev, ring, txd); 694 txd->addr = le64_to_cpu(txd->addr); 695 txd->val1 = le32_to_cpu(txd->val1); 696 txd->val2 = le32_to_cpu(txd->val2); 697 } 698 699 static inline bool 700 vmxnet3_pop_next_tx_descr(VMXNET3State *s, 701 int qidx, 702 struct Vmxnet3_TxDesc *txd, 703 uint32_t *descr_idx) 704 { 705 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring; 706 PCIDevice *d = PCI_DEVICE(s); 707 708 vmxnet3_ring_read_curr_txdesc(d, ring, txd); 709 if (txd->gen == vmxnet3_ring_curr_gen(ring)) { 710 /* Only read after generation field verification */ 711 smp_rmb(); 712 /* Re-read to be sure we got the latest version */ 713 vmxnet3_ring_read_curr_txdesc(d, ring, txd); 714 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring); 715 *descr_idx = vmxnet3_ring_curr_cell_idx(ring); 716 vmxnet3_inc_tx_consumption_counter(s, qidx); 717 return true; 718 } 719 720 return false; 721 } 722 723 static bool 724 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx) 725 { 726 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK; 727 728 if (!vmxnet3_setup_tx_offloads(s)) { 729 status = VMXNET3_PKT_STATUS_ERROR; 730 goto func_exit; 731 } 732 733 /* debug prints */ 734 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt)); 735 net_tx_pkt_dump(s->tx_pkt); 736 737 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) { 738 status = VMXNET3_PKT_STATUS_DISCARD; 739 goto func_exit; 740 } 741 742 func_exit: 743 vmxnet3_on_tx_done_update_stats(s, qidx, status); 744 return (status == VMXNET3_PKT_STATUS_OK); 745 } 746 747 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx) 748 { 749 struct Vmxnet3_TxDesc txd; 750 uint32_t txd_idx; 751 uint32_t data_len; 752 hwaddr data_pa; 753 754 for (;;) { 755 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) { 756 break; 757 } 758 759 vmxnet3_dump_tx_descr(&txd); 760 761 if (!s->skip_current_tx_pkt) { 762 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE; 763 data_pa = txd.addr; 764 765 if (!net_tx_pkt_add_raw_fragment(s->tx_pkt, 766 data_pa, 767 data_len)) { 768 s->skip_current_tx_pkt = true; 769 } 770 } 771 772 if (s->tx_sop) { 773 vmxnet3_tx_retrieve_metadata(s, &txd); 774 s->tx_sop = false; 775 } 776 777 if (txd.eop) { 778 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) { 779 if (s->needs_vlan) { 780 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci); 781 } 782 783 vmxnet3_send_packet(s, qidx); 784 } else { 785 vmxnet3_on_tx_done_update_stats(s, qidx, 786 VMXNET3_PKT_STATUS_ERROR); 787 } 788 789 vmxnet3_complete_packet(s, qidx, txd_idx); 790 s->tx_sop = true; 791 s->skip_current_tx_pkt = false; 792 net_tx_pkt_reset(s->tx_pkt); 793 } 794 } 795 } 796 797 static inline void 798 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx, 799 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx) 800 { 801 PCIDevice *d = PCI_DEVICE(s); 802 803 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx]; 804 *didx = vmxnet3_ring_curr_cell_idx(ring); 805 vmxnet3_ring_read_curr_cell(d, ring, dbuf); 806 dbuf->addr = le64_to_cpu(dbuf->addr); 807 dbuf->val1 = le32_to_cpu(dbuf->val1); 808 dbuf->ext1 = le32_to_cpu(dbuf->ext1); 809 } 810 811 static inline uint8_t 812 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx) 813 { 814 return s->rxq_descr[qidx].rx_ring[ridx].gen; 815 } 816 817 static inline hwaddr 818 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen) 819 { 820 uint8_t ring_gen; 821 struct Vmxnet3_RxCompDesc rxcd; 822 823 hwaddr daddr = 824 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring); 825 826 pci_dma_read(PCI_DEVICE(s), 827 daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc)); 828 rxcd.val1 = le32_to_cpu(rxcd.val1); 829 rxcd.val2 = le32_to_cpu(rxcd.val2); 830 rxcd.val3 = le32_to_cpu(rxcd.val3); 831 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring); 832 833 if (rxcd.gen != ring_gen) { 834 *descr_gen = ring_gen; 835 vmxnet3_inc_rx_completion_counter(s, qidx); 836 return daddr; 837 } 838 839 return 0; 840 } 841 842 static inline void 843 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx) 844 { 845 vmxnet3_dec_rx_completion_counter(s, qidx); 846 } 847 848 #define RXQ_IDX (0) 849 #define RX_HEAD_BODY_RING (0) 850 #define RX_BODY_ONLY_RING (1) 851 852 static bool 853 vmxnet3_get_next_head_rx_descr(VMXNET3State *s, 854 struct Vmxnet3_RxDesc *descr_buf, 855 uint32_t *descr_idx, 856 uint32_t *ridx) 857 { 858 for (;;) { 859 uint32_t ring_gen; 860 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 861 descr_buf, descr_idx); 862 863 /* If no more free descriptors - return */ 864 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING); 865 if (descr_buf->gen != ring_gen) { 866 return false; 867 } 868 869 /* Only read after generation field verification */ 870 smp_rmb(); 871 /* Re-read to be sure we got the latest version */ 872 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 873 descr_buf, descr_idx); 874 875 /* Mark current descriptor as used/skipped */ 876 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 877 878 /* If this is what we are looking for - return */ 879 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) { 880 *ridx = RX_HEAD_BODY_RING; 881 return true; 882 } 883 } 884 } 885 886 static bool 887 vmxnet3_get_next_body_rx_descr(VMXNET3State *s, 888 struct Vmxnet3_RxDesc *d, 889 uint32_t *didx, 890 uint32_t *ridx) 891 { 892 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 893 894 /* Try to find corresponding descriptor in head/body ring */ 895 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) { 896 /* Only read after generation field verification */ 897 smp_rmb(); 898 /* Re-read to be sure we got the latest version */ 899 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 900 if (d->btype == VMXNET3_RXD_BTYPE_BODY) { 901 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 902 *ridx = RX_HEAD_BODY_RING; 903 return true; 904 } 905 } 906 907 /* 908 * If there is no free descriptors on head/body ring or next free 909 * descriptor is a head descriptor switch to body only ring 910 */ 911 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 912 913 /* If no more free descriptors - return */ 914 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) { 915 /* Only read after generation field verification */ 916 smp_rmb(); 917 /* Re-read to be sure we got the latest version */ 918 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 919 assert(d->btype == VMXNET3_RXD_BTYPE_BODY); 920 *ridx = RX_BODY_ONLY_RING; 921 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING); 922 return true; 923 } 924 925 return false; 926 } 927 928 static inline bool 929 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head, 930 struct Vmxnet3_RxDesc *descr_buf, 931 uint32_t *descr_idx, 932 uint32_t *ridx) 933 { 934 if (is_head || !s->rx_packets_compound) { 935 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx); 936 } else { 937 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx); 938 } 939 } 940 941 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID), 942 * the implementation always passes an RxCompDesc with a "Checksum 943 * calculated and found correct" to the OS (cnc=0 and tuc=1, see 944 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior. 945 * 946 * Therefore, if packet has the NEEDS_CSUM set, we must calculate 947 * and place a fully computed checksum into the tcp/udp header. 948 * Otherwise, the OS driver will receive a checksum-correct indication 949 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field 950 * having just the pseudo header csum value. 951 * 952 * While this is not a problem if packet is destined for local delivery, 953 * in the case the host OS performs forwarding, it will forward an 954 * incorrectly checksummed packet. 955 */ 956 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt, 957 const void *pkt_data, 958 size_t pkt_len) 959 { 960 struct virtio_net_hdr *vhdr; 961 bool isip4, isip6, istcp, isudp; 962 uint8_t *data; 963 int len; 964 965 if (!net_rx_pkt_has_virt_hdr(pkt)) { 966 return; 967 } 968 969 vhdr = net_rx_pkt_get_vhdr(pkt); 970 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 971 return; 972 } 973 974 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 975 if (!(isip4 || isip6) || !(istcp || isudp)) { 976 return; 977 } 978 979 vmxnet3_dump_virt_hdr(vhdr); 980 981 /* Validate packet len: csum_start + scum_offset + length of csum field */ 982 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) { 983 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, " 984 "cannot calculate checksum", 985 pkt_len, vhdr->csum_start, vhdr->csum_offset); 986 return; 987 } 988 989 data = (uint8_t *)pkt_data + vhdr->csum_start; 990 len = pkt_len - vhdr->csum_start; 991 /* Put the checksum obtained into the packet */ 992 stw_be_p(data + vhdr->csum_offset, 993 net_checksum_finish_nozero(net_checksum_add(len, data))); 994 995 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM; 996 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID; 997 } 998 999 static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt, 1000 struct Vmxnet3_RxCompDesc *rxcd) 1001 { 1002 int csum_ok, is_gso; 1003 bool isip4, isip6, istcp, isudp; 1004 struct virtio_net_hdr *vhdr; 1005 uint8_t offload_type; 1006 1007 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1008 rxcd->ts = 1; 1009 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt); 1010 } 1011 1012 if (!net_rx_pkt_has_virt_hdr(pkt)) { 1013 goto nocsum; 1014 } 1015 1016 vhdr = net_rx_pkt_get_vhdr(pkt); 1017 /* 1018 * Checksum is valid when lower level tell so or when lower level 1019 * requires checksum offload telling that packet produced/bridged 1020 * locally and did travel over network after last checksum calculation 1021 * or production 1022 */ 1023 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) || 1024 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM); 1025 1026 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN; 1027 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0; 1028 1029 if (!csum_ok && !is_gso) { 1030 goto nocsum; 1031 } 1032 1033 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 1034 if ((!istcp && !isudp) || (!isip4 && !isip6)) { 1035 goto nocsum; 1036 } 1037 1038 rxcd->cnc = 0; 1039 rxcd->v4 = isip4 ? 1 : 0; 1040 rxcd->v6 = isip6 ? 1 : 0; 1041 rxcd->tcp = istcp ? 1 : 0; 1042 rxcd->udp = isudp ? 1 : 0; 1043 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1; 1044 return; 1045 1046 nocsum: 1047 rxcd->cnc = 1; 1048 return; 1049 } 1050 1051 static void 1052 vmxnet3_pci_dma_writev(PCIDevice *pci_dev, 1053 const struct iovec *iov, 1054 size_t start_iov_off, 1055 hwaddr target_addr, 1056 size_t bytes_to_copy) 1057 { 1058 size_t curr_off = 0; 1059 size_t copied = 0; 1060 1061 while (bytes_to_copy) { 1062 if (start_iov_off < (curr_off + iov->iov_len)) { 1063 size_t chunk_len = 1064 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy); 1065 1066 pci_dma_write(pci_dev, target_addr + copied, 1067 iov->iov_base + start_iov_off - curr_off, 1068 chunk_len); 1069 1070 copied += chunk_len; 1071 start_iov_off += chunk_len; 1072 curr_off = start_iov_off; 1073 bytes_to_copy -= chunk_len; 1074 } else { 1075 curr_off += iov->iov_len; 1076 } 1077 iov++; 1078 } 1079 } 1080 1081 static void 1082 vmxnet3_pci_dma_write_rxcd(PCIDevice *pcidev, dma_addr_t pa, 1083 struct Vmxnet3_RxCompDesc *rxcd) 1084 { 1085 rxcd->val1 = cpu_to_le32(rxcd->val1); 1086 rxcd->val2 = cpu_to_le32(rxcd->val2); 1087 rxcd->val3 = cpu_to_le32(rxcd->val3); 1088 pci_dma_write(pcidev, pa, rxcd, sizeof(*rxcd)); 1089 } 1090 1091 static bool 1092 vmxnet3_indicate_packet(VMXNET3State *s) 1093 { 1094 struct Vmxnet3_RxDesc rxd; 1095 PCIDevice *d = PCI_DEVICE(s); 1096 bool is_head = true; 1097 uint32_t rxd_idx; 1098 uint32_t rx_ridx = 0; 1099 1100 struct Vmxnet3_RxCompDesc rxcd; 1101 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN; 1102 hwaddr new_rxcd_pa = 0; 1103 hwaddr ready_rxcd_pa = 0; 1104 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt); 1105 size_t bytes_copied = 0; 1106 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt); 1107 uint16_t num_frags = 0; 1108 size_t chunk_size; 1109 1110 net_rx_pkt_dump(s->rx_pkt); 1111 1112 while (bytes_left > 0) { 1113 1114 /* cannot add more frags to packet */ 1115 if (num_frags == s->max_rx_frags) { 1116 break; 1117 } 1118 1119 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen); 1120 if (!new_rxcd_pa) { 1121 break; 1122 } 1123 1124 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) { 1125 break; 1126 } 1127 1128 chunk_size = MIN(bytes_left, rxd.len); 1129 vmxnet3_pci_dma_writev(d, data, bytes_copied, rxd.addr, chunk_size); 1130 bytes_copied += chunk_size; 1131 bytes_left -= chunk_size; 1132 1133 vmxnet3_dump_rx_descr(&rxd); 1134 1135 if (ready_rxcd_pa != 0) { 1136 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd); 1137 } 1138 1139 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc)); 1140 rxcd.rxdIdx = rxd_idx; 1141 rxcd.len = chunk_size; 1142 rxcd.sop = is_head; 1143 rxcd.gen = new_rxcd_gen; 1144 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num; 1145 1146 if (bytes_left == 0) { 1147 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd); 1148 } 1149 1150 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu " 1151 "sop %d csum_correct %lu", 1152 (unsigned long) rx_ridx, 1153 (unsigned long) rxcd.rxdIdx, 1154 (unsigned long) rxcd.len, 1155 (int) rxcd.sop, 1156 (unsigned long) rxcd.tuc); 1157 1158 is_head = false; 1159 ready_rxcd_pa = new_rxcd_pa; 1160 new_rxcd_pa = 0; 1161 num_frags++; 1162 } 1163 1164 if (ready_rxcd_pa != 0) { 1165 rxcd.eop = 1; 1166 rxcd.err = (bytes_left != 0); 1167 1168 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd); 1169 1170 /* Flush RX descriptor changes */ 1171 smp_wmb(); 1172 } 1173 1174 if (new_rxcd_pa != 0) { 1175 vmxnet3_revert_rxc_descr(s, RXQ_IDX); 1176 } 1177 1178 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx); 1179 1180 if (bytes_left == 0) { 1181 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK); 1182 return true; 1183 } else if (num_frags == s->max_rx_frags) { 1184 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR); 1185 return false; 1186 } else { 1187 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, 1188 VMXNET3_PKT_STATUS_OUT_OF_BUF); 1189 return false; 1190 } 1191 } 1192 1193 static void 1194 vmxnet3_io_bar0_write(void *opaque, hwaddr addr, 1195 uint64_t val, unsigned size) 1196 { 1197 VMXNET3State *s = opaque; 1198 1199 if (!s->device_active) { 1200 return; 1201 } 1202 1203 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD, 1204 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) { 1205 int tx_queue_idx = 1206 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD, 1207 VMXNET3_REG_ALIGN); 1208 assert(tx_queue_idx <= s->txq_num); 1209 vmxnet3_process_tx_queue(s, tx_queue_idx); 1210 return; 1211 } 1212 1213 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1214 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1215 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1216 VMXNET3_REG_ALIGN); 1217 1218 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val); 1219 1220 vmxnet3_on_interrupt_mask_changed(s, l, val); 1221 return; 1222 } 1223 1224 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD, 1225 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) || 1226 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2, 1227 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) { 1228 return; 1229 } 1230 1231 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d", 1232 (uint64_t) addr, val, size); 1233 } 1234 1235 static uint64_t 1236 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size) 1237 { 1238 VMXNET3State *s = opaque; 1239 1240 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1241 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1242 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1243 VMXNET3_REG_ALIGN); 1244 return s->interrupt_states[l].is_masked; 1245 } 1246 1247 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size); 1248 return 0; 1249 } 1250 1251 static void vmxnet3_reset_interrupt_states(VMXNET3State *s) 1252 { 1253 int i; 1254 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) { 1255 s->interrupt_states[i].is_asserted = false; 1256 s->interrupt_states[i].is_pending = false; 1257 s->interrupt_states[i].is_masked = true; 1258 } 1259 } 1260 1261 static void vmxnet3_reset_mac(VMXNET3State *s) 1262 { 1263 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a)); 1264 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 1265 } 1266 1267 static void vmxnet3_deactivate_device(VMXNET3State *s) 1268 { 1269 if (s->device_active) { 1270 VMW_CBPRN("Deactivating vmxnet3..."); 1271 net_tx_pkt_reset(s->tx_pkt); 1272 net_tx_pkt_uninit(s->tx_pkt); 1273 net_rx_pkt_uninit(s->rx_pkt); 1274 s->device_active = false; 1275 } 1276 } 1277 1278 static void vmxnet3_reset(VMXNET3State *s) 1279 { 1280 VMW_CBPRN("Resetting vmxnet3..."); 1281 1282 vmxnet3_deactivate_device(s); 1283 vmxnet3_reset_interrupt_states(s); 1284 s->drv_shmem = 0; 1285 s->tx_sop = true; 1286 s->skip_current_tx_pkt = false; 1287 } 1288 1289 static void vmxnet3_update_rx_mode(VMXNET3State *s) 1290 { 1291 PCIDevice *d = PCI_DEVICE(s); 1292 1293 s->rx_mode = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, 1294 devRead.rxFilterConf.rxMode); 1295 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode); 1296 } 1297 1298 static void vmxnet3_update_vlan_filters(VMXNET3State *s) 1299 { 1300 int i; 1301 PCIDevice *d = PCI_DEVICE(s); 1302 1303 /* Copy configuration from shared memory */ 1304 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, 1305 devRead.rxFilterConf.vfTable, 1306 s->vlan_table, 1307 sizeof(s->vlan_table)); 1308 1309 /* Invert byte order when needed */ 1310 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) { 1311 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]); 1312 } 1313 1314 /* Dump configuration for debugging purposes */ 1315 VMW_CFPRN("Configured VLANs:"); 1316 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) { 1317 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) { 1318 VMW_CFPRN("\tVLAN %d is present", i); 1319 } 1320 } 1321 } 1322 1323 static void vmxnet3_update_mcast_filters(VMXNET3State *s) 1324 { 1325 PCIDevice *d = PCI_DEVICE(s); 1326 1327 uint16_t list_bytes = 1328 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, 1329 devRead.rxFilterConf.mfTableLen); 1330 1331 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]); 1332 1333 s->mcast_list = g_realloc(s->mcast_list, list_bytes); 1334 if (!s->mcast_list) { 1335 if (s->mcast_list_len == 0) { 1336 VMW_CFPRN("Current multicast list is empty"); 1337 } else { 1338 VMW_ERPRN("Failed to allocate multicast list of %d elements", 1339 s->mcast_list_len); 1340 } 1341 s->mcast_list_len = 0; 1342 } else { 1343 int i; 1344 hwaddr mcast_list_pa = 1345 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, 1346 devRead.rxFilterConf.mfTablePA); 1347 1348 pci_dma_read(d, mcast_list_pa, s->mcast_list, list_bytes); 1349 1350 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len); 1351 for (i = 0; i < s->mcast_list_len; i++) { 1352 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a)); 1353 } 1354 } 1355 } 1356 1357 static void vmxnet3_setup_rx_filtering(VMXNET3State *s) 1358 { 1359 vmxnet3_update_rx_mode(s); 1360 vmxnet3_update_vlan_filters(s); 1361 vmxnet3_update_mcast_filters(s); 1362 } 1363 1364 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s) 1365 { 1366 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2); 1367 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode); 1368 return interrupt_mode; 1369 } 1370 1371 static void vmxnet3_fill_stats(VMXNET3State *s) 1372 { 1373 int i; 1374 PCIDevice *d = PCI_DEVICE(s); 1375 1376 if (!s->device_active) 1377 return; 1378 1379 for (i = 0; i < s->txq_num; i++) { 1380 pci_dma_write(d, 1381 s->txq_descr[i].tx_stats_pa, 1382 &s->txq_descr[i].txq_stats, 1383 sizeof(s->txq_descr[i].txq_stats)); 1384 } 1385 1386 for (i = 0; i < s->rxq_num; i++) { 1387 pci_dma_write(d, 1388 s->rxq_descr[i].rx_stats_pa, 1389 &s->rxq_descr[i].rxq_stats, 1390 sizeof(s->rxq_descr[i].rxq_stats)); 1391 } 1392 } 1393 1394 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s) 1395 { 1396 struct Vmxnet3_GOSInfo gos; 1397 PCIDevice *d = PCI_DEVICE(s); 1398 1399 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, devRead.misc.driverInfo.gos, 1400 &gos, sizeof(gos)); 1401 s->rx_packets_compound = 1402 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true; 1403 1404 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound); 1405 } 1406 1407 static void 1408 vmxnet3_dump_conf_descr(const char *name, 1409 struct Vmxnet3_VariableLenConfDesc *pm_descr) 1410 { 1411 VMW_CFPRN("%s descriptor dump: Version %u, Length %u", 1412 name, pm_descr->confVer, pm_descr->confLen); 1413 1414 }; 1415 1416 static void vmxnet3_update_pm_state(VMXNET3State *s) 1417 { 1418 struct Vmxnet3_VariableLenConfDesc pm_descr; 1419 PCIDevice *d = PCI_DEVICE(s); 1420 1421 pm_descr.confLen = 1422 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confLen); 1423 pm_descr.confVer = 1424 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confVer); 1425 pm_descr.confPA = 1426 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.pmConfDesc.confPA); 1427 1428 vmxnet3_dump_conf_descr("PM State", &pm_descr); 1429 } 1430 1431 static void vmxnet3_update_features(VMXNET3State *s) 1432 { 1433 uint32_t guest_features; 1434 int rxcso_supported; 1435 PCIDevice *d = PCI_DEVICE(s); 1436 1437 guest_features = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, 1438 devRead.misc.uptFeatures); 1439 1440 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM); 1441 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN); 1442 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO); 1443 1444 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d", 1445 s->lro_supported, rxcso_supported, 1446 s->rx_vlan_stripping); 1447 if (s->peer_has_vhdr) { 1448 qemu_set_offload(qemu_get_queue(s->nic)->peer, 1449 rxcso_supported, 1450 s->lro_supported, 1451 s->lro_supported, 1452 0, 1453 0); 1454 } 1455 } 1456 1457 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx) 1458 { 1459 return s->msix_used || msi_enabled(PCI_DEVICE(s)) 1460 || intx == pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1; 1461 } 1462 1463 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx) 1464 { 1465 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS; 1466 if (idx >= max_ints) { 1467 hw_error("Bad interrupt index: %d\n", idx); 1468 } 1469 } 1470 1471 static void vmxnet3_validate_interrupts(VMXNET3State *s) 1472 { 1473 int i; 1474 1475 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx); 1476 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx); 1477 1478 for (i = 0; i < s->txq_num; i++) { 1479 int idx = s->txq_descr[i].intr_idx; 1480 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx); 1481 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1482 } 1483 1484 for (i = 0; i < s->rxq_num; i++) { 1485 int idx = s->rxq_descr[i].intr_idx; 1486 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx); 1487 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1488 } 1489 } 1490 1491 static void vmxnet3_validate_queues(VMXNET3State *s) 1492 { 1493 /* 1494 * txq_num and rxq_num are total number of queues 1495 * configured by guest. These numbers must not 1496 * exceed corresponding maximal values. 1497 */ 1498 1499 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) { 1500 hw_error("Bad TX queues number: %d\n", s->txq_num); 1501 } 1502 1503 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) { 1504 hw_error("Bad RX queues number: %d\n", s->rxq_num); 1505 } 1506 } 1507 1508 static void vmxnet3_activate_device(VMXNET3State *s) 1509 { 1510 int i; 1511 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1; 1512 PCIDevice *d = PCI_DEVICE(s); 1513 hwaddr qdescr_table_pa; 1514 uint64_t pa; 1515 uint32_t size; 1516 1517 /* Verify configuration consistency */ 1518 if (!vmxnet3_verify_driver_magic(d, s->drv_shmem)) { 1519 VMW_ERPRN("Device configuration received from driver is invalid"); 1520 return; 1521 } 1522 1523 /* Verify if device is active */ 1524 if (s->device_active) { 1525 VMW_CFPRN("Vmxnet3 device is active"); 1526 return; 1527 } 1528 1529 vmxnet3_adjust_by_guest_type(s); 1530 vmxnet3_update_features(s); 1531 vmxnet3_update_pm_state(s); 1532 vmxnet3_setup_rx_filtering(s); 1533 /* Cache fields from shared memory */ 1534 s->mtu = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.misc.mtu); 1535 VMW_CFPRN("MTU is %u", s->mtu); 1536 1537 s->max_rx_frags = 1538 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, devRead.misc.maxNumRxSG); 1539 1540 if (s->max_rx_frags == 0) { 1541 s->max_rx_frags = 1; 1542 } 1543 1544 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags); 1545 1546 s->event_int_idx = 1547 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.eventIntrIdx); 1548 assert(vmxnet3_verify_intx(s, s->event_int_idx)); 1549 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx); 1550 1551 s->auto_int_masking = 1552 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.autoMask); 1553 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking); 1554 1555 s->txq_num = 1556 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numTxQueues); 1557 s->rxq_num = 1558 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numRxQueues); 1559 1560 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num); 1561 vmxnet3_validate_queues(s); 1562 1563 qdescr_table_pa = 1564 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.misc.queueDescPA); 1565 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa); 1566 1567 /* 1568 * Worst-case scenario is a packet that holds all TX rings space so 1569 * we calculate total size of all TX rings for max TX fragments number 1570 */ 1571 s->max_tx_frags = 0; 1572 1573 /* TX queues */ 1574 for (i = 0; i < s->txq_num; i++) { 1575 hwaddr qdescr_pa = 1576 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc); 1577 1578 /* Read interrupt number for this TX queue */ 1579 s->txq_descr[i].intr_idx = 1580 VMXNET3_READ_TX_QUEUE_DESCR8(d, qdescr_pa, conf.intrIdx); 1581 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx)); 1582 1583 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx); 1584 1585 /* Read rings memory locations for TX queues */ 1586 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA); 1587 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.txRingSize); 1588 1589 vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size, 1590 sizeof(struct Vmxnet3_TxDesc), false); 1591 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring); 1592 1593 s->max_tx_frags += size; 1594 1595 /* TXC ring */ 1596 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA); 1597 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.compRingSize); 1598 vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size, 1599 sizeof(struct Vmxnet3_TxCompDesc), true); 1600 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring); 1601 1602 s->txq_descr[i].tx_stats_pa = 1603 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats); 1604 1605 memset(&s->txq_descr[i].txq_stats, 0, 1606 sizeof(s->txq_descr[i].txq_stats)); 1607 1608 /* Fill device-managed parameters for queues */ 1609 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa, 1610 ctrl.txThreshold, 1611 VMXNET3_DEF_TX_THRESHOLD); 1612 } 1613 1614 /* Preallocate TX packet wrapper */ 1615 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags); 1616 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), 1617 s->max_tx_frags, s->peer_has_vhdr); 1618 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); 1619 1620 /* Read rings memory locations for RX queues */ 1621 for (i = 0; i < s->rxq_num; i++) { 1622 int j; 1623 hwaddr qd_pa = 1624 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) + 1625 i * sizeof(struct Vmxnet3_RxQueueDesc); 1626 1627 /* Read interrupt number for this RX queue */ 1628 s->rxq_descr[i].intr_idx = 1629 VMXNET3_READ_TX_QUEUE_DESCR8(d, qd_pa, conf.intrIdx); 1630 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx)); 1631 1632 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx); 1633 1634 /* Read rings memory locations */ 1635 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) { 1636 /* RX rings */ 1637 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]); 1638 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.rxRingSize[j]); 1639 vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size, 1640 sizeof(struct Vmxnet3_RxDesc), false); 1641 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d", 1642 i, j, pa, size); 1643 } 1644 1645 /* RXC ring */ 1646 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA); 1647 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.compRingSize); 1648 vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size, 1649 sizeof(struct Vmxnet3_RxCompDesc), true); 1650 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size); 1651 1652 s->rxq_descr[i].rx_stats_pa = 1653 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats); 1654 memset(&s->rxq_descr[i].rxq_stats, 0, 1655 sizeof(s->rxq_descr[i].rxq_stats)); 1656 } 1657 1658 vmxnet3_validate_interrupts(s); 1659 1660 /* Make sure everything is in place before device activation */ 1661 smp_wmb(); 1662 1663 vmxnet3_reset_mac(s); 1664 1665 s->device_active = true; 1666 } 1667 1668 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd) 1669 { 1670 s->last_command = cmd; 1671 1672 switch (cmd) { 1673 case VMXNET3_CMD_GET_PERM_MAC_HI: 1674 VMW_CBPRN("Set: Get upper part of permanent MAC"); 1675 break; 1676 1677 case VMXNET3_CMD_GET_PERM_MAC_LO: 1678 VMW_CBPRN("Set: Get lower part of permanent MAC"); 1679 break; 1680 1681 case VMXNET3_CMD_GET_STATS: 1682 VMW_CBPRN("Set: Get device statistics"); 1683 vmxnet3_fill_stats(s); 1684 break; 1685 1686 case VMXNET3_CMD_ACTIVATE_DEV: 1687 VMW_CBPRN("Set: Activating vmxnet3 device"); 1688 vmxnet3_activate_device(s); 1689 break; 1690 1691 case VMXNET3_CMD_UPDATE_RX_MODE: 1692 VMW_CBPRN("Set: Update rx mode"); 1693 vmxnet3_update_rx_mode(s); 1694 break; 1695 1696 case VMXNET3_CMD_UPDATE_VLAN_FILTERS: 1697 VMW_CBPRN("Set: Update VLAN filters"); 1698 vmxnet3_update_vlan_filters(s); 1699 break; 1700 1701 case VMXNET3_CMD_UPDATE_MAC_FILTERS: 1702 VMW_CBPRN("Set: Update MAC filters"); 1703 vmxnet3_update_mcast_filters(s); 1704 break; 1705 1706 case VMXNET3_CMD_UPDATE_FEATURE: 1707 VMW_CBPRN("Set: Update features"); 1708 vmxnet3_update_features(s); 1709 break; 1710 1711 case VMXNET3_CMD_UPDATE_PMCFG: 1712 VMW_CBPRN("Set: Update power management config"); 1713 vmxnet3_update_pm_state(s); 1714 break; 1715 1716 case VMXNET3_CMD_GET_LINK: 1717 VMW_CBPRN("Set: Get link"); 1718 break; 1719 1720 case VMXNET3_CMD_RESET_DEV: 1721 VMW_CBPRN("Set: Reset device"); 1722 vmxnet3_reset(s); 1723 break; 1724 1725 case VMXNET3_CMD_QUIESCE_DEV: 1726 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device"); 1727 vmxnet3_deactivate_device(s); 1728 break; 1729 1730 case VMXNET3_CMD_GET_CONF_INTR: 1731 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration"); 1732 break; 1733 1734 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1735 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - " 1736 "adaptive ring info flags"); 1737 break; 1738 1739 case VMXNET3_CMD_GET_DID_LO: 1740 VMW_CBPRN("Set: Get lower part of device ID"); 1741 break; 1742 1743 case VMXNET3_CMD_GET_DID_HI: 1744 VMW_CBPRN("Set: Get upper part of device ID"); 1745 break; 1746 1747 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1748 VMW_CBPRN("Set: Get device extra info"); 1749 break; 1750 1751 default: 1752 VMW_CBPRN("Received unknown command: %" PRIx64, cmd); 1753 break; 1754 } 1755 } 1756 1757 static uint64_t vmxnet3_get_command_status(VMXNET3State *s) 1758 { 1759 uint64_t ret; 1760 1761 switch (s->last_command) { 1762 case VMXNET3_CMD_ACTIVATE_DEV: 1763 ret = (s->device_active) ? 0 : 1; 1764 VMW_CFPRN("Device active: %" PRIx64, ret); 1765 break; 1766 1767 case VMXNET3_CMD_RESET_DEV: 1768 case VMXNET3_CMD_QUIESCE_DEV: 1769 case VMXNET3_CMD_GET_QUEUE_STATUS: 1770 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1771 ret = 0; 1772 break; 1773 1774 case VMXNET3_CMD_GET_LINK: 1775 ret = s->link_status_and_speed; 1776 VMW_CFPRN("Link and speed: %" PRIx64, ret); 1777 break; 1778 1779 case VMXNET3_CMD_GET_PERM_MAC_LO: 1780 ret = vmxnet3_get_mac_low(&s->perm_mac); 1781 break; 1782 1783 case VMXNET3_CMD_GET_PERM_MAC_HI: 1784 ret = vmxnet3_get_mac_high(&s->perm_mac); 1785 break; 1786 1787 case VMXNET3_CMD_GET_CONF_INTR: 1788 ret = vmxnet3_get_interrupt_config(s); 1789 break; 1790 1791 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1792 ret = VMXNET3_DISABLE_ADAPTIVE_RING; 1793 break; 1794 1795 case VMXNET3_CMD_GET_DID_LO: 1796 ret = PCI_DEVICE_ID_VMWARE_VMXNET3; 1797 break; 1798 1799 case VMXNET3_CMD_GET_DID_HI: 1800 ret = VMXNET3_DEVICE_REVISION; 1801 break; 1802 1803 default: 1804 VMW_WRPRN("Received request for unknown command: %x", s->last_command); 1805 ret = 0; 1806 break; 1807 } 1808 1809 return ret; 1810 } 1811 1812 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val) 1813 { 1814 uint32_t events; 1815 PCIDevice *d = PCI_DEVICE(s); 1816 1817 VMW_CBPRN("Setting events: 0x%x", val); 1818 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) | val; 1819 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events); 1820 } 1821 1822 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val) 1823 { 1824 PCIDevice *d = PCI_DEVICE(s); 1825 uint32_t events; 1826 1827 VMW_CBPRN("Clearing events: 0x%x", val); 1828 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) & ~val; 1829 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events); 1830 } 1831 1832 static void 1833 vmxnet3_io_bar1_write(void *opaque, 1834 hwaddr addr, 1835 uint64_t val, 1836 unsigned size) 1837 { 1838 VMXNET3State *s = opaque; 1839 1840 switch (addr) { 1841 /* Vmxnet3 Revision Report Selection */ 1842 case VMXNET3_REG_VRRS: 1843 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d", 1844 val, size); 1845 break; 1846 1847 /* UPT Version Report Selection */ 1848 case VMXNET3_REG_UVRS: 1849 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d", 1850 val, size); 1851 break; 1852 1853 /* Driver Shared Address Low */ 1854 case VMXNET3_REG_DSAL: 1855 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d", 1856 val, size); 1857 /* 1858 * Guest driver will first write the low part of the shared 1859 * memory address. We save it to temp variable and set the 1860 * shared address only after we get the high part 1861 */ 1862 if (val == 0) { 1863 vmxnet3_deactivate_device(s); 1864 } 1865 s->temp_shared_guest_driver_memory = val; 1866 s->drv_shmem = 0; 1867 break; 1868 1869 /* Driver Shared Address High */ 1870 case VMXNET3_REG_DSAH: 1871 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d", 1872 val, size); 1873 /* 1874 * Set the shared memory between guest driver and device. 1875 * We already should have low address part. 1876 */ 1877 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32); 1878 break; 1879 1880 /* Command */ 1881 case VMXNET3_REG_CMD: 1882 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d", 1883 val, size); 1884 vmxnet3_handle_command(s, val); 1885 break; 1886 1887 /* MAC Address Low */ 1888 case VMXNET3_REG_MACL: 1889 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d", 1890 val, size); 1891 s->temp_mac = val; 1892 break; 1893 1894 /* MAC Address High */ 1895 case VMXNET3_REG_MACH: 1896 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d", 1897 val, size); 1898 vmxnet3_set_variable_mac(s, val, s->temp_mac); 1899 break; 1900 1901 /* Interrupt Cause Register */ 1902 case VMXNET3_REG_ICR: 1903 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d", 1904 val, size); 1905 g_assert_not_reached(); 1906 break; 1907 1908 /* Event Cause Register */ 1909 case VMXNET3_REG_ECR: 1910 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d", 1911 val, size); 1912 vmxnet3_ack_events(s, val); 1913 break; 1914 1915 default: 1916 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d", 1917 addr, val, size); 1918 break; 1919 } 1920 } 1921 1922 static uint64_t 1923 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size) 1924 { 1925 VMXNET3State *s = opaque; 1926 uint64_t ret = 0; 1927 1928 switch (addr) { 1929 /* Vmxnet3 Revision Report Selection */ 1930 case VMXNET3_REG_VRRS: 1931 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size); 1932 ret = VMXNET3_DEVICE_REVISION; 1933 break; 1934 1935 /* UPT Version Report Selection */ 1936 case VMXNET3_REG_UVRS: 1937 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size); 1938 ret = VMXNET3_UPT_REVISION; 1939 break; 1940 1941 /* Command */ 1942 case VMXNET3_REG_CMD: 1943 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size); 1944 ret = vmxnet3_get_command_status(s); 1945 break; 1946 1947 /* MAC Address Low */ 1948 case VMXNET3_REG_MACL: 1949 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size); 1950 ret = vmxnet3_get_mac_low(&s->conf.macaddr); 1951 break; 1952 1953 /* MAC Address High */ 1954 case VMXNET3_REG_MACH: 1955 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size); 1956 ret = vmxnet3_get_mac_high(&s->conf.macaddr); 1957 break; 1958 1959 /* 1960 * Interrupt Cause Register 1961 * Used for legacy interrupts only so interrupt index always 0 1962 */ 1963 case VMXNET3_REG_ICR: 1964 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size); 1965 if (vmxnet3_interrupt_asserted(s, 0)) { 1966 vmxnet3_clear_interrupt(s, 0); 1967 ret = true; 1968 } else { 1969 ret = false; 1970 } 1971 break; 1972 1973 default: 1974 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size); 1975 break; 1976 } 1977 1978 return ret; 1979 } 1980 1981 static int 1982 vmxnet3_can_receive(NetClientState *nc) 1983 { 1984 VMXNET3State *s = qemu_get_nic_opaque(nc); 1985 return s->device_active && 1986 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP); 1987 } 1988 1989 static inline bool 1990 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data) 1991 { 1992 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK; 1993 if (IS_SPECIAL_VLAN_ID(vlan_tag)) { 1994 return true; 1995 } 1996 1997 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag); 1998 } 1999 2000 static bool 2001 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac) 2002 { 2003 int i; 2004 for (i = 0; i < s->mcast_list_len; i++) { 2005 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) { 2006 return true; 2007 } 2008 } 2009 return false; 2010 } 2011 2012 static bool 2013 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data, 2014 size_t size) 2015 { 2016 struct eth_header *ehdr = PKT_GET_ETH_HDR(data); 2017 2018 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) { 2019 return true; 2020 } 2021 2022 if (!vmxnet3_is_registered_vlan(s, data)) { 2023 return false; 2024 } 2025 2026 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 2027 case ETH_PKT_UCAST: 2028 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) { 2029 return false; 2030 } 2031 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) { 2032 return false; 2033 } 2034 break; 2035 2036 case ETH_PKT_BCAST: 2037 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) { 2038 return false; 2039 } 2040 break; 2041 2042 case ETH_PKT_MCAST: 2043 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) { 2044 return true; 2045 } 2046 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) { 2047 return false; 2048 } 2049 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) { 2050 return false; 2051 } 2052 break; 2053 2054 default: 2055 g_assert_not_reached(); 2056 } 2057 2058 return true; 2059 } 2060 2061 static ssize_t 2062 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size) 2063 { 2064 VMXNET3State *s = qemu_get_nic_opaque(nc); 2065 size_t bytes_indicated; 2066 uint8_t min_buf[MIN_BUF_SIZE]; 2067 2068 if (!vmxnet3_can_receive(nc)) { 2069 VMW_PKPRN("Cannot receive now"); 2070 return -1; 2071 } 2072 2073 if (s->peer_has_vhdr) { 2074 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf); 2075 buf += sizeof(struct virtio_net_hdr); 2076 size -= sizeof(struct virtio_net_hdr); 2077 } 2078 2079 /* Pad to minimum Ethernet frame length */ 2080 if (size < sizeof(min_buf)) { 2081 memcpy(min_buf, buf, size); 2082 memset(&min_buf[size], 0, sizeof(min_buf) - size); 2083 buf = min_buf; 2084 size = sizeof(min_buf); 2085 } 2086 2087 net_rx_pkt_set_packet_type(s->rx_pkt, 2088 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 2089 2090 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) { 2091 net_rx_pkt_set_protocols(s->rx_pkt, buf, size); 2092 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size); 2093 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping); 2094 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1; 2095 if (bytes_indicated < size) { 2096 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size); 2097 } 2098 } else { 2099 VMW_PKPRN("Packet dropped by RX filter"); 2100 bytes_indicated = size; 2101 } 2102 2103 assert(size > 0); 2104 assert(bytes_indicated != 0); 2105 return bytes_indicated; 2106 } 2107 2108 static void vmxnet3_set_link_status(NetClientState *nc) 2109 { 2110 VMXNET3State *s = qemu_get_nic_opaque(nc); 2111 2112 if (nc->link_down) { 2113 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP; 2114 } else { 2115 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP; 2116 } 2117 2118 vmxnet3_set_events(s, VMXNET3_ECR_LINK); 2119 vmxnet3_trigger_interrupt(s, s->event_int_idx); 2120 } 2121 2122 static NetClientInfo net_vmxnet3_info = { 2123 .type = NET_CLIENT_DRIVER_NIC, 2124 .size = sizeof(NICState), 2125 .receive = vmxnet3_receive, 2126 .link_status_changed = vmxnet3_set_link_status, 2127 }; 2128 2129 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s) 2130 { 2131 NetClientState *nc = qemu_get_queue(s->nic); 2132 2133 if (qemu_has_vnet_hdr(nc->peer)) { 2134 return true; 2135 } 2136 2137 return false; 2138 } 2139 2140 static void vmxnet3_net_uninit(VMXNET3State *s) 2141 { 2142 g_free(s->mcast_list); 2143 vmxnet3_deactivate_device(s); 2144 qemu_del_nic(s->nic); 2145 } 2146 2147 static void vmxnet3_net_init(VMXNET3State *s) 2148 { 2149 DeviceState *d = DEVICE(s); 2150 2151 VMW_CBPRN("vmxnet3_net_init called..."); 2152 2153 qemu_macaddr_default_if_unset(&s->conf.macaddr); 2154 2155 /* Windows guest will query the address that was set on init */ 2156 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a)); 2157 2158 s->mcast_list = NULL; 2159 s->mcast_list_len = 0; 2160 2161 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP; 2162 2163 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a)); 2164 2165 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf, 2166 object_get_typename(OBJECT(s)), 2167 d->id, s); 2168 2169 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s); 2170 s->tx_sop = true; 2171 s->skip_current_tx_pkt = false; 2172 s->tx_pkt = NULL; 2173 s->rx_pkt = NULL; 2174 s->rx_vlan_stripping = false; 2175 s->lro_supported = false; 2176 2177 if (s->peer_has_vhdr) { 2178 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer, 2179 sizeof(struct virtio_net_hdr)); 2180 2181 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1); 2182 } 2183 2184 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 2185 } 2186 2187 static void 2188 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors) 2189 { 2190 PCIDevice *d = PCI_DEVICE(s); 2191 int i; 2192 for (i = 0; i < num_vectors; i++) { 2193 msix_vector_unuse(d, i); 2194 } 2195 } 2196 2197 static bool 2198 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors) 2199 { 2200 PCIDevice *d = PCI_DEVICE(s); 2201 int i; 2202 for (i = 0; i < num_vectors; i++) { 2203 int res = msix_vector_use(d, i); 2204 if (0 > res) { 2205 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res); 2206 vmxnet3_unuse_msix_vectors(s, i); 2207 return false; 2208 } 2209 } 2210 return true; 2211 } 2212 2213 static bool 2214 vmxnet3_init_msix(VMXNET3State *s) 2215 { 2216 PCIDevice *d = PCI_DEVICE(s); 2217 int res = msix_init(d, VMXNET3_MAX_INTRS, 2218 &s->msix_bar, 2219 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE, 2220 &s->msix_bar, 2221 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s), 2222 VMXNET3_MSIX_OFFSET(s), NULL); 2223 2224 if (0 > res) { 2225 VMW_WRPRN("Failed to initialize MSI-X, error %d", res); 2226 s->msix_used = false; 2227 } else { 2228 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) { 2229 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res); 2230 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2231 s->msix_used = false; 2232 } else { 2233 s->msix_used = true; 2234 } 2235 } 2236 return s->msix_used; 2237 } 2238 2239 static void 2240 vmxnet3_cleanup_msix(VMXNET3State *s) 2241 { 2242 PCIDevice *d = PCI_DEVICE(s); 2243 2244 if (s->msix_used) { 2245 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS); 2246 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2247 } 2248 } 2249 2250 static void 2251 vmxnet3_cleanup_msi(VMXNET3State *s) 2252 { 2253 PCIDevice *d = PCI_DEVICE(s); 2254 2255 msi_uninit(d); 2256 } 2257 2258 static void 2259 vmxnet3_msix_save(QEMUFile *f, void *opaque) 2260 { 2261 PCIDevice *d = PCI_DEVICE(opaque); 2262 msix_save(d, f); 2263 } 2264 2265 static int 2266 vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id) 2267 { 2268 PCIDevice *d = PCI_DEVICE(opaque); 2269 msix_load(d, f); 2270 return 0; 2271 } 2272 2273 static const MemoryRegionOps b0_ops = { 2274 .read = vmxnet3_io_bar0_read, 2275 .write = vmxnet3_io_bar0_write, 2276 .endianness = DEVICE_LITTLE_ENDIAN, 2277 .impl = { 2278 .min_access_size = 4, 2279 .max_access_size = 4, 2280 }, 2281 }; 2282 2283 static const MemoryRegionOps b1_ops = { 2284 .read = vmxnet3_io_bar1_read, 2285 .write = vmxnet3_io_bar1_write, 2286 .endianness = DEVICE_LITTLE_ENDIAN, 2287 .impl = { 2288 .min_access_size = 4, 2289 .max_access_size = 4, 2290 }, 2291 }; 2292 2293 static SaveVMHandlers savevm_vmxnet3_msix = { 2294 .save_state = vmxnet3_msix_save, 2295 .load_state = vmxnet3_msix_load, 2296 }; 2297 2298 static uint64_t vmxnet3_device_serial_num(VMXNET3State *s) 2299 { 2300 uint64_t dsn_payload; 2301 uint8_t *dsnp = (uint8_t *)&dsn_payload; 2302 2303 dsnp[0] = 0xfe; 2304 dsnp[1] = s->conf.macaddr.a[3]; 2305 dsnp[2] = s->conf.macaddr.a[4]; 2306 dsnp[3] = s->conf.macaddr.a[5]; 2307 dsnp[4] = s->conf.macaddr.a[0]; 2308 dsnp[5] = s->conf.macaddr.a[1]; 2309 dsnp[6] = s->conf.macaddr.a[2]; 2310 dsnp[7] = 0xff; 2311 return dsn_payload; 2312 } 2313 2314 2315 #define VMXNET3_USE_64BIT (true) 2316 #define VMXNET3_PER_VECTOR_MASK (false) 2317 2318 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp) 2319 { 2320 DeviceState *dev = DEVICE(pci_dev); 2321 VMXNET3State *s = VMXNET3(pci_dev); 2322 int ret; 2323 2324 VMW_CBPRN("Starting init..."); 2325 2326 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s, 2327 "vmxnet3-b0", VMXNET3_PT_REG_SIZE); 2328 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX, 2329 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 2330 2331 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s, 2332 "vmxnet3-b1", VMXNET3_VD_REG_SIZE); 2333 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX, 2334 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1); 2335 2336 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar", 2337 VMXNET3_MSIX_BAR_SIZE); 2338 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX, 2339 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar); 2340 2341 vmxnet3_reset_interrupt_states(s); 2342 2343 /* Interrupt pin A */ 2344 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01; 2345 2346 ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS, 2347 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL); 2348 /* Any error other than -ENOTSUP(board's MSI support is broken) 2349 * is a programming error. Fall back to INTx silently on -ENOTSUP */ 2350 assert(!ret || ret == -ENOTSUP); 2351 2352 if (!vmxnet3_init_msix(s)) { 2353 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent."); 2354 } 2355 2356 vmxnet3_net_init(s); 2357 2358 if (pci_is_express(pci_dev)) { 2359 if (pci_bus_is_express(pci_get_bus(pci_dev))) { 2360 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET); 2361 } 2362 2363 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET, 2364 vmxnet3_device_serial_num(s)); 2365 } 2366 2367 register_savevm_live(dev, "vmxnet3-msix", -1, 1, &savevm_vmxnet3_msix, s); 2368 } 2369 2370 static void vmxnet3_instance_init(Object *obj) 2371 { 2372 VMXNET3State *s = VMXNET3(obj); 2373 device_add_bootindex_property(obj, &s->conf.bootindex, 2374 "bootindex", "/ethernet-phy@0", 2375 DEVICE(obj), NULL); 2376 } 2377 2378 static void vmxnet3_pci_uninit(PCIDevice *pci_dev) 2379 { 2380 DeviceState *dev = DEVICE(pci_dev); 2381 VMXNET3State *s = VMXNET3(pci_dev); 2382 2383 VMW_CBPRN("Starting uninit..."); 2384 2385 unregister_savevm(dev, "vmxnet3-msix", s); 2386 2387 vmxnet3_net_uninit(s); 2388 2389 vmxnet3_cleanup_msix(s); 2390 2391 vmxnet3_cleanup_msi(s); 2392 } 2393 2394 static void vmxnet3_qdev_reset(DeviceState *dev) 2395 { 2396 PCIDevice *d = PCI_DEVICE(dev); 2397 VMXNET3State *s = VMXNET3(d); 2398 2399 VMW_CBPRN("Starting QDEV reset..."); 2400 vmxnet3_reset(s); 2401 } 2402 2403 static bool vmxnet3_mc_list_needed(void *opaque) 2404 { 2405 return true; 2406 } 2407 2408 static int vmxnet3_mcast_list_pre_load(void *opaque) 2409 { 2410 VMXNET3State *s = opaque; 2411 2412 s->mcast_list = g_malloc(s->mcast_list_buff_size); 2413 2414 return 0; 2415 } 2416 2417 2418 static int vmxnet3_pre_save(void *opaque) 2419 { 2420 VMXNET3State *s = opaque; 2421 2422 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr); 2423 2424 return 0; 2425 } 2426 2427 static const VMStateDescription vmxstate_vmxnet3_mcast_list = { 2428 .name = "vmxnet3/mcast_list", 2429 .version_id = 1, 2430 .minimum_version_id = 1, 2431 .pre_load = vmxnet3_mcast_list_pre_load, 2432 .needed = vmxnet3_mc_list_needed, 2433 .fields = (VMStateField[]) { 2434 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 2435 mcast_list_buff_size), 2436 VMSTATE_END_OF_LIST() 2437 } 2438 }; 2439 2440 static const VMStateDescription vmstate_vmxnet3_ring = { 2441 .name = "vmxnet3-ring", 2442 .version_id = 0, 2443 .fields = (VMStateField[]) { 2444 VMSTATE_UINT64(pa, Vmxnet3Ring), 2445 VMSTATE_UINT32(size, Vmxnet3Ring), 2446 VMSTATE_UINT32(cell_size, Vmxnet3Ring), 2447 VMSTATE_UINT32(next, Vmxnet3Ring), 2448 VMSTATE_UINT8(gen, Vmxnet3Ring), 2449 VMSTATE_END_OF_LIST() 2450 } 2451 }; 2452 2453 static const VMStateDescription vmstate_vmxnet3_tx_stats = { 2454 .name = "vmxnet3-tx-stats", 2455 .version_id = 0, 2456 .fields = (VMStateField[]) { 2457 VMSTATE_UINT64(TSOPktsTxOK, struct UPT1_TxStats), 2458 VMSTATE_UINT64(TSOBytesTxOK, struct UPT1_TxStats), 2459 VMSTATE_UINT64(ucastPktsTxOK, struct UPT1_TxStats), 2460 VMSTATE_UINT64(ucastBytesTxOK, struct UPT1_TxStats), 2461 VMSTATE_UINT64(mcastPktsTxOK, struct UPT1_TxStats), 2462 VMSTATE_UINT64(mcastBytesTxOK, struct UPT1_TxStats), 2463 VMSTATE_UINT64(bcastPktsTxOK, struct UPT1_TxStats), 2464 VMSTATE_UINT64(bcastBytesTxOK, struct UPT1_TxStats), 2465 VMSTATE_UINT64(pktsTxError, struct UPT1_TxStats), 2466 VMSTATE_UINT64(pktsTxDiscard, struct UPT1_TxStats), 2467 VMSTATE_END_OF_LIST() 2468 } 2469 }; 2470 2471 static const VMStateDescription vmstate_vmxnet3_txq_descr = { 2472 .name = "vmxnet3-txq-descr", 2473 .version_id = 0, 2474 .fields = (VMStateField[]) { 2475 VMSTATE_STRUCT(tx_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring, 2476 Vmxnet3Ring), 2477 VMSTATE_STRUCT(comp_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring, 2478 Vmxnet3Ring), 2479 VMSTATE_UINT8(intr_idx, Vmxnet3TxqDescr), 2480 VMSTATE_UINT64(tx_stats_pa, Vmxnet3TxqDescr), 2481 VMSTATE_STRUCT(txq_stats, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_tx_stats, 2482 struct UPT1_TxStats), 2483 VMSTATE_END_OF_LIST() 2484 } 2485 }; 2486 2487 static const VMStateDescription vmstate_vmxnet3_rx_stats = { 2488 .name = "vmxnet3-rx-stats", 2489 .version_id = 0, 2490 .fields = (VMStateField[]) { 2491 VMSTATE_UINT64(LROPktsRxOK, struct UPT1_RxStats), 2492 VMSTATE_UINT64(LROBytesRxOK, struct UPT1_RxStats), 2493 VMSTATE_UINT64(ucastPktsRxOK, struct UPT1_RxStats), 2494 VMSTATE_UINT64(ucastBytesRxOK, struct UPT1_RxStats), 2495 VMSTATE_UINT64(mcastPktsRxOK, struct UPT1_RxStats), 2496 VMSTATE_UINT64(mcastBytesRxOK, struct UPT1_RxStats), 2497 VMSTATE_UINT64(bcastPktsRxOK, struct UPT1_RxStats), 2498 VMSTATE_UINT64(bcastBytesRxOK, struct UPT1_RxStats), 2499 VMSTATE_UINT64(pktsRxOutOfBuf, struct UPT1_RxStats), 2500 VMSTATE_UINT64(pktsRxError, struct UPT1_RxStats), 2501 VMSTATE_END_OF_LIST() 2502 } 2503 }; 2504 2505 static const VMStateDescription vmstate_vmxnet3_rxq_descr = { 2506 .name = "vmxnet3-rxq-descr", 2507 .version_id = 0, 2508 .fields = (VMStateField[]) { 2509 VMSTATE_STRUCT_ARRAY(rx_ring, Vmxnet3RxqDescr, 2510 VMXNET3_RX_RINGS_PER_QUEUE, 0, 2511 vmstate_vmxnet3_ring, Vmxnet3Ring), 2512 VMSTATE_STRUCT(comp_ring, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_ring, 2513 Vmxnet3Ring), 2514 VMSTATE_UINT8(intr_idx, Vmxnet3RxqDescr), 2515 VMSTATE_UINT64(rx_stats_pa, Vmxnet3RxqDescr), 2516 VMSTATE_STRUCT(rxq_stats, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_rx_stats, 2517 struct UPT1_RxStats), 2518 VMSTATE_END_OF_LIST() 2519 } 2520 }; 2521 2522 static int vmxnet3_post_load(void *opaque, int version_id) 2523 { 2524 VMXNET3State *s = opaque; 2525 PCIDevice *d = PCI_DEVICE(s); 2526 2527 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), 2528 s->max_tx_frags, s->peer_has_vhdr); 2529 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); 2530 2531 if (s->msix_used) { 2532 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) { 2533 VMW_WRPRN("Failed to re-use MSI-X vectors"); 2534 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2535 s->msix_used = false; 2536 return -1; 2537 } 2538 } 2539 2540 vmxnet3_validate_queues(s); 2541 vmxnet3_validate_interrupts(s); 2542 2543 return 0; 2544 } 2545 2546 static const VMStateDescription vmstate_vmxnet3_int_state = { 2547 .name = "vmxnet3-int-state", 2548 .version_id = 0, 2549 .fields = (VMStateField[]) { 2550 VMSTATE_BOOL(is_masked, Vmxnet3IntState), 2551 VMSTATE_BOOL(is_pending, Vmxnet3IntState), 2552 VMSTATE_BOOL(is_asserted, Vmxnet3IntState), 2553 VMSTATE_END_OF_LIST() 2554 } 2555 }; 2556 2557 static bool vmxnet3_vmstate_need_pcie_device(void *opaque) 2558 { 2559 VMXNET3State *s = VMXNET3(opaque); 2560 2561 return !(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE); 2562 } 2563 2564 static bool vmxnet3_vmstate_test_pci_device(void *opaque, int version_id) 2565 { 2566 return !vmxnet3_vmstate_need_pcie_device(opaque); 2567 } 2568 2569 static const VMStateDescription vmstate_vmxnet3_pcie_device = { 2570 .name = "vmxnet3/pcie", 2571 .version_id = 1, 2572 .minimum_version_id = 1, 2573 .needed = vmxnet3_vmstate_need_pcie_device, 2574 .fields = (VMStateField[]) { 2575 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State), 2576 VMSTATE_END_OF_LIST() 2577 } 2578 }; 2579 2580 static const VMStateDescription vmstate_vmxnet3 = { 2581 .name = "vmxnet3", 2582 .version_id = 1, 2583 .minimum_version_id = 1, 2584 .pre_save = vmxnet3_pre_save, 2585 .post_load = vmxnet3_post_load, 2586 .fields = (VMStateField[]) { 2587 VMSTATE_STRUCT_TEST(parent_obj, VMXNET3State, 2588 vmxnet3_vmstate_test_pci_device, 0, 2589 vmstate_pci_device, PCIDevice), 2590 VMSTATE_BOOL(rx_packets_compound, VMXNET3State), 2591 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State), 2592 VMSTATE_BOOL(lro_supported, VMXNET3State), 2593 VMSTATE_UINT32(rx_mode, VMXNET3State), 2594 VMSTATE_UINT32(mcast_list_len, VMXNET3State), 2595 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State), 2596 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE), 2597 VMSTATE_UINT32(mtu, VMXNET3State), 2598 VMSTATE_UINT16(max_rx_frags, VMXNET3State), 2599 VMSTATE_UINT32(max_tx_frags, VMXNET3State), 2600 VMSTATE_UINT8(event_int_idx, VMXNET3State), 2601 VMSTATE_BOOL(auto_int_masking, VMXNET3State), 2602 VMSTATE_UINT8(txq_num, VMXNET3State), 2603 VMSTATE_UINT8(rxq_num, VMXNET3State), 2604 VMSTATE_UINT32(device_active, VMXNET3State), 2605 VMSTATE_UINT32(last_command, VMXNET3State), 2606 VMSTATE_UINT32(link_status_and_speed, VMXNET3State), 2607 VMSTATE_UINT32(temp_mac, VMXNET3State), 2608 VMSTATE_UINT64(drv_shmem, VMXNET3State), 2609 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State), 2610 2611 VMSTATE_STRUCT_ARRAY(txq_descr, VMXNET3State, 2612 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, vmstate_vmxnet3_txq_descr, 2613 Vmxnet3TxqDescr), 2614 VMSTATE_STRUCT_ARRAY(rxq_descr, VMXNET3State, 2615 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, vmstate_vmxnet3_rxq_descr, 2616 Vmxnet3RxqDescr), 2617 VMSTATE_STRUCT_ARRAY(interrupt_states, VMXNET3State, 2618 VMXNET3_MAX_INTRS, 0, vmstate_vmxnet3_int_state, 2619 Vmxnet3IntState), 2620 2621 VMSTATE_END_OF_LIST() 2622 }, 2623 .subsections = (const VMStateDescription*[]) { 2624 &vmxstate_vmxnet3_mcast_list, 2625 &vmstate_vmxnet3_pcie_device, 2626 NULL 2627 } 2628 }; 2629 2630 static Property vmxnet3_properties[] = { 2631 DEFINE_NIC_PROPERTIES(VMXNET3State, conf), 2632 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags, 2633 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false), 2634 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags, 2635 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false), 2636 DEFINE_PROP_END_OF_LIST(), 2637 }; 2638 2639 static void vmxnet3_realize(DeviceState *qdev, Error **errp) 2640 { 2641 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev); 2642 PCIDevice *pci_dev = PCI_DEVICE(qdev); 2643 VMXNET3State *s = VMXNET3(qdev); 2644 2645 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) { 2646 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2647 } 2648 2649 vc->parent_dc_realize(qdev, errp); 2650 } 2651 2652 static void vmxnet3_class_init(ObjectClass *class, void *data) 2653 { 2654 DeviceClass *dc = DEVICE_CLASS(class); 2655 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 2656 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class); 2657 2658 c->realize = vmxnet3_pci_realize; 2659 c->exit = vmxnet3_pci_uninit; 2660 c->vendor_id = PCI_VENDOR_ID_VMWARE; 2661 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2662 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION; 2663 c->romfile = "efi-vmxnet3.rom"; 2664 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 2665 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 2666 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2667 device_class_set_parent_realize(dc, vmxnet3_realize, 2668 &vc->parent_dc_realize); 2669 dc->desc = "VMWare Paravirtualized Ethernet v3"; 2670 dc->reset = vmxnet3_qdev_reset; 2671 dc->vmsd = &vmstate_vmxnet3; 2672 dc->props = vmxnet3_properties; 2673 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 2674 } 2675 2676 static const TypeInfo vmxnet3_info = { 2677 .name = TYPE_VMXNET3, 2678 .parent = TYPE_PCI_DEVICE, 2679 .class_size = sizeof(VMXNET3Class), 2680 .instance_size = sizeof(VMXNET3State), 2681 .class_init = vmxnet3_class_init, 2682 .instance_init = vmxnet3_instance_init, 2683 .interfaces = (InterfaceInfo[]) { 2684 { INTERFACE_PCIE_DEVICE }, 2685 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2686 { } 2687 }, 2688 }; 2689 2690 static void vmxnet3_register_types(void) 2691 { 2692 VMW_CBPRN("vmxnet3_register_types called..."); 2693 type_register_static(&vmxnet3_info); 2694 } 2695 2696 type_init(vmxnet3_register_types) 2697