1 /* 2 * QEMU VMWARE VMXNET3 paravirtual NIC 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: 9 * Dmitry Fleytman <dmitry@daynix.com> 10 * Tamir Shomer <tamirs@daynix.com> 11 * Yan Vugenfirer <yan@daynix.com> 12 * 13 * This work is licensed under the terms of the GNU GPL, version 2. 14 * See the COPYING file in the top-level directory. 15 * 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/hw.h" 20 #include "hw/pci/pci.h" 21 #include "net/tap.h" 22 #include "net/checksum.h" 23 #include "sysemu/sysemu.h" 24 #include "qemu-common.h" 25 #include "qemu/bswap.h" 26 #include "hw/pci/msix.h" 27 #include "hw/pci/msi.h" 28 #include "migration/register.h" 29 30 #include "vmxnet3.h" 31 #include "vmxnet3_defs.h" 32 #include "vmxnet_debug.h" 33 #include "vmware_utils.h" 34 #include "net_tx_pkt.h" 35 #include "net_rx_pkt.h" 36 37 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1 38 #define VMXNET3_MSIX_BAR_SIZE 0x2000 39 #define MIN_BUF_SIZE 60 40 41 /* Compatibility flags for migration */ 42 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0 43 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \ 44 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT) 45 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1 46 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \ 47 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT) 48 49 #define VMXNET3_EXP_EP_OFFSET (0x48) 50 #define VMXNET3_MSI_OFFSET(s) \ 51 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84) 52 #define VMXNET3_MSIX_OFFSET(s) \ 53 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c) 54 #define VMXNET3_DSN_OFFSET (0x100) 55 56 #define VMXNET3_BAR0_IDX (0) 57 #define VMXNET3_BAR1_IDX (1) 58 #define VMXNET3_MSIX_BAR_IDX (2) 59 60 #define VMXNET3_OFF_MSIX_TABLE (0x000) 61 #define VMXNET3_OFF_MSIX_PBA(s) \ 62 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000) 63 64 /* Link speed in Mbps should be shifted by 16 */ 65 #define VMXNET3_LINK_SPEED (1000 << 16) 66 67 /* Link status: 1 - up, 0 - down. */ 68 #define VMXNET3_LINK_STATUS_UP 0x1 69 70 /* Least significant bit should be set for revision and version */ 71 #define VMXNET3_UPT_REVISION 0x1 72 #define VMXNET3_DEVICE_REVISION 0x1 73 74 /* Number of interrupt vectors for non-MSIx modes */ 75 #define VMXNET3_MAX_NMSIX_INTRS (1) 76 77 /* Macros for rings descriptors access */ 78 #define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \ 79 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 80 81 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \ 82 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value))) 83 84 #define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \ 85 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 86 87 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \ 88 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 89 90 #define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \ 91 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 92 93 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \ 94 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 95 96 #define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \ 97 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 98 99 #define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \ 100 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 101 102 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \ 103 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 104 105 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \ 106 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 107 108 /* Macros for guest driver shared area access */ 109 #define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \ 110 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 111 112 #define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \ 113 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 114 115 #define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \ 116 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val)) 117 118 #define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \ 119 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 120 121 #define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \ 122 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 123 124 #define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \ 125 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l)) 126 127 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag)) 128 129 typedef struct VMXNET3Class { 130 PCIDeviceClass parent_class; 131 DeviceRealize parent_dc_realize; 132 } VMXNET3Class; 133 134 #define VMXNET3_DEVICE_CLASS(klass) \ 135 OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3) 136 #define VMXNET3_DEVICE_GET_CLASS(obj) \ 137 OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3) 138 139 static inline void vmxnet3_ring_init(PCIDevice *d, 140 Vmxnet3Ring *ring, 141 hwaddr pa, 142 uint32_t size, 143 uint32_t cell_size, 144 bool zero_region) 145 { 146 ring->pa = pa; 147 ring->size = size; 148 ring->cell_size = cell_size; 149 ring->gen = VMXNET3_INIT_GEN; 150 ring->next = 0; 151 152 if (zero_region) { 153 vmw_shmem_set(d, pa, 0, size * cell_size); 154 } 155 } 156 157 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \ 158 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \ 159 (ring_name), (ridx), \ 160 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next) 161 162 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring) 163 { 164 if (++ring->next >= ring->size) { 165 ring->next = 0; 166 ring->gen ^= 1; 167 } 168 } 169 170 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring) 171 { 172 if (ring->next-- == 0) { 173 ring->next = ring->size - 1; 174 ring->gen ^= 1; 175 } 176 } 177 178 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring) 179 { 180 return ring->pa + ring->next * ring->cell_size; 181 } 182 183 static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring, 184 void *buff) 185 { 186 vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 187 } 188 189 static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring, 190 void *buff) 191 { 192 vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 193 } 194 195 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring) 196 { 197 return ring->next; 198 } 199 200 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring) 201 { 202 return ring->gen; 203 } 204 205 /* Debug trace-related functions */ 206 static inline void 207 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr) 208 { 209 VMW_PKPRN("TX DESCR: " 210 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 211 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, " 212 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d", 213 descr->addr, descr->len, descr->gen, descr->rsvd, 214 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om, 215 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci); 216 } 217 218 static inline void 219 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr) 220 { 221 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, " 222 "csum_start: %d, csum_offset: %d", 223 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size, 224 vhdr->csum_start, vhdr->csum_offset); 225 } 226 227 static inline void 228 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr) 229 { 230 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 231 "dtype: %d, ext1: %d, btype: %d", 232 descr->addr, descr->len, descr->gen, 233 descr->rsvd, descr->dtype, descr->ext1, descr->btype); 234 } 235 236 /* Interrupt management */ 237 238 /* 239 * This function returns sign whether interrupt line is in asserted state 240 * This depends on the type of interrupt used. For INTX interrupt line will 241 * be asserted until explicit deassertion, for MSI(X) interrupt line will 242 * be deasserted automatically due to notification semantics of the MSI(X) 243 * interrupts 244 */ 245 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx) 246 { 247 PCIDevice *d = PCI_DEVICE(s); 248 249 if (s->msix_used && msix_enabled(d)) { 250 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx); 251 msix_notify(d, int_idx); 252 return false; 253 } 254 if (msi_enabled(d)) { 255 VMW_IRPRN("Sending MSI notification for vector %u", int_idx); 256 msi_notify(d, int_idx); 257 return false; 258 } 259 260 VMW_IRPRN("Asserting line for interrupt %u", int_idx); 261 pci_irq_assert(d); 262 return true; 263 } 264 265 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx) 266 { 267 PCIDevice *d = PCI_DEVICE(s); 268 269 /* 270 * This function should never be called for MSI(X) interrupts 271 * because deassertion never required for message interrupts 272 */ 273 assert(!s->msix_used || !msix_enabled(d)); 274 /* 275 * This function should never be called for MSI(X) interrupts 276 * because deassertion never required for message interrupts 277 */ 278 assert(!msi_enabled(d)); 279 280 VMW_IRPRN("Deasserting line for interrupt %u", lidx); 281 pci_irq_deassert(d); 282 } 283 284 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx) 285 { 286 if (!s->interrupt_states[lidx].is_pending && 287 s->interrupt_states[lidx].is_asserted) { 288 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx); 289 _vmxnet3_deassert_interrupt_line(s, lidx); 290 s->interrupt_states[lidx].is_asserted = false; 291 return; 292 } 293 294 if (s->interrupt_states[lidx].is_pending && 295 !s->interrupt_states[lidx].is_masked && 296 !s->interrupt_states[lidx].is_asserted) { 297 VMW_IRPRN("New interrupt line state for index %d is UP", lidx); 298 s->interrupt_states[lidx].is_asserted = 299 _vmxnet3_assert_interrupt_line(s, lidx); 300 s->interrupt_states[lidx].is_pending = false; 301 return; 302 } 303 } 304 305 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx) 306 { 307 PCIDevice *d = PCI_DEVICE(s); 308 s->interrupt_states[lidx].is_pending = true; 309 vmxnet3_update_interrupt_line_state(s, lidx); 310 311 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) { 312 goto do_automask; 313 } 314 315 if (msi_enabled(d) && s->auto_int_masking) { 316 goto do_automask; 317 } 318 319 return; 320 321 do_automask: 322 s->interrupt_states[lidx].is_masked = true; 323 vmxnet3_update_interrupt_line_state(s, lidx); 324 } 325 326 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx) 327 { 328 return s->interrupt_states[lidx].is_asserted; 329 } 330 331 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx) 332 { 333 s->interrupt_states[int_idx].is_pending = false; 334 if (s->auto_int_masking) { 335 s->interrupt_states[int_idx].is_masked = true; 336 } 337 vmxnet3_update_interrupt_line_state(s, int_idx); 338 } 339 340 static void 341 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked) 342 { 343 s->interrupt_states[lidx].is_masked = is_masked; 344 vmxnet3_update_interrupt_line_state(s, lidx); 345 } 346 347 static bool vmxnet3_verify_driver_magic(PCIDevice *d, hwaddr dshmem) 348 { 349 return (VMXNET3_READ_DRV_SHARED32(d, dshmem, magic) == VMXNET3_REV1_MAGIC); 350 } 351 352 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF) 353 #define VMXNET3_MAKE_BYTE(byte_num, val) \ 354 (((uint32_t)((val) & 0xFF)) << (byte_num)*8) 355 356 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l) 357 { 358 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0); 359 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1); 360 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2); 361 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3); 362 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0); 363 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1); 364 365 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 366 367 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 368 } 369 370 static uint64_t vmxnet3_get_mac_low(MACAddr *addr) 371 { 372 return VMXNET3_MAKE_BYTE(0, addr->a[0]) | 373 VMXNET3_MAKE_BYTE(1, addr->a[1]) | 374 VMXNET3_MAKE_BYTE(2, addr->a[2]) | 375 VMXNET3_MAKE_BYTE(3, addr->a[3]); 376 } 377 378 static uint64_t vmxnet3_get_mac_high(MACAddr *addr) 379 { 380 return VMXNET3_MAKE_BYTE(0, addr->a[4]) | 381 VMXNET3_MAKE_BYTE(1, addr->a[5]); 382 } 383 384 static void 385 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx) 386 { 387 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring); 388 } 389 390 static inline void 391 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx) 392 { 393 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]); 394 } 395 396 static inline void 397 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx) 398 { 399 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring); 400 } 401 402 static void 403 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx) 404 { 405 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring); 406 } 407 408 static void 409 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx) 410 { 411 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring); 412 } 413 414 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx) 415 { 416 struct Vmxnet3_TxCompDesc txcq_descr; 417 PCIDevice *d = PCI_DEVICE(s); 418 419 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring); 420 421 memset(&txcq_descr, 0, sizeof(txcq_descr)); 422 txcq_descr.txdIdx = tx_ridx; 423 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring); 424 txcq_descr.val1 = cpu_to_le32(txcq_descr.val1); 425 txcq_descr.val2 = cpu_to_le32(txcq_descr.val2); 426 vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr); 427 428 /* Flush changes in TX descriptor before changing the counter value */ 429 smp_wmb(); 430 431 vmxnet3_inc_tx_completion_counter(s, qidx); 432 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx); 433 } 434 435 static bool 436 vmxnet3_setup_tx_offloads(VMXNET3State *s) 437 { 438 switch (s->offload_mode) { 439 case VMXNET3_OM_NONE: 440 net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0); 441 break; 442 443 case VMXNET3_OM_CSUM: 444 net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0); 445 VMW_PKPRN("L4 CSO requested\n"); 446 break; 447 448 case VMXNET3_OM_TSO: 449 net_tx_pkt_build_vheader(s->tx_pkt, true, true, 450 s->cso_or_gso_size); 451 net_tx_pkt_update_ip_checksums(s->tx_pkt); 452 VMW_PKPRN("GSO offload requested."); 453 break; 454 455 default: 456 g_assert_not_reached(); 457 return false; 458 } 459 460 return true; 461 } 462 463 static void 464 vmxnet3_tx_retrieve_metadata(VMXNET3State *s, 465 const struct Vmxnet3_TxDesc *txd) 466 { 467 s->offload_mode = txd->om; 468 s->cso_or_gso_size = txd->msscof; 469 s->tci = txd->tci; 470 s->needs_vlan = txd->ti; 471 } 472 473 typedef enum { 474 VMXNET3_PKT_STATUS_OK, 475 VMXNET3_PKT_STATUS_ERROR, 476 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */ 477 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */ 478 } Vmxnet3PktStatus; 479 480 static void 481 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx, 482 Vmxnet3PktStatus status) 483 { 484 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt); 485 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats; 486 487 switch (status) { 488 case VMXNET3_PKT_STATUS_OK: 489 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) { 490 case ETH_PKT_BCAST: 491 stats->bcastPktsTxOK++; 492 stats->bcastBytesTxOK += tot_len; 493 break; 494 case ETH_PKT_MCAST: 495 stats->mcastPktsTxOK++; 496 stats->mcastBytesTxOK += tot_len; 497 break; 498 case ETH_PKT_UCAST: 499 stats->ucastPktsTxOK++; 500 stats->ucastBytesTxOK += tot_len; 501 break; 502 default: 503 g_assert_not_reached(); 504 } 505 506 if (s->offload_mode == VMXNET3_OM_TSO) { 507 /* 508 * According to VMWARE headers this statistic is a number 509 * of packets after segmentation but since we don't have 510 * this information in QEMU model, the best we can do is to 511 * provide number of non-segmented packets 512 */ 513 stats->TSOPktsTxOK++; 514 stats->TSOBytesTxOK += tot_len; 515 } 516 break; 517 518 case VMXNET3_PKT_STATUS_DISCARD: 519 stats->pktsTxDiscard++; 520 break; 521 522 case VMXNET3_PKT_STATUS_ERROR: 523 stats->pktsTxError++; 524 break; 525 526 default: 527 g_assert_not_reached(); 528 } 529 } 530 531 static void 532 vmxnet3_on_rx_done_update_stats(VMXNET3State *s, 533 int qidx, 534 Vmxnet3PktStatus status) 535 { 536 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats; 537 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt); 538 539 switch (status) { 540 case VMXNET3_PKT_STATUS_OUT_OF_BUF: 541 stats->pktsRxOutOfBuf++; 542 break; 543 544 case VMXNET3_PKT_STATUS_ERROR: 545 stats->pktsRxError++; 546 break; 547 case VMXNET3_PKT_STATUS_OK: 548 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 549 case ETH_PKT_BCAST: 550 stats->bcastPktsRxOK++; 551 stats->bcastBytesRxOK += tot_len; 552 break; 553 case ETH_PKT_MCAST: 554 stats->mcastPktsRxOK++; 555 stats->mcastBytesRxOK += tot_len; 556 break; 557 case ETH_PKT_UCAST: 558 stats->ucastPktsRxOK++; 559 stats->ucastBytesRxOK += tot_len; 560 break; 561 default: 562 g_assert_not_reached(); 563 } 564 565 if (tot_len > s->mtu) { 566 stats->LROPktsRxOK++; 567 stats->LROBytesRxOK += tot_len; 568 } 569 break; 570 default: 571 g_assert_not_reached(); 572 } 573 } 574 575 static inline void 576 vmxnet3_ring_read_curr_txdesc(PCIDevice *pcidev, Vmxnet3Ring *ring, 577 struct Vmxnet3_TxDesc *txd) 578 { 579 vmxnet3_ring_read_curr_cell(pcidev, ring, txd); 580 txd->addr = le64_to_cpu(txd->addr); 581 txd->val1 = le32_to_cpu(txd->val1); 582 txd->val2 = le32_to_cpu(txd->val2); 583 } 584 585 static inline bool 586 vmxnet3_pop_next_tx_descr(VMXNET3State *s, 587 int qidx, 588 struct Vmxnet3_TxDesc *txd, 589 uint32_t *descr_idx) 590 { 591 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring; 592 PCIDevice *d = PCI_DEVICE(s); 593 594 vmxnet3_ring_read_curr_txdesc(d, ring, txd); 595 if (txd->gen == vmxnet3_ring_curr_gen(ring)) { 596 /* Only read after generation field verification */ 597 smp_rmb(); 598 /* Re-read to be sure we got the latest version */ 599 vmxnet3_ring_read_curr_txdesc(d, ring, txd); 600 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring); 601 *descr_idx = vmxnet3_ring_curr_cell_idx(ring); 602 vmxnet3_inc_tx_consumption_counter(s, qidx); 603 return true; 604 } 605 606 return false; 607 } 608 609 static bool 610 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx) 611 { 612 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK; 613 614 if (!vmxnet3_setup_tx_offloads(s)) { 615 status = VMXNET3_PKT_STATUS_ERROR; 616 goto func_exit; 617 } 618 619 /* debug prints */ 620 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt)); 621 net_tx_pkt_dump(s->tx_pkt); 622 623 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) { 624 status = VMXNET3_PKT_STATUS_DISCARD; 625 goto func_exit; 626 } 627 628 func_exit: 629 vmxnet3_on_tx_done_update_stats(s, qidx, status); 630 return (status == VMXNET3_PKT_STATUS_OK); 631 } 632 633 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx) 634 { 635 struct Vmxnet3_TxDesc txd; 636 uint32_t txd_idx; 637 uint32_t data_len; 638 hwaddr data_pa; 639 640 for (;;) { 641 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) { 642 break; 643 } 644 645 vmxnet3_dump_tx_descr(&txd); 646 647 if (!s->skip_current_tx_pkt) { 648 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE; 649 data_pa = txd.addr; 650 651 if (!net_tx_pkt_add_raw_fragment(s->tx_pkt, 652 data_pa, 653 data_len)) { 654 s->skip_current_tx_pkt = true; 655 } 656 } 657 658 if (s->tx_sop) { 659 vmxnet3_tx_retrieve_metadata(s, &txd); 660 s->tx_sop = false; 661 } 662 663 if (txd.eop) { 664 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) { 665 if (s->needs_vlan) { 666 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci); 667 } 668 669 vmxnet3_send_packet(s, qidx); 670 } else { 671 vmxnet3_on_tx_done_update_stats(s, qidx, 672 VMXNET3_PKT_STATUS_ERROR); 673 } 674 675 vmxnet3_complete_packet(s, qidx, txd_idx); 676 s->tx_sop = true; 677 s->skip_current_tx_pkt = false; 678 net_tx_pkt_reset(s->tx_pkt); 679 } 680 } 681 } 682 683 static inline void 684 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx, 685 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx) 686 { 687 PCIDevice *d = PCI_DEVICE(s); 688 689 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx]; 690 *didx = vmxnet3_ring_curr_cell_idx(ring); 691 vmxnet3_ring_read_curr_cell(d, ring, dbuf); 692 dbuf->addr = le64_to_cpu(dbuf->addr); 693 dbuf->val1 = le32_to_cpu(dbuf->val1); 694 dbuf->ext1 = le32_to_cpu(dbuf->ext1); 695 } 696 697 static inline uint8_t 698 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx) 699 { 700 return s->rxq_descr[qidx].rx_ring[ridx].gen; 701 } 702 703 static inline hwaddr 704 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen) 705 { 706 uint8_t ring_gen; 707 struct Vmxnet3_RxCompDesc rxcd; 708 709 hwaddr daddr = 710 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring); 711 712 pci_dma_read(PCI_DEVICE(s), 713 daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc)); 714 rxcd.val1 = le32_to_cpu(rxcd.val1); 715 rxcd.val2 = le32_to_cpu(rxcd.val2); 716 rxcd.val3 = le32_to_cpu(rxcd.val3); 717 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring); 718 719 if (rxcd.gen != ring_gen) { 720 *descr_gen = ring_gen; 721 vmxnet3_inc_rx_completion_counter(s, qidx); 722 return daddr; 723 } 724 725 return 0; 726 } 727 728 static inline void 729 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx) 730 { 731 vmxnet3_dec_rx_completion_counter(s, qidx); 732 } 733 734 #define RXQ_IDX (0) 735 #define RX_HEAD_BODY_RING (0) 736 #define RX_BODY_ONLY_RING (1) 737 738 static bool 739 vmxnet3_get_next_head_rx_descr(VMXNET3State *s, 740 struct Vmxnet3_RxDesc *descr_buf, 741 uint32_t *descr_idx, 742 uint32_t *ridx) 743 { 744 for (;;) { 745 uint32_t ring_gen; 746 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 747 descr_buf, descr_idx); 748 749 /* If no more free descriptors - return */ 750 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING); 751 if (descr_buf->gen != ring_gen) { 752 return false; 753 } 754 755 /* Only read after generation field verification */ 756 smp_rmb(); 757 /* Re-read to be sure we got the latest version */ 758 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 759 descr_buf, descr_idx); 760 761 /* Mark current descriptor as used/skipped */ 762 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 763 764 /* If this is what we are looking for - return */ 765 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) { 766 *ridx = RX_HEAD_BODY_RING; 767 return true; 768 } 769 } 770 } 771 772 static bool 773 vmxnet3_get_next_body_rx_descr(VMXNET3State *s, 774 struct Vmxnet3_RxDesc *d, 775 uint32_t *didx, 776 uint32_t *ridx) 777 { 778 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 779 780 /* Try to find corresponding descriptor in head/body ring */ 781 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) { 782 /* Only read after generation field verification */ 783 smp_rmb(); 784 /* Re-read to be sure we got the latest version */ 785 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 786 if (d->btype == VMXNET3_RXD_BTYPE_BODY) { 787 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 788 *ridx = RX_HEAD_BODY_RING; 789 return true; 790 } 791 } 792 793 /* 794 * If there is no free descriptors on head/body ring or next free 795 * descriptor is a head descriptor switch to body only ring 796 */ 797 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 798 799 /* If no more free descriptors - return */ 800 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) { 801 /* Only read after generation field verification */ 802 smp_rmb(); 803 /* Re-read to be sure we got the latest version */ 804 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 805 assert(d->btype == VMXNET3_RXD_BTYPE_BODY); 806 *ridx = RX_BODY_ONLY_RING; 807 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING); 808 return true; 809 } 810 811 return false; 812 } 813 814 static inline bool 815 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head, 816 struct Vmxnet3_RxDesc *descr_buf, 817 uint32_t *descr_idx, 818 uint32_t *ridx) 819 { 820 if (is_head || !s->rx_packets_compound) { 821 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx); 822 } else { 823 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx); 824 } 825 } 826 827 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID), 828 * the implementation always passes an RxCompDesc with a "Checksum 829 * calculated and found correct" to the OS (cnc=0 and tuc=1, see 830 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior. 831 * 832 * Therefore, if packet has the NEEDS_CSUM set, we must calculate 833 * and place a fully computed checksum into the tcp/udp header. 834 * Otherwise, the OS driver will receive a checksum-correct indication 835 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field 836 * having just the pseudo header csum value. 837 * 838 * While this is not a problem if packet is destined for local delivery, 839 * in the case the host OS performs forwarding, it will forward an 840 * incorrectly checksummed packet. 841 */ 842 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt, 843 const void *pkt_data, 844 size_t pkt_len) 845 { 846 struct virtio_net_hdr *vhdr; 847 bool isip4, isip6, istcp, isudp; 848 uint8_t *data; 849 int len; 850 851 if (!net_rx_pkt_has_virt_hdr(pkt)) { 852 return; 853 } 854 855 vhdr = net_rx_pkt_get_vhdr(pkt); 856 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 857 return; 858 } 859 860 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 861 if (!(isip4 || isip6) || !(istcp || isudp)) { 862 return; 863 } 864 865 vmxnet3_dump_virt_hdr(vhdr); 866 867 /* Validate packet len: csum_start + scum_offset + length of csum field */ 868 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) { 869 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, " 870 "cannot calculate checksum", 871 pkt_len, vhdr->csum_start, vhdr->csum_offset); 872 return; 873 } 874 875 data = (uint8_t *)pkt_data + vhdr->csum_start; 876 len = pkt_len - vhdr->csum_start; 877 /* Put the checksum obtained into the packet */ 878 stw_be_p(data + vhdr->csum_offset, 879 net_checksum_finish_nozero(net_checksum_add(len, data))); 880 881 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM; 882 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID; 883 } 884 885 static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt, 886 struct Vmxnet3_RxCompDesc *rxcd) 887 { 888 int csum_ok, is_gso; 889 bool isip4, isip6, istcp, isudp; 890 struct virtio_net_hdr *vhdr; 891 uint8_t offload_type; 892 893 if (net_rx_pkt_is_vlan_stripped(pkt)) { 894 rxcd->ts = 1; 895 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt); 896 } 897 898 if (!net_rx_pkt_has_virt_hdr(pkt)) { 899 goto nocsum; 900 } 901 902 vhdr = net_rx_pkt_get_vhdr(pkt); 903 /* 904 * Checksum is valid when lower level tell so or when lower level 905 * requires checksum offload telling that packet produced/bridged 906 * locally and did travel over network after last checksum calculation 907 * or production 908 */ 909 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) || 910 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM); 911 912 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN; 913 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0; 914 915 if (!csum_ok && !is_gso) { 916 goto nocsum; 917 } 918 919 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 920 if ((!istcp && !isudp) || (!isip4 && !isip6)) { 921 goto nocsum; 922 } 923 924 rxcd->cnc = 0; 925 rxcd->v4 = isip4 ? 1 : 0; 926 rxcd->v6 = isip6 ? 1 : 0; 927 rxcd->tcp = istcp ? 1 : 0; 928 rxcd->udp = isudp ? 1 : 0; 929 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1; 930 return; 931 932 nocsum: 933 rxcd->cnc = 1; 934 return; 935 } 936 937 static void 938 vmxnet3_pci_dma_writev(PCIDevice *pci_dev, 939 const struct iovec *iov, 940 size_t start_iov_off, 941 hwaddr target_addr, 942 size_t bytes_to_copy) 943 { 944 size_t curr_off = 0; 945 size_t copied = 0; 946 947 while (bytes_to_copy) { 948 if (start_iov_off < (curr_off + iov->iov_len)) { 949 size_t chunk_len = 950 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy); 951 952 pci_dma_write(pci_dev, target_addr + copied, 953 iov->iov_base + start_iov_off - curr_off, 954 chunk_len); 955 956 copied += chunk_len; 957 start_iov_off += chunk_len; 958 curr_off = start_iov_off; 959 bytes_to_copy -= chunk_len; 960 } else { 961 curr_off += iov->iov_len; 962 } 963 iov++; 964 } 965 } 966 967 static void 968 vmxnet3_pci_dma_write_rxcd(PCIDevice *pcidev, dma_addr_t pa, 969 struct Vmxnet3_RxCompDesc *rxcd) 970 { 971 rxcd->val1 = cpu_to_le32(rxcd->val1); 972 rxcd->val2 = cpu_to_le32(rxcd->val2); 973 rxcd->val3 = cpu_to_le32(rxcd->val3); 974 pci_dma_write(pcidev, pa, rxcd, sizeof(*rxcd)); 975 } 976 977 static bool 978 vmxnet3_indicate_packet(VMXNET3State *s) 979 { 980 struct Vmxnet3_RxDesc rxd; 981 PCIDevice *d = PCI_DEVICE(s); 982 bool is_head = true; 983 uint32_t rxd_idx; 984 uint32_t rx_ridx = 0; 985 986 struct Vmxnet3_RxCompDesc rxcd; 987 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN; 988 hwaddr new_rxcd_pa = 0; 989 hwaddr ready_rxcd_pa = 0; 990 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt); 991 size_t bytes_copied = 0; 992 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt); 993 uint16_t num_frags = 0; 994 size_t chunk_size; 995 996 net_rx_pkt_dump(s->rx_pkt); 997 998 while (bytes_left > 0) { 999 1000 /* cannot add more frags to packet */ 1001 if (num_frags == s->max_rx_frags) { 1002 break; 1003 } 1004 1005 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen); 1006 if (!new_rxcd_pa) { 1007 break; 1008 } 1009 1010 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) { 1011 break; 1012 } 1013 1014 chunk_size = MIN(bytes_left, rxd.len); 1015 vmxnet3_pci_dma_writev(d, data, bytes_copied, rxd.addr, chunk_size); 1016 bytes_copied += chunk_size; 1017 bytes_left -= chunk_size; 1018 1019 vmxnet3_dump_rx_descr(&rxd); 1020 1021 if (ready_rxcd_pa != 0) { 1022 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd); 1023 } 1024 1025 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc)); 1026 rxcd.rxdIdx = rxd_idx; 1027 rxcd.len = chunk_size; 1028 rxcd.sop = is_head; 1029 rxcd.gen = new_rxcd_gen; 1030 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num; 1031 1032 if (bytes_left == 0) { 1033 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd); 1034 } 1035 1036 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu " 1037 "sop %d csum_correct %lu", 1038 (unsigned long) rx_ridx, 1039 (unsigned long) rxcd.rxdIdx, 1040 (unsigned long) rxcd.len, 1041 (int) rxcd.sop, 1042 (unsigned long) rxcd.tuc); 1043 1044 is_head = false; 1045 ready_rxcd_pa = new_rxcd_pa; 1046 new_rxcd_pa = 0; 1047 num_frags++; 1048 } 1049 1050 if (ready_rxcd_pa != 0) { 1051 rxcd.eop = 1; 1052 rxcd.err = (bytes_left != 0); 1053 1054 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd); 1055 1056 /* Flush RX descriptor changes */ 1057 smp_wmb(); 1058 } 1059 1060 if (new_rxcd_pa != 0) { 1061 vmxnet3_revert_rxc_descr(s, RXQ_IDX); 1062 } 1063 1064 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx); 1065 1066 if (bytes_left == 0) { 1067 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK); 1068 return true; 1069 } else if (num_frags == s->max_rx_frags) { 1070 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR); 1071 return false; 1072 } else { 1073 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, 1074 VMXNET3_PKT_STATUS_OUT_OF_BUF); 1075 return false; 1076 } 1077 } 1078 1079 static void 1080 vmxnet3_io_bar0_write(void *opaque, hwaddr addr, 1081 uint64_t val, unsigned size) 1082 { 1083 VMXNET3State *s = opaque; 1084 1085 if (!s->device_active) { 1086 return; 1087 } 1088 1089 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD, 1090 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) { 1091 int tx_queue_idx = 1092 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD, 1093 VMXNET3_REG_ALIGN); 1094 assert(tx_queue_idx <= s->txq_num); 1095 vmxnet3_process_tx_queue(s, tx_queue_idx); 1096 return; 1097 } 1098 1099 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1100 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1101 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1102 VMXNET3_REG_ALIGN); 1103 1104 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val); 1105 1106 vmxnet3_on_interrupt_mask_changed(s, l, val); 1107 return; 1108 } 1109 1110 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD, 1111 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) || 1112 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2, 1113 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) { 1114 return; 1115 } 1116 1117 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d", 1118 (uint64_t) addr, val, size); 1119 } 1120 1121 static uint64_t 1122 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size) 1123 { 1124 VMXNET3State *s = opaque; 1125 1126 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1127 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1128 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1129 VMXNET3_REG_ALIGN); 1130 return s->interrupt_states[l].is_masked; 1131 } 1132 1133 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size); 1134 return 0; 1135 } 1136 1137 static void vmxnet3_reset_interrupt_states(VMXNET3State *s) 1138 { 1139 int i; 1140 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) { 1141 s->interrupt_states[i].is_asserted = false; 1142 s->interrupt_states[i].is_pending = false; 1143 s->interrupt_states[i].is_masked = true; 1144 } 1145 } 1146 1147 static void vmxnet3_reset_mac(VMXNET3State *s) 1148 { 1149 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a)); 1150 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 1151 } 1152 1153 static void vmxnet3_deactivate_device(VMXNET3State *s) 1154 { 1155 if (s->device_active) { 1156 VMW_CBPRN("Deactivating vmxnet3..."); 1157 net_tx_pkt_reset(s->tx_pkt); 1158 net_tx_pkt_uninit(s->tx_pkt); 1159 net_rx_pkt_uninit(s->rx_pkt); 1160 s->device_active = false; 1161 } 1162 } 1163 1164 static void vmxnet3_reset(VMXNET3State *s) 1165 { 1166 VMW_CBPRN("Resetting vmxnet3..."); 1167 1168 vmxnet3_deactivate_device(s); 1169 vmxnet3_reset_interrupt_states(s); 1170 s->drv_shmem = 0; 1171 s->tx_sop = true; 1172 s->skip_current_tx_pkt = false; 1173 } 1174 1175 static void vmxnet3_update_rx_mode(VMXNET3State *s) 1176 { 1177 PCIDevice *d = PCI_DEVICE(s); 1178 1179 s->rx_mode = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, 1180 devRead.rxFilterConf.rxMode); 1181 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode); 1182 } 1183 1184 static void vmxnet3_update_vlan_filters(VMXNET3State *s) 1185 { 1186 int i; 1187 PCIDevice *d = PCI_DEVICE(s); 1188 1189 /* Copy configuration from shared memory */ 1190 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, 1191 devRead.rxFilterConf.vfTable, 1192 s->vlan_table, 1193 sizeof(s->vlan_table)); 1194 1195 /* Invert byte order when needed */ 1196 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) { 1197 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]); 1198 } 1199 1200 /* Dump configuration for debugging purposes */ 1201 VMW_CFPRN("Configured VLANs:"); 1202 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) { 1203 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) { 1204 VMW_CFPRN("\tVLAN %d is present", i); 1205 } 1206 } 1207 } 1208 1209 static void vmxnet3_update_mcast_filters(VMXNET3State *s) 1210 { 1211 PCIDevice *d = PCI_DEVICE(s); 1212 1213 uint16_t list_bytes = 1214 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, 1215 devRead.rxFilterConf.mfTableLen); 1216 1217 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]); 1218 1219 s->mcast_list = g_realloc(s->mcast_list, list_bytes); 1220 if (!s->mcast_list) { 1221 if (s->mcast_list_len == 0) { 1222 VMW_CFPRN("Current multicast list is empty"); 1223 } else { 1224 VMW_ERPRN("Failed to allocate multicast list of %d elements", 1225 s->mcast_list_len); 1226 } 1227 s->mcast_list_len = 0; 1228 } else { 1229 int i; 1230 hwaddr mcast_list_pa = 1231 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, 1232 devRead.rxFilterConf.mfTablePA); 1233 1234 pci_dma_read(d, mcast_list_pa, s->mcast_list, list_bytes); 1235 1236 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len); 1237 for (i = 0; i < s->mcast_list_len; i++) { 1238 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a)); 1239 } 1240 } 1241 } 1242 1243 static void vmxnet3_setup_rx_filtering(VMXNET3State *s) 1244 { 1245 vmxnet3_update_rx_mode(s); 1246 vmxnet3_update_vlan_filters(s); 1247 vmxnet3_update_mcast_filters(s); 1248 } 1249 1250 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s) 1251 { 1252 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2); 1253 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode); 1254 return interrupt_mode; 1255 } 1256 1257 static void vmxnet3_fill_stats(VMXNET3State *s) 1258 { 1259 int i; 1260 PCIDevice *d = PCI_DEVICE(s); 1261 1262 if (!s->device_active) 1263 return; 1264 1265 for (i = 0; i < s->txq_num; i++) { 1266 pci_dma_write(d, 1267 s->txq_descr[i].tx_stats_pa, 1268 &s->txq_descr[i].txq_stats, 1269 sizeof(s->txq_descr[i].txq_stats)); 1270 } 1271 1272 for (i = 0; i < s->rxq_num; i++) { 1273 pci_dma_write(d, 1274 s->rxq_descr[i].rx_stats_pa, 1275 &s->rxq_descr[i].rxq_stats, 1276 sizeof(s->rxq_descr[i].rxq_stats)); 1277 } 1278 } 1279 1280 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s) 1281 { 1282 struct Vmxnet3_GOSInfo gos; 1283 PCIDevice *d = PCI_DEVICE(s); 1284 1285 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, devRead.misc.driverInfo.gos, 1286 &gos, sizeof(gos)); 1287 s->rx_packets_compound = 1288 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true; 1289 1290 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound); 1291 } 1292 1293 static void 1294 vmxnet3_dump_conf_descr(const char *name, 1295 struct Vmxnet3_VariableLenConfDesc *pm_descr) 1296 { 1297 VMW_CFPRN("%s descriptor dump: Version %u, Length %u", 1298 name, pm_descr->confVer, pm_descr->confLen); 1299 1300 }; 1301 1302 static void vmxnet3_update_pm_state(VMXNET3State *s) 1303 { 1304 struct Vmxnet3_VariableLenConfDesc pm_descr; 1305 PCIDevice *d = PCI_DEVICE(s); 1306 1307 pm_descr.confLen = 1308 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confLen); 1309 pm_descr.confVer = 1310 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confVer); 1311 pm_descr.confPA = 1312 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.pmConfDesc.confPA); 1313 1314 vmxnet3_dump_conf_descr("PM State", &pm_descr); 1315 } 1316 1317 static void vmxnet3_update_features(VMXNET3State *s) 1318 { 1319 uint32_t guest_features; 1320 int rxcso_supported; 1321 PCIDevice *d = PCI_DEVICE(s); 1322 1323 guest_features = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, 1324 devRead.misc.uptFeatures); 1325 1326 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM); 1327 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN); 1328 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO); 1329 1330 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d", 1331 s->lro_supported, rxcso_supported, 1332 s->rx_vlan_stripping); 1333 if (s->peer_has_vhdr) { 1334 qemu_set_offload(qemu_get_queue(s->nic)->peer, 1335 rxcso_supported, 1336 s->lro_supported, 1337 s->lro_supported, 1338 0, 1339 0); 1340 } 1341 } 1342 1343 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx) 1344 { 1345 return s->msix_used || msi_enabled(PCI_DEVICE(s)) 1346 || intx == pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1; 1347 } 1348 1349 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx) 1350 { 1351 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS; 1352 if (idx >= max_ints) { 1353 hw_error("Bad interrupt index: %d\n", idx); 1354 } 1355 } 1356 1357 static void vmxnet3_validate_interrupts(VMXNET3State *s) 1358 { 1359 int i; 1360 1361 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx); 1362 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx); 1363 1364 for (i = 0; i < s->txq_num; i++) { 1365 int idx = s->txq_descr[i].intr_idx; 1366 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx); 1367 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1368 } 1369 1370 for (i = 0; i < s->rxq_num; i++) { 1371 int idx = s->rxq_descr[i].intr_idx; 1372 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx); 1373 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1374 } 1375 } 1376 1377 static void vmxnet3_validate_queues(VMXNET3State *s) 1378 { 1379 /* 1380 * txq_num and rxq_num are total number of queues 1381 * configured by guest. These numbers must not 1382 * exceed corresponding maximal values. 1383 */ 1384 1385 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) { 1386 hw_error("Bad TX queues number: %d\n", s->txq_num); 1387 } 1388 1389 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) { 1390 hw_error("Bad RX queues number: %d\n", s->rxq_num); 1391 } 1392 } 1393 1394 static void vmxnet3_activate_device(VMXNET3State *s) 1395 { 1396 int i; 1397 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1; 1398 PCIDevice *d = PCI_DEVICE(s); 1399 hwaddr qdescr_table_pa; 1400 uint64_t pa; 1401 uint32_t size; 1402 1403 /* Verify configuration consistency */ 1404 if (!vmxnet3_verify_driver_magic(d, s->drv_shmem)) { 1405 VMW_ERPRN("Device configuration received from driver is invalid"); 1406 return; 1407 } 1408 1409 /* Verify if device is active */ 1410 if (s->device_active) { 1411 VMW_CFPRN("Vmxnet3 device is active"); 1412 return; 1413 } 1414 1415 vmxnet3_adjust_by_guest_type(s); 1416 vmxnet3_update_features(s); 1417 vmxnet3_update_pm_state(s); 1418 vmxnet3_setup_rx_filtering(s); 1419 /* Cache fields from shared memory */ 1420 s->mtu = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.misc.mtu); 1421 VMW_CFPRN("MTU is %u", s->mtu); 1422 1423 s->max_rx_frags = 1424 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, devRead.misc.maxNumRxSG); 1425 1426 if (s->max_rx_frags == 0) { 1427 s->max_rx_frags = 1; 1428 } 1429 1430 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags); 1431 1432 s->event_int_idx = 1433 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.eventIntrIdx); 1434 assert(vmxnet3_verify_intx(s, s->event_int_idx)); 1435 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx); 1436 1437 s->auto_int_masking = 1438 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.autoMask); 1439 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking); 1440 1441 s->txq_num = 1442 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numTxQueues); 1443 s->rxq_num = 1444 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numRxQueues); 1445 1446 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num); 1447 vmxnet3_validate_queues(s); 1448 1449 qdescr_table_pa = 1450 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.misc.queueDescPA); 1451 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa); 1452 1453 /* 1454 * Worst-case scenario is a packet that holds all TX rings space so 1455 * we calculate total size of all TX rings for max TX fragments number 1456 */ 1457 s->max_tx_frags = 0; 1458 1459 /* TX queues */ 1460 for (i = 0; i < s->txq_num; i++) { 1461 hwaddr qdescr_pa = 1462 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc); 1463 1464 /* Read interrupt number for this TX queue */ 1465 s->txq_descr[i].intr_idx = 1466 VMXNET3_READ_TX_QUEUE_DESCR8(d, qdescr_pa, conf.intrIdx); 1467 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx)); 1468 1469 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx); 1470 1471 /* Read rings memory locations for TX queues */ 1472 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA); 1473 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.txRingSize); 1474 1475 vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size, 1476 sizeof(struct Vmxnet3_TxDesc), false); 1477 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring); 1478 1479 s->max_tx_frags += size; 1480 1481 /* TXC ring */ 1482 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA); 1483 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.compRingSize); 1484 vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size, 1485 sizeof(struct Vmxnet3_TxCompDesc), true); 1486 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring); 1487 1488 s->txq_descr[i].tx_stats_pa = 1489 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats); 1490 1491 memset(&s->txq_descr[i].txq_stats, 0, 1492 sizeof(s->txq_descr[i].txq_stats)); 1493 1494 /* Fill device-managed parameters for queues */ 1495 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa, 1496 ctrl.txThreshold, 1497 VMXNET3_DEF_TX_THRESHOLD); 1498 } 1499 1500 /* Preallocate TX packet wrapper */ 1501 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags); 1502 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), 1503 s->max_tx_frags, s->peer_has_vhdr); 1504 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); 1505 1506 /* Read rings memory locations for RX queues */ 1507 for (i = 0; i < s->rxq_num; i++) { 1508 int j; 1509 hwaddr qd_pa = 1510 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) + 1511 i * sizeof(struct Vmxnet3_RxQueueDesc); 1512 1513 /* Read interrupt number for this RX queue */ 1514 s->rxq_descr[i].intr_idx = 1515 VMXNET3_READ_TX_QUEUE_DESCR8(d, qd_pa, conf.intrIdx); 1516 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx)); 1517 1518 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx); 1519 1520 /* Read rings memory locations */ 1521 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) { 1522 /* RX rings */ 1523 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]); 1524 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.rxRingSize[j]); 1525 vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size, 1526 sizeof(struct Vmxnet3_RxDesc), false); 1527 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d", 1528 i, j, pa, size); 1529 } 1530 1531 /* RXC ring */ 1532 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA); 1533 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.compRingSize); 1534 vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size, 1535 sizeof(struct Vmxnet3_RxCompDesc), true); 1536 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size); 1537 1538 s->rxq_descr[i].rx_stats_pa = 1539 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats); 1540 memset(&s->rxq_descr[i].rxq_stats, 0, 1541 sizeof(s->rxq_descr[i].rxq_stats)); 1542 } 1543 1544 vmxnet3_validate_interrupts(s); 1545 1546 /* Make sure everything is in place before device activation */ 1547 smp_wmb(); 1548 1549 vmxnet3_reset_mac(s); 1550 1551 s->device_active = true; 1552 } 1553 1554 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd) 1555 { 1556 s->last_command = cmd; 1557 1558 switch (cmd) { 1559 case VMXNET3_CMD_GET_PERM_MAC_HI: 1560 VMW_CBPRN("Set: Get upper part of permanent MAC"); 1561 break; 1562 1563 case VMXNET3_CMD_GET_PERM_MAC_LO: 1564 VMW_CBPRN("Set: Get lower part of permanent MAC"); 1565 break; 1566 1567 case VMXNET3_CMD_GET_STATS: 1568 VMW_CBPRN("Set: Get device statistics"); 1569 vmxnet3_fill_stats(s); 1570 break; 1571 1572 case VMXNET3_CMD_ACTIVATE_DEV: 1573 VMW_CBPRN("Set: Activating vmxnet3 device"); 1574 vmxnet3_activate_device(s); 1575 break; 1576 1577 case VMXNET3_CMD_UPDATE_RX_MODE: 1578 VMW_CBPRN("Set: Update rx mode"); 1579 vmxnet3_update_rx_mode(s); 1580 break; 1581 1582 case VMXNET3_CMD_UPDATE_VLAN_FILTERS: 1583 VMW_CBPRN("Set: Update VLAN filters"); 1584 vmxnet3_update_vlan_filters(s); 1585 break; 1586 1587 case VMXNET3_CMD_UPDATE_MAC_FILTERS: 1588 VMW_CBPRN("Set: Update MAC filters"); 1589 vmxnet3_update_mcast_filters(s); 1590 break; 1591 1592 case VMXNET3_CMD_UPDATE_FEATURE: 1593 VMW_CBPRN("Set: Update features"); 1594 vmxnet3_update_features(s); 1595 break; 1596 1597 case VMXNET3_CMD_UPDATE_PMCFG: 1598 VMW_CBPRN("Set: Update power management config"); 1599 vmxnet3_update_pm_state(s); 1600 break; 1601 1602 case VMXNET3_CMD_GET_LINK: 1603 VMW_CBPRN("Set: Get link"); 1604 break; 1605 1606 case VMXNET3_CMD_RESET_DEV: 1607 VMW_CBPRN("Set: Reset device"); 1608 vmxnet3_reset(s); 1609 break; 1610 1611 case VMXNET3_CMD_QUIESCE_DEV: 1612 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device"); 1613 vmxnet3_deactivate_device(s); 1614 break; 1615 1616 case VMXNET3_CMD_GET_CONF_INTR: 1617 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration"); 1618 break; 1619 1620 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1621 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - " 1622 "adaptive ring info flags"); 1623 break; 1624 1625 case VMXNET3_CMD_GET_DID_LO: 1626 VMW_CBPRN("Set: Get lower part of device ID"); 1627 break; 1628 1629 case VMXNET3_CMD_GET_DID_HI: 1630 VMW_CBPRN("Set: Get upper part of device ID"); 1631 break; 1632 1633 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1634 VMW_CBPRN("Set: Get device extra info"); 1635 break; 1636 1637 default: 1638 VMW_CBPRN("Received unknown command: %" PRIx64, cmd); 1639 break; 1640 } 1641 } 1642 1643 static uint64_t vmxnet3_get_command_status(VMXNET3State *s) 1644 { 1645 uint64_t ret; 1646 1647 switch (s->last_command) { 1648 case VMXNET3_CMD_ACTIVATE_DEV: 1649 ret = (s->device_active) ? 0 : 1; 1650 VMW_CFPRN("Device active: %" PRIx64, ret); 1651 break; 1652 1653 case VMXNET3_CMD_RESET_DEV: 1654 case VMXNET3_CMD_QUIESCE_DEV: 1655 case VMXNET3_CMD_GET_QUEUE_STATUS: 1656 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1657 ret = 0; 1658 break; 1659 1660 case VMXNET3_CMD_GET_LINK: 1661 ret = s->link_status_and_speed; 1662 VMW_CFPRN("Link and speed: %" PRIx64, ret); 1663 break; 1664 1665 case VMXNET3_CMD_GET_PERM_MAC_LO: 1666 ret = vmxnet3_get_mac_low(&s->perm_mac); 1667 break; 1668 1669 case VMXNET3_CMD_GET_PERM_MAC_HI: 1670 ret = vmxnet3_get_mac_high(&s->perm_mac); 1671 break; 1672 1673 case VMXNET3_CMD_GET_CONF_INTR: 1674 ret = vmxnet3_get_interrupt_config(s); 1675 break; 1676 1677 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1678 ret = VMXNET3_DISABLE_ADAPTIVE_RING; 1679 break; 1680 1681 case VMXNET3_CMD_GET_DID_LO: 1682 ret = PCI_DEVICE_ID_VMWARE_VMXNET3; 1683 break; 1684 1685 case VMXNET3_CMD_GET_DID_HI: 1686 ret = VMXNET3_DEVICE_REVISION; 1687 break; 1688 1689 default: 1690 VMW_WRPRN("Received request for unknown command: %x", s->last_command); 1691 ret = 0; 1692 break; 1693 } 1694 1695 return ret; 1696 } 1697 1698 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val) 1699 { 1700 uint32_t events; 1701 PCIDevice *d = PCI_DEVICE(s); 1702 1703 VMW_CBPRN("Setting events: 0x%x", val); 1704 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) | val; 1705 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events); 1706 } 1707 1708 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val) 1709 { 1710 PCIDevice *d = PCI_DEVICE(s); 1711 uint32_t events; 1712 1713 VMW_CBPRN("Clearing events: 0x%x", val); 1714 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) & ~val; 1715 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events); 1716 } 1717 1718 static void 1719 vmxnet3_io_bar1_write(void *opaque, 1720 hwaddr addr, 1721 uint64_t val, 1722 unsigned size) 1723 { 1724 VMXNET3State *s = opaque; 1725 1726 switch (addr) { 1727 /* Vmxnet3 Revision Report Selection */ 1728 case VMXNET3_REG_VRRS: 1729 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d", 1730 val, size); 1731 break; 1732 1733 /* UPT Version Report Selection */ 1734 case VMXNET3_REG_UVRS: 1735 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d", 1736 val, size); 1737 break; 1738 1739 /* Driver Shared Address Low */ 1740 case VMXNET3_REG_DSAL: 1741 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d", 1742 val, size); 1743 /* 1744 * Guest driver will first write the low part of the shared 1745 * memory address. We save it to temp variable and set the 1746 * shared address only after we get the high part 1747 */ 1748 if (val == 0) { 1749 vmxnet3_deactivate_device(s); 1750 } 1751 s->temp_shared_guest_driver_memory = val; 1752 s->drv_shmem = 0; 1753 break; 1754 1755 /* Driver Shared Address High */ 1756 case VMXNET3_REG_DSAH: 1757 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d", 1758 val, size); 1759 /* 1760 * Set the shared memory between guest driver and device. 1761 * We already should have low address part. 1762 */ 1763 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32); 1764 break; 1765 1766 /* Command */ 1767 case VMXNET3_REG_CMD: 1768 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d", 1769 val, size); 1770 vmxnet3_handle_command(s, val); 1771 break; 1772 1773 /* MAC Address Low */ 1774 case VMXNET3_REG_MACL: 1775 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d", 1776 val, size); 1777 s->temp_mac = val; 1778 break; 1779 1780 /* MAC Address High */ 1781 case VMXNET3_REG_MACH: 1782 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d", 1783 val, size); 1784 vmxnet3_set_variable_mac(s, val, s->temp_mac); 1785 break; 1786 1787 /* Interrupt Cause Register */ 1788 case VMXNET3_REG_ICR: 1789 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d", 1790 val, size); 1791 g_assert_not_reached(); 1792 break; 1793 1794 /* Event Cause Register */ 1795 case VMXNET3_REG_ECR: 1796 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d", 1797 val, size); 1798 vmxnet3_ack_events(s, val); 1799 break; 1800 1801 default: 1802 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d", 1803 addr, val, size); 1804 break; 1805 } 1806 } 1807 1808 static uint64_t 1809 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size) 1810 { 1811 VMXNET3State *s = opaque; 1812 uint64_t ret = 0; 1813 1814 switch (addr) { 1815 /* Vmxnet3 Revision Report Selection */ 1816 case VMXNET3_REG_VRRS: 1817 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size); 1818 ret = VMXNET3_DEVICE_REVISION; 1819 break; 1820 1821 /* UPT Version Report Selection */ 1822 case VMXNET3_REG_UVRS: 1823 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size); 1824 ret = VMXNET3_UPT_REVISION; 1825 break; 1826 1827 /* Command */ 1828 case VMXNET3_REG_CMD: 1829 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size); 1830 ret = vmxnet3_get_command_status(s); 1831 break; 1832 1833 /* MAC Address Low */ 1834 case VMXNET3_REG_MACL: 1835 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size); 1836 ret = vmxnet3_get_mac_low(&s->conf.macaddr); 1837 break; 1838 1839 /* MAC Address High */ 1840 case VMXNET3_REG_MACH: 1841 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size); 1842 ret = vmxnet3_get_mac_high(&s->conf.macaddr); 1843 break; 1844 1845 /* 1846 * Interrupt Cause Register 1847 * Used for legacy interrupts only so interrupt index always 0 1848 */ 1849 case VMXNET3_REG_ICR: 1850 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size); 1851 if (vmxnet3_interrupt_asserted(s, 0)) { 1852 vmxnet3_clear_interrupt(s, 0); 1853 ret = true; 1854 } else { 1855 ret = false; 1856 } 1857 break; 1858 1859 default: 1860 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size); 1861 break; 1862 } 1863 1864 return ret; 1865 } 1866 1867 static int 1868 vmxnet3_can_receive(NetClientState *nc) 1869 { 1870 VMXNET3State *s = qemu_get_nic_opaque(nc); 1871 return s->device_active && 1872 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP); 1873 } 1874 1875 static inline bool 1876 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data) 1877 { 1878 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK; 1879 if (IS_SPECIAL_VLAN_ID(vlan_tag)) { 1880 return true; 1881 } 1882 1883 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag); 1884 } 1885 1886 static bool 1887 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac) 1888 { 1889 int i; 1890 for (i = 0; i < s->mcast_list_len; i++) { 1891 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) { 1892 return true; 1893 } 1894 } 1895 return false; 1896 } 1897 1898 static bool 1899 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data, 1900 size_t size) 1901 { 1902 struct eth_header *ehdr = PKT_GET_ETH_HDR(data); 1903 1904 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) { 1905 return true; 1906 } 1907 1908 if (!vmxnet3_is_registered_vlan(s, data)) { 1909 return false; 1910 } 1911 1912 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 1913 case ETH_PKT_UCAST: 1914 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) { 1915 return false; 1916 } 1917 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) { 1918 return false; 1919 } 1920 break; 1921 1922 case ETH_PKT_BCAST: 1923 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) { 1924 return false; 1925 } 1926 break; 1927 1928 case ETH_PKT_MCAST: 1929 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) { 1930 return true; 1931 } 1932 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) { 1933 return false; 1934 } 1935 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) { 1936 return false; 1937 } 1938 break; 1939 1940 default: 1941 g_assert_not_reached(); 1942 } 1943 1944 return true; 1945 } 1946 1947 static ssize_t 1948 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1949 { 1950 VMXNET3State *s = qemu_get_nic_opaque(nc); 1951 size_t bytes_indicated; 1952 uint8_t min_buf[MIN_BUF_SIZE]; 1953 1954 if (!vmxnet3_can_receive(nc)) { 1955 VMW_PKPRN("Cannot receive now"); 1956 return -1; 1957 } 1958 1959 if (s->peer_has_vhdr) { 1960 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf); 1961 buf += sizeof(struct virtio_net_hdr); 1962 size -= sizeof(struct virtio_net_hdr); 1963 } 1964 1965 /* Pad to minimum Ethernet frame length */ 1966 if (size < sizeof(min_buf)) { 1967 memcpy(min_buf, buf, size); 1968 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1969 buf = min_buf; 1970 size = sizeof(min_buf); 1971 } 1972 1973 net_rx_pkt_set_packet_type(s->rx_pkt, 1974 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 1975 1976 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) { 1977 net_rx_pkt_set_protocols(s->rx_pkt, buf, size); 1978 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size); 1979 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping); 1980 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1; 1981 if (bytes_indicated < size) { 1982 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size); 1983 } 1984 } else { 1985 VMW_PKPRN("Packet dropped by RX filter"); 1986 bytes_indicated = size; 1987 } 1988 1989 assert(size > 0); 1990 assert(bytes_indicated != 0); 1991 return bytes_indicated; 1992 } 1993 1994 static void vmxnet3_set_link_status(NetClientState *nc) 1995 { 1996 VMXNET3State *s = qemu_get_nic_opaque(nc); 1997 1998 if (nc->link_down) { 1999 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP; 2000 } else { 2001 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP; 2002 } 2003 2004 vmxnet3_set_events(s, VMXNET3_ECR_LINK); 2005 vmxnet3_trigger_interrupt(s, s->event_int_idx); 2006 } 2007 2008 static NetClientInfo net_vmxnet3_info = { 2009 .type = NET_CLIENT_DRIVER_NIC, 2010 .size = sizeof(NICState), 2011 .receive = vmxnet3_receive, 2012 .link_status_changed = vmxnet3_set_link_status, 2013 }; 2014 2015 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s) 2016 { 2017 NetClientState *nc = qemu_get_queue(s->nic); 2018 2019 if (qemu_has_vnet_hdr(nc->peer)) { 2020 return true; 2021 } 2022 2023 return false; 2024 } 2025 2026 static void vmxnet3_net_uninit(VMXNET3State *s) 2027 { 2028 g_free(s->mcast_list); 2029 vmxnet3_deactivate_device(s); 2030 qemu_del_nic(s->nic); 2031 } 2032 2033 static void vmxnet3_net_init(VMXNET3State *s) 2034 { 2035 DeviceState *d = DEVICE(s); 2036 2037 VMW_CBPRN("vmxnet3_net_init called..."); 2038 2039 qemu_macaddr_default_if_unset(&s->conf.macaddr); 2040 2041 /* Windows guest will query the address that was set on init */ 2042 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a)); 2043 2044 s->mcast_list = NULL; 2045 s->mcast_list_len = 0; 2046 2047 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP; 2048 2049 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a)); 2050 2051 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf, 2052 object_get_typename(OBJECT(s)), 2053 d->id, s); 2054 2055 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s); 2056 s->tx_sop = true; 2057 s->skip_current_tx_pkt = false; 2058 s->tx_pkt = NULL; 2059 s->rx_pkt = NULL; 2060 s->rx_vlan_stripping = false; 2061 s->lro_supported = false; 2062 2063 if (s->peer_has_vhdr) { 2064 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer, 2065 sizeof(struct virtio_net_hdr)); 2066 2067 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1); 2068 } 2069 2070 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 2071 } 2072 2073 static void 2074 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors) 2075 { 2076 PCIDevice *d = PCI_DEVICE(s); 2077 int i; 2078 for (i = 0; i < num_vectors; i++) { 2079 msix_vector_unuse(d, i); 2080 } 2081 } 2082 2083 static bool 2084 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors) 2085 { 2086 PCIDevice *d = PCI_DEVICE(s); 2087 int i; 2088 for (i = 0; i < num_vectors; i++) { 2089 int res = msix_vector_use(d, i); 2090 if (0 > res) { 2091 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res); 2092 vmxnet3_unuse_msix_vectors(s, i); 2093 return false; 2094 } 2095 } 2096 return true; 2097 } 2098 2099 static bool 2100 vmxnet3_init_msix(VMXNET3State *s) 2101 { 2102 PCIDevice *d = PCI_DEVICE(s); 2103 int res = msix_init(d, VMXNET3_MAX_INTRS, 2104 &s->msix_bar, 2105 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE, 2106 &s->msix_bar, 2107 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s), 2108 VMXNET3_MSIX_OFFSET(s), NULL); 2109 2110 if (0 > res) { 2111 VMW_WRPRN("Failed to initialize MSI-X, error %d", res); 2112 s->msix_used = false; 2113 } else { 2114 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) { 2115 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res); 2116 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2117 s->msix_used = false; 2118 } else { 2119 s->msix_used = true; 2120 } 2121 } 2122 return s->msix_used; 2123 } 2124 2125 static void 2126 vmxnet3_cleanup_msix(VMXNET3State *s) 2127 { 2128 PCIDevice *d = PCI_DEVICE(s); 2129 2130 if (s->msix_used) { 2131 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS); 2132 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2133 } 2134 } 2135 2136 static void 2137 vmxnet3_cleanup_msi(VMXNET3State *s) 2138 { 2139 PCIDevice *d = PCI_DEVICE(s); 2140 2141 msi_uninit(d); 2142 } 2143 2144 static void 2145 vmxnet3_msix_save(QEMUFile *f, void *opaque) 2146 { 2147 PCIDevice *d = PCI_DEVICE(opaque); 2148 msix_save(d, f); 2149 } 2150 2151 static int 2152 vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id) 2153 { 2154 PCIDevice *d = PCI_DEVICE(opaque); 2155 msix_load(d, f); 2156 return 0; 2157 } 2158 2159 static const MemoryRegionOps b0_ops = { 2160 .read = vmxnet3_io_bar0_read, 2161 .write = vmxnet3_io_bar0_write, 2162 .endianness = DEVICE_LITTLE_ENDIAN, 2163 .impl = { 2164 .min_access_size = 4, 2165 .max_access_size = 4, 2166 }, 2167 }; 2168 2169 static const MemoryRegionOps b1_ops = { 2170 .read = vmxnet3_io_bar1_read, 2171 .write = vmxnet3_io_bar1_write, 2172 .endianness = DEVICE_LITTLE_ENDIAN, 2173 .impl = { 2174 .min_access_size = 4, 2175 .max_access_size = 4, 2176 }, 2177 }; 2178 2179 static SaveVMHandlers savevm_vmxnet3_msix = { 2180 .save_state = vmxnet3_msix_save, 2181 .load_state = vmxnet3_msix_load, 2182 }; 2183 2184 static uint64_t vmxnet3_device_serial_num(VMXNET3State *s) 2185 { 2186 uint64_t dsn_payload; 2187 uint8_t *dsnp = (uint8_t *)&dsn_payload; 2188 2189 dsnp[0] = 0xfe; 2190 dsnp[1] = s->conf.macaddr.a[3]; 2191 dsnp[2] = s->conf.macaddr.a[4]; 2192 dsnp[3] = s->conf.macaddr.a[5]; 2193 dsnp[4] = s->conf.macaddr.a[0]; 2194 dsnp[5] = s->conf.macaddr.a[1]; 2195 dsnp[6] = s->conf.macaddr.a[2]; 2196 dsnp[7] = 0xff; 2197 return dsn_payload; 2198 } 2199 2200 2201 #define VMXNET3_USE_64BIT (true) 2202 #define VMXNET3_PER_VECTOR_MASK (false) 2203 2204 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp) 2205 { 2206 DeviceState *dev = DEVICE(pci_dev); 2207 VMXNET3State *s = VMXNET3(pci_dev); 2208 int ret; 2209 2210 VMW_CBPRN("Starting init..."); 2211 2212 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s, 2213 "vmxnet3-b0", VMXNET3_PT_REG_SIZE); 2214 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX, 2215 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 2216 2217 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s, 2218 "vmxnet3-b1", VMXNET3_VD_REG_SIZE); 2219 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX, 2220 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1); 2221 2222 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar", 2223 VMXNET3_MSIX_BAR_SIZE); 2224 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX, 2225 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar); 2226 2227 vmxnet3_reset_interrupt_states(s); 2228 2229 /* Interrupt pin A */ 2230 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01; 2231 2232 ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS, 2233 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL); 2234 /* Any error other than -ENOTSUP(board's MSI support is broken) 2235 * is a programming error. Fall back to INTx silently on -ENOTSUP */ 2236 assert(!ret || ret == -ENOTSUP); 2237 2238 if (!vmxnet3_init_msix(s)) { 2239 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent."); 2240 } 2241 2242 vmxnet3_net_init(s); 2243 2244 if (pci_is_express(pci_dev)) { 2245 if (pci_bus_is_express(pci_get_bus(pci_dev))) { 2246 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET); 2247 } 2248 2249 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET, 2250 vmxnet3_device_serial_num(s)); 2251 } 2252 2253 register_savevm_live(dev, "vmxnet3-msix", -1, 1, &savevm_vmxnet3_msix, s); 2254 } 2255 2256 static void vmxnet3_instance_init(Object *obj) 2257 { 2258 VMXNET3State *s = VMXNET3(obj); 2259 device_add_bootindex_property(obj, &s->conf.bootindex, 2260 "bootindex", "/ethernet-phy@0", 2261 DEVICE(obj), NULL); 2262 } 2263 2264 static void vmxnet3_pci_uninit(PCIDevice *pci_dev) 2265 { 2266 DeviceState *dev = DEVICE(pci_dev); 2267 VMXNET3State *s = VMXNET3(pci_dev); 2268 2269 VMW_CBPRN("Starting uninit..."); 2270 2271 unregister_savevm(dev, "vmxnet3-msix", s); 2272 2273 vmxnet3_net_uninit(s); 2274 2275 vmxnet3_cleanup_msix(s); 2276 2277 vmxnet3_cleanup_msi(s); 2278 } 2279 2280 static void vmxnet3_qdev_reset(DeviceState *dev) 2281 { 2282 PCIDevice *d = PCI_DEVICE(dev); 2283 VMXNET3State *s = VMXNET3(d); 2284 2285 VMW_CBPRN("Starting QDEV reset..."); 2286 vmxnet3_reset(s); 2287 } 2288 2289 static bool vmxnet3_mc_list_needed(void *opaque) 2290 { 2291 return true; 2292 } 2293 2294 static int vmxnet3_mcast_list_pre_load(void *opaque) 2295 { 2296 VMXNET3State *s = opaque; 2297 2298 s->mcast_list = g_malloc(s->mcast_list_buff_size); 2299 2300 return 0; 2301 } 2302 2303 2304 static int vmxnet3_pre_save(void *opaque) 2305 { 2306 VMXNET3State *s = opaque; 2307 2308 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr); 2309 2310 return 0; 2311 } 2312 2313 static const VMStateDescription vmxstate_vmxnet3_mcast_list = { 2314 .name = "vmxnet3/mcast_list", 2315 .version_id = 1, 2316 .minimum_version_id = 1, 2317 .pre_load = vmxnet3_mcast_list_pre_load, 2318 .needed = vmxnet3_mc_list_needed, 2319 .fields = (VMStateField[]) { 2320 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 2321 mcast_list_buff_size), 2322 VMSTATE_END_OF_LIST() 2323 } 2324 }; 2325 2326 static const VMStateDescription vmstate_vmxnet3_ring = { 2327 .name = "vmxnet3-ring", 2328 .version_id = 0, 2329 .fields = (VMStateField[]) { 2330 VMSTATE_UINT64(pa, Vmxnet3Ring), 2331 VMSTATE_UINT32(size, Vmxnet3Ring), 2332 VMSTATE_UINT32(cell_size, Vmxnet3Ring), 2333 VMSTATE_UINT32(next, Vmxnet3Ring), 2334 VMSTATE_UINT8(gen, Vmxnet3Ring), 2335 VMSTATE_END_OF_LIST() 2336 } 2337 }; 2338 2339 static const VMStateDescription vmstate_vmxnet3_tx_stats = { 2340 .name = "vmxnet3-tx-stats", 2341 .version_id = 0, 2342 .fields = (VMStateField[]) { 2343 VMSTATE_UINT64(TSOPktsTxOK, struct UPT1_TxStats), 2344 VMSTATE_UINT64(TSOBytesTxOK, struct UPT1_TxStats), 2345 VMSTATE_UINT64(ucastPktsTxOK, struct UPT1_TxStats), 2346 VMSTATE_UINT64(ucastBytesTxOK, struct UPT1_TxStats), 2347 VMSTATE_UINT64(mcastPktsTxOK, struct UPT1_TxStats), 2348 VMSTATE_UINT64(mcastBytesTxOK, struct UPT1_TxStats), 2349 VMSTATE_UINT64(bcastPktsTxOK, struct UPT1_TxStats), 2350 VMSTATE_UINT64(bcastBytesTxOK, struct UPT1_TxStats), 2351 VMSTATE_UINT64(pktsTxError, struct UPT1_TxStats), 2352 VMSTATE_UINT64(pktsTxDiscard, struct UPT1_TxStats), 2353 VMSTATE_END_OF_LIST() 2354 } 2355 }; 2356 2357 static const VMStateDescription vmstate_vmxnet3_txq_descr = { 2358 .name = "vmxnet3-txq-descr", 2359 .version_id = 0, 2360 .fields = (VMStateField[]) { 2361 VMSTATE_STRUCT(tx_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring, 2362 Vmxnet3Ring), 2363 VMSTATE_STRUCT(comp_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring, 2364 Vmxnet3Ring), 2365 VMSTATE_UINT8(intr_idx, Vmxnet3TxqDescr), 2366 VMSTATE_UINT64(tx_stats_pa, Vmxnet3TxqDescr), 2367 VMSTATE_STRUCT(txq_stats, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_tx_stats, 2368 struct UPT1_TxStats), 2369 VMSTATE_END_OF_LIST() 2370 } 2371 }; 2372 2373 static const VMStateDescription vmstate_vmxnet3_rx_stats = { 2374 .name = "vmxnet3-rx-stats", 2375 .version_id = 0, 2376 .fields = (VMStateField[]) { 2377 VMSTATE_UINT64(LROPktsRxOK, struct UPT1_RxStats), 2378 VMSTATE_UINT64(LROBytesRxOK, struct UPT1_RxStats), 2379 VMSTATE_UINT64(ucastPktsRxOK, struct UPT1_RxStats), 2380 VMSTATE_UINT64(ucastBytesRxOK, struct UPT1_RxStats), 2381 VMSTATE_UINT64(mcastPktsRxOK, struct UPT1_RxStats), 2382 VMSTATE_UINT64(mcastBytesRxOK, struct UPT1_RxStats), 2383 VMSTATE_UINT64(bcastPktsRxOK, struct UPT1_RxStats), 2384 VMSTATE_UINT64(bcastBytesRxOK, struct UPT1_RxStats), 2385 VMSTATE_UINT64(pktsRxOutOfBuf, struct UPT1_RxStats), 2386 VMSTATE_UINT64(pktsRxError, struct UPT1_RxStats), 2387 VMSTATE_END_OF_LIST() 2388 } 2389 }; 2390 2391 static const VMStateDescription vmstate_vmxnet3_rxq_descr = { 2392 .name = "vmxnet3-rxq-descr", 2393 .version_id = 0, 2394 .fields = (VMStateField[]) { 2395 VMSTATE_STRUCT_ARRAY(rx_ring, Vmxnet3RxqDescr, 2396 VMXNET3_RX_RINGS_PER_QUEUE, 0, 2397 vmstate_vmxnet3_ring, Vmxnet3Ring), 2398 VMSTATE_STRUCT(comp_ring, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_ring, 2399 Vmxnet3Ring), 2400 VMSTATE_UINT8(intr_idx, Vmxnet3RxqDescr), 2401 VMSTATE_UINT64(rx_stats_pa, Vmxnet3RxqDescr), 2402 VMSTATE_STRUCT(rxq_stats, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_rx_stats, 2403 struct UPT1_RxStats), 2404 VMSTATE_END_OF_LIST() 2405 } 2406 }; 2407 2408 static int vmxnet3_post_load(void *opaque, int version_id) 2409 { 2410 VMXNET3State *s = opaque; 2411 PCIDevice *d = PCI_DEVICE(s); 2412 2413 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), 2414 s->max_tx_frags, s->peer_has_vhdr); 2415 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); 2416 2417 if (s->msix_used) { 2418 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) { 2419 VMW_WRPRN("Failed to re-use MSI-X vectors"); 2420 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2421 s->msix_used = false; 2422 return -1; 2423 } 2424 } 2425 2426 vmxnet3_validate_queues(s); 2427 vmxnet3_validate_interrupts(s); 2428 2429 return 0; 2430 } 2431 2432 static const VMStateDescription vmstate_vmxnet3_int_state = { 2433 .name = "vmxnet3-int-state", 2434 .version_id = 0, 2435 .fields = (VMStateField[]) { 2436 VMSTATE_BOOL(is_masked, Vmxnet3IntState), 2437 VMSTATE_BOOL(is_pending, Vmxnet3IntState), 2438 VMSTATE_BOOL(is_asserted, Vmxnet3IntState), 2439 VMSTATE_END_OF_LIST() 2440 } 2441 }; 2442 2443 static bool vmxnet3_vmstate_need_pcie_device(void *opaque) 2444 { 2445 VMXNET3State *s = VMXNET3(opaque); 2446 2447 return !(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE); 2448 } 2449 2450 static bool vmxnet3_vmstate_test_pci_device(void *opaque, int version_id) 2451 { 2452 return !vmxnet3_vmstate_need_pcie_device(opaque); 2453 } 2454 2455 static const VMStateDescription vmstate_vmxnet3_pcie_device = { 2456 .name = "vmxnet3/pcie", 2457 .version_id = 1, 2458 .minimum_version_id = 1, 2459 .needed = vmxnet3_vmstate_need_pcie_device, 2460 .fields = (VMStateField[]) { 2461 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State), 2462 VMSTATE_END_OF_LIST() 2463 } 2464 }; 2465 2466 static const VMStateDescription vmstate_vmxnet3 = { 2467 .name = "vmxnet3", 2468 .version_id = 1, 2469 .minimum_version_id = 1, 2470 .pre_save = vmxnet3_pre_save, 2471 .post_load = vmxnet3_post_load, 2472 .fields = (VMStateField[]) { 2473 VMSTATE_STRUCT_TEST(parent_obj, VMXNET3State, 2474 vmxnet3_vmstate_test_pci_device, 0, 2475 vmstate_pci_device, PCIDevice), 2476 VMSTATE_BOOL(rx_packets_compound, VMXNET3State), 2477 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State), 2478 VMSTATE_BOOL(lro_supported, VMXNET3State), 2479 VMSTATE_UINT32(rx_mode, VMXNET3State), 2480 VMSTATE_UINT32(mcast_list_len, VMXNET3State), 2481 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State), 2482 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE), 2483 VMSTATE_UINT32(mtu, VMXNET3State), 2484 VMSTATE_UINT16(max_rx_frags, VMXNET3State), 2485 VMSTATE_UINT32(max_tx_frags, VMXNET3State), 2486 VMSTATE_UINT8(event_int_idx, VMXNET3State), 2487 VMSTATE_BOOL(auto_int_masking, VMXNET3State), 2488 VMSTATE_UINT8(txq_num, VMXNET3State), 2489 VMSTATE_UINT8(rxq_num, VMXNET3State), 2490 VMSTATE_UINT32(device_active, VMXNET3State), 2491 VMSTATE_UINT32(last_command, VMXNET3State), 2492 VMSTATE_UINT32(link_status_and_speed, VMXNET3State), 2493 VMSTATE_UINT32(temp_mac, VMXNET3State), 2494 VMSTATE_UINT64(drv_shmem, VMXNET3State), 2495 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State), 2496 2497 VMSTATE_STRUCT_ARRAY(txq_descr, VMXNET3State, 2498 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, vmstate_vmxnet3_txq_descr, 2499 Vmxnet3TxqDescr), 2500 VMSTATE_STRUCT_ARRAY(rxq_descr, VMXNET3State, 2501 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, vmstate_vmxnet3_rxq_descr, 2502 Vmxnet3RxqDescr), 2503 VMSTATE_STRUCT_ARRAY(interrupt_states, VMXNET3State, 2504 VMXNET3_MAX_INTRS, 0, vmstate_vmxnet3_int_state, 2505 Vmxnet3IntState), 2506 2507 VMSTATE_END_OF_LIST() 2508 }, 2509 .subsections = (const VMStateDescription*[]) { 2510 &vmxstate_vmxnet3_mcast_list, 2511 &vmstate_vmxnet3_pcie_device, 2512 NULL 2513 } 2514 }; 2515 2516 static Property vmxnet3_properties[] = { 2517 DEFINE_NIC_PROPERTIES(VMXNET3State, conf), 2518 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags, 2519 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false), 2520 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags, 2521 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false), 2522 DEFINE_PROP_END_OF_LIST(), 2523 }; 2524 2525 static void vmxnet3_realize(DeviceState *qdev, Error **errp) 2526 { 2527 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev); 2528 PCIDevice *pci_dev = PCI_DEVICE(qdev); 2529 VMXNET3State *s = VMXNET3(qdev); 2530 2531 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) { 2532 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2533 } 2534 2535 vc->parent_dc_realize(qdev, errp); 2536 } 2537 2538 static void vmxnet3_class_init(ObjectClass *class, void *data) 2539 { 2540 DeviceClass *dc = DEVICE_CLASS(class); 2541 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 2542 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class); 2543 2544 c->realize = vmxnet3_pci_realize; 2545 c->exit = vmxnet3_pci_uninit; 2546 c->vendor_id = PCI_VENDOR_ID_VMWARE; 2547 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2548 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION; 2549 c->romfile = "efi-vmxnet3.rom"; 2550 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 2551 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 2552 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2553 device_class_set_parent_realize(dc, vmxnet3_realize, 2554 &vc->parent_dc_realize); 2555 dc->desc = "VMWare Paravirtualized Ethernet v3"; 2556 dc->reset = vmxnet3_qdev_reset; 2557 dc->vmsd = &vmstate_vmxnet3; 2558 dc->props = vmxnet3_properties; 2559 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 2560 } 2561 2562 static const TypeInfo vmxnet3_info = { 2563 .name = TYPE_VMXNET3, 2564 .parent = TYPE_PCI_DEVICE, 2565 .class_size = sizeof(VMXNET3Class), 2566 .instance_size = sizeof(VMXNET3State), 2567 .class_init = vmxnet3_class_init, 2568 .instance_init = vmxnet3_instance_init, 2569 .interfaces = (InterfaceInfo[]) { 2570 { INTERFACE_PCIE_DEVICE }, 2571 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2572 { } 2573 }, 2574 }; 2575 2576 static void vmxnet3_register_types(void) 2577 { 2578 VMW_CBPRN("vmxnet3_register_types called..."); 2579 type_register_static(&vmxnet3_info); 2580 } 2581 2582 type_init(vmxnet3_register_types) 2583