1 /* 2 * QEMU VMWARE VMXNET3 paravirtual NIC 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: 9 * Dmitry Fleytman <dmitry@daynix.com> 10 * Tamir Shomer <tamirs@daynix.com> 11 * Yan Vugenfirer <yan@daynix.com> 12 * 13 * This work is licensed under the terms of the GNU GPL, version 2. 14 * See the COPYING file in the top-level directory. 15 * 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/hw.h" 20 #include "hw/pci/pci.h" 21 #include "hw/qdev-properties.h" 22 #include "net/tap.h" 23 #include "net/checksum.h" 24 #include "sysemu/sysemu.h" 25 #include "qemu/bswap.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "hw/pci/msix.h" 29 #include "hw/pci/msi.h" 30 #include "migration/register.h" 31 #include "migration/vmstate.h" 32 33 #include "vmxnet3.h" 34 #include "vmxnet3_defs.h" 35 #include "vmxnet_debug.h" 36 #include "vmware_utils.h" 37 #include "net_tx_pkt.h" 38 #include "net_rx_pkt.h" 39 #include "qom/object.h" 40 41 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1 42 #define VMXNET3_MSIX_BAR_SIZE 0x2000 43 #define MIN_BUF_SIZE 60 44 45 /* Compatibility flags for migration */ 46 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0 47 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \ 48 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT) 49 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1 50 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \ 51 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT) 52 53 #define VMXNET3_EXP_EP_OFFSET (0x48) 54 #define VMXNET3_MSI_OFFSET(s) \ 55 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84) 56 #define VMXNET3_MSIX_OFFSET(s) \ 57 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c) 58 #define VMXNET3_DSN_OFFSET (0x100) 59 60 #define VMXNET3_BAR0_IDX (0) 61 #define VMXNET3_BAR1_IDX (1) 62 #define VMXNET3_MSIX_BAR_IDX (2) 63 64 #define VMXNET3_OFF_MSIX_TABLE (0x000) 65 #define VMXNET3_OFF_MSIX_PBA(s) \ 66 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000) 67 68 /* Link speed in Mbps should be shifted by 16 */ 69 #define VMXNET3_LINK_SPEED (1000 << 16) 70 71 /* Link status: 1 - up, 0 - down. */ 72 #define VMXNET3_LINK_STATUS_UP 0x1 73 74 /* Least significant bit should be set for revision and version */ 75 #define VMXNET3_UPT_REVISION 0x1 76 #define VMXNET3_DEVICE_REVISION 0x1 77 78 /* Number of interrupt vectors for non-MSIx modes */ 79 #define VMXNET3_MAX_NMSIX_INTRS (1) 80 81 /* Macros for rings descriptors access */ 82 #define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \ 83 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 84 85 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \ 86 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value))) 87 88 #define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \ 89 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 90 91 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \ 92 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 93 94 #define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \ 95 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 96 97 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \ 98 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 99 100 #define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \ 101 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 102 103 #define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \ 104 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 105 106 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \ 107 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 108 109 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \ 110 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 111 112 /* Macros for guest driver shared area access */ 113 #define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \ 114 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 115 116 #define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \ 117 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 118 119 #define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \ 120 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val)) 121 122 #define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \ 123 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 124 125 #define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \ 126 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 127 128 #define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \ 129 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l)) 130 131 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag)) 132 133 struct VMXNET3Class { 134 PCIDeviceClass parent_class; 135 DeviceRealize parent_dc_realize; 136 }; 137 typedef struct VMXNET3Class VMXNET3Class; 138 139 DECLARE_CLASS_CHECKERS(VMXNET3Class, VMXNET3_DEVICE, 140 TYPE_VMXNET3) 141 142 static inline void vmxnet3_ring_init(PCIDevice *d, 143 Vmxnet3Ring *ring, 144 hwaddr pa, 145 uint32_t size, 146 uint32_t cell_size, 147 bool zero_region) 148 { 149 ring->pa = pa; 150 ring->size = size; 151 ring->cell_size = cell_size; 152 ring->gen = VMXNET3_INIT_GEN; 153 ring->next = 0; 154 155 if (zero_region) { 156 vmw_shmem_set(d, pa, 0, size * cell_size); 157 } 158 } 159 160 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \ 161 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \ 162 (ring_name), (ridx), \ 163 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next) 164 165 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring) 166 { 167 if (++ring->next >= ring->size) { 168 ring->next = 0; 169 ring->gen ^= 1; 170 } 171 } 172 173 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring) 174 { 175 if (ring->next-- == 0) { 176 ring->next = ring->size - 1; 177 ring->gen ^= 1; 178 } 179 } 180 181 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring) 182 { 183 return ring->pa + ring->next * ring->cell_size; 184 } 185 186 static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring, 187 void *buff) 188 { 189 vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 190 } 191 192 static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring, 193 void *buff) 194 { 195 vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 196 } 197 198 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring) 199 { 200 return ring->next; 201 } 202 203 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring) 204 { 205 return ring->gen; 206 } 207 208 /* Debug trace-related functions */ 209 static inline void 210 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr) 211 { 212 VMW_PKPRN("TX DESCR: " 213 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 214 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, " 215 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d", 216 descr->addr, descr->len, descr->gen, descr->rsvd, 217 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om, 218 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci); 219 } 220 221 static inline void 222 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr) 223 { 224 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, " 225 "csum_start: %d, csum_offset: %d", 226 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size, 227 vhdr->csum_start, vhdr->csum_offset); 228 } 229 230 static inline void 231 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr) 232 { 233 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 234 "dtype: %d, ext1: %d, btype: %d", 235 descr->addr, descr->len, descr->gen, 236 descr->rsvd, descr->dtype, descr->ext1, descr->btype); 237 } 238 239 /* Interrupt management */ 240 241 /* 242 * This function returns sign whether interrupt line is in asserted state 243 * This depends on the type of interrupt used. For INTX interrupt line will 244 * be asserted until explicit deassertion, for MSI(X) interrupt line will 245 * be deasserted automatically due to notification semantics of the MSI(X) 246 * interrupts 247 */ 248 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx) 249 { 250 PCIDevice *d = PCI_DEVICE(s); 251 252 if (s->msix_used && msix_enabled(d)) { 253 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx); 254 msix_notify(d, int_idx); 255 return false; 256 } 257 if (msi_enabled(d)) { 258 VMW_IRPRN("Sending MSI notification for vector %u", int_idx); 259 msi_notify(d, int_idx); 260 return false; 261 } 262 263 VMW_IRPRN("Asserting line for interrupt %u", int_idx); 264 pci_irq_assert(d); 265 return true; 266 } 267 268 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx) 269 { 270 PCIDevice *d = PCI_DEVICE(s); 271 272 /* 273 * This function should never be called for MSI(X) interrupts 274 * because deassertion never required for message interrupts 275 */ 276 assert(!s->msix_used || !msix_enabled(d)); 277 /* 278 * This function should never be called for MSI(X) interrupts 279 * because deassertion never required for message interrupts 280 */ 281 assert(!msi_enabled(d)); 282 283 VMW_IRPRN("Deasserting line for interrupt %u", lidx); 284 pci_irq_deassert(d); 285 } 286 287 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx) 288 { 289 if (!s->interrupt_states[lidx].is_pending && 290 s->interrupt_states[lidx].is_asserted) { 291 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx); 292 _vmxnet3_deassert_interrupt_line(s, lidx); 293 s->interrupt_states[lidx].is_asserted = false; 294 return; 295 } 296 297 if (s->interrupt_states[lidx].is_pending && 298 !s->interrupt_states[lidx].is_masked && 299 !s->interrupt_states[lidx].is_asserted) { 300 VMW_IRPRN("New interrupt line state for index %d is UP", lidx); 301 s->interrupt_states[lidx].is_asserted = 302 _vmxnet3_assert_interrupt_line(s, lidx); 303 s->interrupt_states[lidx].is_pending = false; 304 return; 305 } 306 } 307 308 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx) 309 { 310 PCIDevice *d = PCI_DEVICE(s); 311 s->interrupt_states[lidx].is_pending = true; 312 vmxnet3_update_interrupt_line_state(s, lidx); 313 314 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) { 315 goto do_automask; 316 } 317 318 if (msi_enabled(d) && s->auto_int_masking) { 319 goto do_automask; 320 } 321 322 return; 323 324 do_automask: 325 s->interrupt_states[lidx].is_masked = true; 326 vmxnet3_update_interrupt_line_state(s, lidx); 327 } 328 329 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx) 330 { 331 return s->interrupt_states[lidx].is_asserted; 332 } 333 334 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx) 335 { 336 s->interrupt_states[int_idx].is_pending = false; 337 if (s->auto_int_masking) { 338 s->interrupt_states[int_idx].is_masked = true; 339 } 340 vmxnet3_update_interrupt_line_state(s, int_idx); 341 } 342 343 static void 344 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked) 345 { 346 s->interrupt_states[lidx].is_masked = is_masked; 347 vmxnet3_update_interrupt_line_state(s, lidx); 348 } 349 350 static bool vmxnet3_verify_driver_magic(PCIDevice *d, hwaddr dshmem) 351 { 352 return (VMXNET3_READ_DRV_SHARED32(d, dshmem, magic) == VMXNET3_REV1_MAGIC); 353 } 354 355 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF) 356 #define VMXNET3_MAKE_BYTE(byte_num, val) \ 357 (((uint32_t)((val) & 0xFF)) << (byte_num)*8) 358 359 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l) 360 { 361 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0); 362 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1); 363 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2); 364 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3); 365 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0); 366 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1); 367 368 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 369 370 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 371 } 372 373 static uint64_t vmxnet3_get_mac_low(MACAddr *addr) 374 { 375 return VMXNET3_MAKE_BYTE(0, addr->a[0]) | 376 VMXNET3_MAKE_BYTE(1, addr->a[1]) | 377 VMXNET3_MAKE_BYTE(2, addr->a[2]) | 378 VMXNET3_MAKE_BYTE(3, addr->a[3]); 379 } 380 381 static uint64_t vmxnet3_get_mac_high(MACAddr *addr) 382 { 383 return VMXNET3_MAKE_BYTE(0, addr->a[4]) | 384 VMXNET3_MAKE_BYTE(1, addr->a[5]); 385 } 386 387 static void 388 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx) 389 { 390 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring); 391 } 392 393 static inline void 394 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx) 395 { 396 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]); 397 } 398 399 static inline void 400 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx) 401 { 402 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring); 403 } 404 405 static void 406 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx) 407 { 408 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring); 409 } 410 411 static void 412 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx) 413 { 414 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring); 415 } 416 417 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx) 418 { 419 struct Vmxnet3_TxCompDesc txcq_descr; 420 PCIDevice *d = PCI_DEVICE(s); 421 422 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring); 423 424 memset(&txcq_descr, 0, sizeof(txcq_descr)); 425 txcq_descr.txdIdx = tx_ridx; 426 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring); 427 txcq_descr.val1 = cpu_to_le32(txcq_descr.val1); 428 txcq_descr.val2 = cpu_to_le32(txcq_descr.val2); 429 vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr); 430 431 /* Flush changes in TX descriptor before changing the counter value */ 432 smp_wmb(); 433 434 vmxnet3_inc_tx_completion_counter(s, qidx); 435 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx); 436 } 437 438 static bool 439 vmxnet3_setup_tx_offloads(VMXNET3State *s) 440 { 441 switch (s->offload_mode) { 442 case VMXNET3_OM_NONE: 443 return net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0); 444 445 case VMXNET3_OM_CSUM: 446 VMW_PKPRN("L4 CSO requested\n"); 447 return net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0); 448 449 case VMXNET3_OM_TSO: 450 VMW_PKPRN("GSO offload requested."); 451 if (!net_tx_pkt_build_vheader(s->tx_pkt, true, true, 452 s->cso_or_gso_size)) { 453 return false; 454 } 455 net_tx_pkt_update_ip_checksums(s->tx_pkt); 456 break; 457 458 default: 459 g_assert_not_reached(); 460 return false; 461 } 462 463 return true; 464 } 465 466 static void 467 vmxnet3_tx_retrieve_metadata(VMXNET3State *s, 468 const struct Vmxnet3_TxDesc *txd) 469 { 470 s->offload_mode = txd->om; 471 s->cso_or_gso_size = txd->msscof; 472 s->tci = txd->tci; 473 s->needs_vlan = txd->ti; 474 } 475 476 typedef enum { 477 VMXNET3_PKT_STATUS_OK, 478 VMXNET3_PKT_STATUS_ERROR, 479 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */ 480 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */ 481 } Vmxnet3PktStatus; 482 483 static void 484 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx, 485 Vmxnet3PktStatus status) 486 { 487 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt); 488 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats; 489 490 switch (status) { 491 case VMXNET3_PKT_STATUS_OK: 492 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) { 493 case ETH_PKT_BCAST: 494 stats->bcastPktsTxOK++; 495 stats->bcastBytesTxOK += tot_len; 496 break; 497 case ETH_PKT_MCAST: 498 stats->mcastPktsTxOK++; 499 stats->mcastBytesTxOK += tot_len; 500 break; 501 case ETH_PKT_UCAST: 502 stats->ucastPktsTxOK++; 503 stats->ucastBytesTxOK += tot_len; 504 break; 505 default: 506 g_assert_not_reached(); 507 } 508 509 if (s->offload_mode == VMXNET3_OM_TSO) { 510 /* 511 * According to VMWARE headers this statistic is a number 512 * of packets after segmentation but since we don't have 513 * this information in QEMU model, the best we can do is to 514 * provide number of non-segmented packets 515 */ 516 stats->TSOPktsTxOK++; 517 stats->TSOBytesTxOK += tot_len; 518 } 519 break; 520 521 case VMXNET3_PKT_STATUS_DISCARD: 522 stats->pktsTxDiscard++; 523 break; 524 525 case VMXNET3_PKT_STATUS_ERROR: 526 stats->pktsTxError++; 527 break; 528 529 default: 530 g_assert_not_reached(); 531 } 532 } 533 534 static void 535 vmxnet3_on_rx_done_update_stats(VMXNET3State *s, 536 int qidx, 537 Vmxnet3PktStatus status) 538 { 539 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats; 540 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt); 541 542 switch (status) { 543 case VMXNET3_PKT_STATUS_OUT_OF_BUF: 544 stats->pktsRxOutOfBuf++; 545 break; 546 547 case VMXNET3_PKT_STATUS_ERROR: 548 stats->pktsRxError++; 549 break; 550 case VMXNET3_PKT_STATUS_OK: 551 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 552 case ETH_PKT_BCAST: 553 stats->bcastPktsRxOK++; 554 stats->bcastBytesRxOK += tot_len; 555 break; 556 case ETH_PKT_MCAST: 557 stats->mcastPktsRxOK++; 558 stats->mcastBytesRxOK += tot_len; 559 break; 560 case ETH_PKT_UCAST: 561 stats->ucastPktsRxOK++; 562 stats->ucastBytesRxOK += tot_len; 563 break; 564 default: 565 g_assert_not_reached(); 566 } 567 568 if (tot_len > s->mtu) { 569 stats->LROPktsRxOK++; 570 stats->LROBytesRxOK += tot_len; 571 } 572 break; 573 default: 574 g_assert_not_reached(); 575 } 576 } 577 578 static inline void 579 vmxnet3_ring_read_curr_txdesc(PCIDevice *pcidev, Vmxnet3Ring *ring, 580 struct Vmxnet3_TxDesc *txd) 581 { 582 vmxnet3_ring_read_curr_cell(pcidev, ring, txd); 583 txd->addr = le64_to_cpu(txd->addr); 584 txd->val1 = le32_to_cpu(txd->val1); 585 txd->val2 = le32_to_cpu(txd->val2); 586 } 587 588 static inline bool 589 vmxnet3_pop_next_tx_descr(VMXNET3State *s, 590 int qidx, 591 struct Vmxnet3_TxDesc *txd, 592 uint32_t *descr_idx) 593 { 594 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring; 595 PCIDevice *d = PCI_DEVICE(s); 596 597 vmxnet3_ring_read_curr_txdesc(d, ring, txd); 598 if (txd->gen == vmxnet3_ring_curr_gen(ring)) { 599 /* Only read after generation field verification */ 600 smp_rmb(); 601 /* Re-read to be sure we got the latest version */ 602 vmxnet3_ring_read_curr_txdesc(d, ring, txd); 603 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring); 604 *descr_idx = vmxnet3_ring_curr_cell_idx(ring); 605 vmxnet3_inc_tx_consumption_counter(s, qidx); 606 return true; 607 } 608 609 return false; 610 } 611 612 static bool 613 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx) 614 { 615 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK; 616 617 if (!vmxnet3_setup_tx_offloads(s)) { 618 status = VMXNET3_PKT_STATUS_ERROR; 619 goto func_exit; 620 } 621 622 /* debug prints */ 623 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt)); 624 net_tx_pkt_dump(s->tx_pkt); 625 626 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) { 627 status = VMXNET3_PKT_STATUS_DISCARD; 628 goto func_exit; 629 } 630 631 func_exit: 632 vmxnet3_on_tx_done_update_stats(s, qidx, status); 633 return (status == VMXNET3_PKT_STATUS_OK); 634 } 635 636 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx) 637 { 638 struct Vmxnet3_TxDesc txd; 639 uint32_t txd_idx; 640 uint32_t data_len; 641 hwaddr data_pa; 642 643 for (;;) { 644 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) { 645 break; 646 } 647 648 vmxnet3_dump_tx_descr(&txd); 649 650 if (!s->skip_current_tx_pkt) { 651 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE; 652 data_pa = txd.addr; 653 654 if (!net_tx_pkt_add_raw_fragment(s->tx_pkt, 655 data_pa, 656 data_len)) { 657 s->skip_current_tx_pkt = true; 658 } 659 } 660 661 if (s->tx_sop) { 662 vmxnet3_tx_retrieve_metadata(s, &txd); 663 s->tx_sop = false; 664 } 665 666 if (txd.eop) { 667 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) { 668 if (s->needs_vlan) { 669 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci); 670 } 671 672 vmxnet3_send_packet(s, qidx); 673 } else { 674 vmxnet3_on_tx_done_update_stats(s, qidx, 675 VMXNET3_PKT_STATUS_ERROR); 676 } 677 678 vmxnet3_complete_packet(s, qidx, txd_idx); 679 s->tx_sop = true; 680 s->skip_current_tx_pkt = false; 681 net_tx_pkt_reset(s->tx_pkt, PCI_DEVICE(s)); 682 } 683 } 684 } 685 686 static inline void 687 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx, 688 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx) 689 { 690 PCIDevice *d = PCI_DEVICE(s); 691 692 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx]; 693 *didx = vmxnet3_ring_curr_cell_idx(ring); 694 vmxnet3_ring_read_curr_cell(d, ring, dbuf); 695 dbuf->addr = le64_to_cpu(dbuf->addr); 696 dbuf->val1 = le32_to_cpu(dbuf->val1); 697 dbuf->ext1 = le32_to_cpu(dbuf->ext1); 698 } 699 700 static inline uint8_t 701 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx) 702 { 703 return s->rxq_descr[qidx].rx_ring[ridx].gen; 704 } 705 706 static inline hwaddr 707 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen) 708 { 709 uint8_t ring_gen; 710 struct Vmxnet3_RxCompDesc rxcd; 711 712 hwaddr daddr = 713 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring); 714 715 pci_dma_read(PCI_DEVICE(s), 716 daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc)); 717 rxcd.val1 = le32_to_cpu(rxcd.val1); 718 rxcd.val2 = le32_to_cpu(rxcd.val2); 719 rxcd.val3 = le32_to_cpu(rxcd.val3); 720 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring); 721 722 if (rxcd.gen != ring_gen) { 723 *descr_gen = ring_gen; 724 vmxnet3_inc_rx_completion_counter(s, qidx); 725 return daddr; 726 } 727 728 return 0; 729 } 730 731 static inline void 732 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx) 733 { 734 vmxnet3_dec_rx_completion_counter(s, qidx); 735 } 736 737 #define RXQ_IDX (0) 738 #define RX_HEAD_BODY_RING (0) 739 #define RX_BODY_ONLY_RING (1) 740 741 static bool 742 vmxnet3_get_next_head_rx_descr(VMXNET3State *s, 743 struct Vmxnet3_RxDesc *descr_buf, 744 uint32_t *descr_idx, 745 uint32_t *ridx) 746 { 747 for (;;) { 748 uint32_t ring_gen; 749 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 750 descr_buf, descr_idx); 751 752 /* If no more free descriptors - return */ 753 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING); 754 if (descr_buf->gen != ring_gen) { 755 return false; 756 } 757 758 /* Only read after generation field verification */ 759 smp_rmb(); 760 /* Re-read to be sure we got the latest version */ 761 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 762 descr_buf, descr_idx); 763 764 /* Mark current descriptor as used/skipped */ 765 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 766 767 /* If this is what we are looking for - return */ 768 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) { 769 *ridx = RX_HEAD_BODY_RING; 770 return true; 771 } 772 } 773 } 774 775 static bool 776 vmxnet3_get_next_body_rx_descr(VMXNET3State *s, 777 struct Vmxnet3_RxDesc *d, 778 uint32_t *didx, 779 uint32_t *ridx) 780 { 781 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 782 783 /* Try to find corresponding descriptor in head/body ring */ 784 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) { 785 /* Only read after generation field verification */ 786 smp_rmb(); 787 /* Re-read to be sure we got the latest version */ 788 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 789 if (d->btype == VMXNET3_RXD_BTYPE_BODY) { 790 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 791 *ridx = RX_HEAD_BODY_RING; 792 return true; 793 } 794 } 795 796 /* 797 * If there is no free descriptors on head/body ring or next free 798 * descriptor is a head descriptor switch to body only ring 799 */ 800 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 801 802 /* If no more free descriptors - return */ 803 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) { 804 /* Only read after generation field verification */ 805 smp_rmb(); 806 /* Re-read to be sure we got the latest version */ 807 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 808 assert(d->btype == VMXNET3_RXD_BTYPE_BODY); 809 *ridx = RX_BODY_ONLY_RING; 810 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING); 811 return true; 812 } 813 814 return false; 815 } 816 817 static inline bool 818 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head, 819 struct Vmxnet3_RxDesc *descr_buf, 820 uint32_t *descr_idx, 821 uint32_t *ridx) 822 { 823 if (is_head || !s->rx_packets_compound) { 824 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx); 825 } else { 826 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx); 827 } 828 } 829 830 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID), 831 * the implementation always passes an RxCompDesc with a "Checksum 832 * calculated and found correct" to the OS (cnc=0 and tuc=1, see 833 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior. 834 * 835 * Therefore, if packet has the NEEDS_CSUM set, we must calculate 836 * and place a fully computed checksum into the tcp/udp header. 837 * Otherwise, the OS driver will receive a checksum-correct indication 838 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field 839 * having just the pseudo header csum value. 840 * 841 * While this is not a problem if packet is destined for local delivery, 842 * in the case the host OS performs forwarding, it will forward an 843 * incorrectly checksummed packet. 844 */ 845 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt, 846 const void *pkt_data, 847 size_t pkt_len) 848 { 849 struct virtio_net_hdr *vhdr; 850 bool hasip4, hasip6; 851 EthL4HdrProto l4hdr_proto; 852 uint8_t *data; 853 int len; 854 855 vhdr = net_rx_pkt_get_vhdr(pkt); 856 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 857 return; 858 } 859 860 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 861 if (!(hasip4 || hasip6) || 862 (l4hdr_proto != ETH_L4_HDR_PROTO_TCP && 863 l4hdr_proto != ETH_L4_HDR_PROTO_UDP)) { 864 return; 865 } 866 867 vmxnet3_dump_virt_hdr(vhdr); 868 869 /* Validate packet len: csum_start + scum_offset + length of csum field */ 870 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) { 871 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, " 872 "cannot calculate checksum", 873 pkt_len, vhdr->csum_start, vhdr->csum_offset); 874 return; 875 } 876 877 data = (uint8_t *)pkt_data + vhdr->csum_start; 878 len = pkt_len - vhdr->csum_start; 879 /* Put the checksum obtained into the packet */ 880 stw_be_p(data + vhdr->csum_offset, 881 net_checksum_finish_nozero(net_checksum_add(len, data))); 882 883 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM; 884 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID; 885 } 886 887 static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt, 888 struct Vmxnet3_RxCompDesc *rxcd) 889 { 890 int csum_ok, is_gso; 891 bool hasip4, hasip6; 892 EthL4HdrProto l4hdr_proto; 893 struct virtio_net_hdr *vhdr; 894 uint8_t offload_type; 895 896 if (net_rx_pkt_is_vlan_stripped(pkt)) { 897 rxcd->ts = 1; 898 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt); 899 } 900 901 vhdr = net_rx_pkt_get_vhdr(pkt); 902 /* 903 * Checksum is valid when lower level tell so or when lower level 904 * requires checksum offload telling that packet produced/bridged 905 * locally and did travel over network after last checksum calculation 906 * or production 907 */ 908 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) || 909 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM); 910 911 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN; 912 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0; 913 914 if (!csum_ok && !is_gso) { 915 goto nocsum; 916 } 917 918 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 919 if ((l4hdr_proto != ETH_L4_HDR_PROTO_TCP && 920 l4hdr_proto != ETH_L4_HDR_PROTO_UDP) || 921 (!hasip4 && !hasip6)) { 922 goto nocsum; 923 } 924 925 rxcd->cnc = 0; 926 rxcd->v4 = hasip4 ? 1 : 0; 927 rxcd->v6 = hasip6 ? 1 : 0; 928 rxcd->tcp = l4hdr_proto == ETH_L4_HDR_PROTO_TCP; 929 rxcd->udp = l4hdr_proto == ETH_L4_HDR_PROTO_UDP; 930 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1; 931 return; 932 933 nocsum: 934 rxcd->cnc = 1; 935 return; 936 } 937 938 static void 939 vmxnet3_pci_dma_writev(PCIDevice *pci_dev, 940 const struct iovec *iov, 941 size_t start_iov_off, 942 hwaddr target_addr, 943 size_t bytes_to_copy) 944 { 945 size_t curr_off = 0; 946 size_t copied = 0; 947 948 while (bytes_to_copy) { 949 if (start_iov_off < (curr_off + iov->iov_len)) { 950 size_t chunk_len = 951 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy); 952 953 pci_dma_write(pci_dev, target_addr + copied, 954 iov->iov_base + start_iov_off - curr_off, 955 chunk_len); 956 957 copied += chunk_len; 958 start_iov_off += chunk_len; 959 curr_off = start_iov_off; 960 bytes_to_copy -= chunk_len; 961 } else { 962 curr_off += iov->iov_len; 963 } 964 iov++; 965 } 966 } 967 968 static void 969 vmxnet3_pci_dma_write_rxcd(PCIDevice *pcidev, dma_addr_t pa, 970 struct Vmxnet3_RxCompDesc *rxcd) 971 { 972 rxcd->val1 = cpu_to_le32(rxcd->val1); 973 rxcd->val2 = cpu_to_le32(rxcd->val2); 974 rxcd->val3 = cpu_to_le32(rxcd->val3); 975 pci_dma_write(pcidev, pa, rxcd, sizeof(*rxcd)); 976 } 977 978 static bool 979 vmxnet3_indicate_packet(VMXNET3State *s) 980 { 981 struct Vmxnet3_RxDesc rxd; 982 PCIDevice *d = PCI_DEVICE(s); 983 bool is_head = true; 984 uint32_t rxd_idx; 985 uint32_t rx_ridx = 0; 986 987 struct Vmxnet3_RxCompDesc rxcd; 988 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN; 989 hwaddr new_rxcd_pa = 0; 990 hwaddr ready_rxcd_pa = 0; 991 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt); 992 size_t bytes_copied = 0; 993 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt); 994 uint16_t num_frags = 0; 995 size_t chunk_size; 996 997 net_rx_pkt_dump(s->rx_pkt); 998 999 while (bytes_left > 0) { 1000 1001 /* cannot add more frags to packet */ 1002 if (num_frags == s->max_rx_frags) { 1003 break; 1004 } 1005 1006 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen); 1007 if (!new_rxcd_pa) { 1008 break; 1009 } 1010 1011 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) { 1012 break; 1013 } 1014 1015 chunk_size = MIN(bytes_left, rxd.len); 1016 vmxnet3_pci_dma_writev(d, data, bytes_copied, rxd.addr, chunk_size); 1017 bytes_copied += chunk_size; 1018 bytes_left -= chunk_size; 1019 1020 vmxnet3_dump_rx_descr(&rxd); 1021 1022 if (ready_rxcd_pa != 0) { 1023 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd); 1024 } 1025 1026 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc)); 1027 rxcd.rxdIdx = rxd_idx; 1028 rxcd.len = chunk_size; 1029 rxcd.sop = is_head; 1030 rxcd.gen = new_rxcd_gen; 1031 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num; 1032 1033 if (bytes_left == 0) { 1034 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd); 1035 } 1036 1037 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu " 1038 "sop %d csum_correct %lu", 1039 (unsigned long) rx_ridx, 1040 (unsigned long) rxcd.rxdIdx, 1041 (unsigned long) rxcd.len, 1042 (int) rxcd.sop, 1043 (unsigned long) rxcd.tuc); 1044 1045 is_head = false; 1046 ready_rxcd_pa = new_rxcd_pa; 1047 new_rxcd_pa = 0; 1048 num_frags++; 1049 } 1050 1051 if (ready_rxcd_pa != 0) { 1052 rxcd.eop = 1; 1053 rxcd.err = (bytes_left != 0); 1054 1055 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd); 1056 1057 /* Flush RX descriptor changes */ 1058 smp_wmb(); 1059 } 1060 1061 if (new_rxcd_pa != 0) { 1062 vmxnet3_revert_rxc_descr(s, RXQ_IDX); 1063 } 1064 1065 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx); 1066 1067 if (bytes_left == 0) { 1068 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK); 1069 return true; 1070 } else if (num_frags == s->max_rx_frags) { 1071 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR); 1072 return false; 1073 } else { 1074 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, 1075 VMXNET3_PKT_STATUS_OUT_OF_BUF); 1076 return false; 1077 } 1078 } 1079 1080 static void 1081 vmxnet3_io_bar0_write(void *opaque, hwaddr addr, 1082 uint64_t val, unsigned size) 1083 { 1084 VMXNET3State *s = opaque; 1085 1086 if (!s->device_active) { 1087 return; 1088 } 1089 1090 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD, 1091 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) { 1092 int tx_queue_idx = 1093 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD, 1094 VMXNET3_REG_ALIGN); 1095 if (tx_queue_idx <= s->txq_num) { 1096 vmxnet3_process_tx_queue(s, tx_queue_idx); 1097 } else { 1098 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Illegal TX queue %d/%d\n", 1099 tx_queue_idx, s->txq_num); 1100 } 1101 return; 1102 } 1103 1104 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1105 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1106 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1107 VMXNET3_REG_ALIGN); 1108 1109 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val); 1110 1111 vmxnet3_on_interrupt_mask_changed(s, l, val); 1112 return; 1113 } 1114 1115 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD, 1116 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) || 1117 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2, 1118 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) { 1119 return; 1120 } 1121 1122 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d", 1123 (uint64_t) addr, val, size); 1124 } 1125 1126 static uint64_t 1127 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size) 1128 { 1129 VMXNET3State *s = opaque; 1130 1131 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1132 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1133 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1134 VMXNET3_REG_ALIGN); 1135 return s->interrupt_states[l].is_masked; 1136 } 1137 1138 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size); 1139 return 0; 1140 } 1141 1142 static void vmxnet3_reset_interrupt_states(VMXNET3State *s) 1143 { 1144 int i; 1145 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) { 1146 s->interrupt_states[i].is_asserted = false; 1147 s->interrupt_states[i].is_pending = false; 1148 s->interrupt_states[i].is_masked = true; 1149 } 1150 } 1151 1152 static void vmxnet3_reset_mac(VMXNET3State *s) 1153 { 1154 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a)); 1155 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 1156 } 1157 1158 static void vmxnet3_deactivate_device(VMXNET3State *s) 1159 { 1160 if (s->device_active) { 1161 VMW_CBPRN("Deactivating vmxnet3..."); 1162 net_tx_pkt_reset(s->tx_pkt, PCI_DEVICE(s)); 1163 net_tx_pkt_uninit(s->tx_pkt); 1164 net_rx_pkt_uninit(s->rx_pkt); 1165 s->device_active = false; 1166 } 1167 } 1168 1169 static void vmxnet3_reset(VMXNET3State *s) 1170 { 1171 VMW_CBPRN("Resetting vmxnet3..."); 1172 1173 vmxnet3_deactivate_device(s); 1174 vmxnet3_reset_interrupt_states(s); 1175 s->drv_shmem = 0; 1176 s->tx_sop = true; 1177 s->skip_current_tx_pkt = false; 1178 } 1179 1180 static void vmxnet3_update_rx_mode(VMXNET3State *s) 1181 { 1182 PCIDevice *d = PCI_DEVICE(s); 1183 1184 s->rx_mode = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, 1185 devRead.rxFilterConf.rxMode); 1186 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode); 1187 } 1188 1189 static void vmxnet3_update_vlan_filters(VMXNET3State *s) 1190 { 1191 int i; 1192 PCIDevice *d = PCI_DEVICE(s); 1193 1194 /* Copy configuration from shared memory */ 1195 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, 1196 devRead.rxFilterConf.vfTable, 1197 s->vlan_table, 1198 sizeof(s->vlan_table)); 1199 1200 /* Invert byte order when needed */ 1201 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) { 1202 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]); 1203 } 1204 1205 /* Dump configuration for debugging purposes */ 1206 VMW_CFPRN("Configured VLANs:"); 1207 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) { 1208 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) { 1209 VMW_CFPRN("\tVLAN %d is present", i); 1210 } 1211 } 1212 } 1213 1214 static void vmxnet3_update_mcast_filters(VMXNET3State *s) 1215 { 1216 PCIDevice *d = PCI_DEVICE(s); 1217 1218 uint16_t list_bytes = 1219 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, 1220 devRead.rxFilterConf.mfTableLen); 1221 1222 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]); 1223 1224 s->mcast_list = g_realloc(s->mcast_list, list_bytes); 1225 if (!s->mcast_list) { 1226 if (s->mcast_list_len == 0) { 1227 VMW_CFPRN("Current multicast list is empty"); 1228 } else { 1229 VMW_ERPRN("Failed to allocate multicast list of %d elements", 1230 s->mcast_list_len); 1231 } 1232 s->mcast_list_len = 0; 1233 } else { 1234 int i; 1235 hwaddr mcast_list_pa = 1236 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, 1237 devRead.rxFilterConf.mfTablePA); 1238 1239 pci_dma_read(d, mcast_list_pa, s->mcast_list, list_bytes); 1240 1241 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len); 1242 for (i = 0; i < s->mcast_list_len; i++) { 1243 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a)); 1244 } 1245 } 1246 } 1247 1248 static void vmxnet3_setup_rx_filtering(VMXNET3State *s) 1249 { 1250 vmxnet3_update_rx_mode(s); 1251 vmxnet3_update_vlan_filters(s); 1252 vmxnet3_update_mcast_filters(s); 1253 } 1254 1255 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s) 1256 { 1257 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2); 1258 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode); 1259 return interrupt_mode; 1260 } 1261 1262 static void vmxnet3_fill_stats(VMXNET3State *s) 1263 { 1264 int i; 1265 PCIDevice *d = PCI_DEVICE(s); 1266 1267 if (!s->device_active) 1268 return; 1269 1270 for (i = 0; i < s->txq_num; i++) { 1271 pci_dma_write(d, 1272 s->txq_descr[i].tx_stats_pa, 1273 &s->txq_descr[i].txq_stats, 1274 sizeof(s->txq_descr[i].txq_stats)); 1275 } 1276 1277 for (i = 0; i < s->rxq_num; i++) { 1278 pci_dma_write(d, 1279 s->rxq_descr[i].rx_stats_pa, 1280 &s->rxq_descr[i].rxq_stats, 1281 sizeof(s->rxq_descr[i].rxq_stats)); 1282 } 1283 } 1284 1285 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s) 1286 { 1287 struct Vmxnet3_GOSInfo gos; 1288 PCIDevice *d = PCI_DEVICE(s); 1289 1290 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, devRead.misc.driverInfo.gos, 1291 &gos, sizeof(gos)); 1292 s->rx_packets_compound = 1293 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true; 1294 1295 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound); 1296 } 1297 1298 static void 1299 vmxnet3_dump_conf_descr(const char *name, 1300 struct Vmxnet3_VariableLenConfDesc *pm_descr) 1301 { 1302 VMW_CFPRN("%s descriptor dump: Version %u, Length %u", 1303 name, pm_descr->confVer, pm_descr->confLen); 1304 1305 }; 1306 1307 static void vmxnet3_update_pm_state(VMXNET3State *s) 1308 { 1309 struct Vmxnet3_VariableLenConfDesc pm_descr; 1310 PCIDevice *d = PCI_DEVICE(s); 1311 1312 pm_descr.confLen = 1313 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confLen); 1314 pm_descr.confVer = 1315 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confVer); 1316 pm_descr.confPA = 1317 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.pmConfDesc.confPA); 1318 1319 vmxnet3_dump_conf_descr("PM State", &pm_descr); 1320 } 1321 1322 static void vmxnet3_update_features(VMXNET3State *s) 1323 { 1324 uint32_t guest_features; 1325 int rxcso_supported; 1326 PCIDevice *d = PCI_DEVICE(s); 1327 1328 guest_features = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, 1329 devRead.misc.uptFeatures); 1330 1331 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM); 1332 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN); 1333 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO); 1334 1335 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d", 1336 s->lro_supported, rxcso_supported, 1337 s->rx_vlan_stripping); 1338 if (s->peer_has_vhdr) { 1339 qemu_set_offload(qemu_get_queue(s->nic)->peer, 1340 rxcso_supported, 1341 s->lro_supported, 1342 s->lro_supported, 1343 0, 1344 0); 1345 } 1346 } 1347 1348 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx) 1349 { 1350 return s->msix_used || msi_enabled(PCI_DEVICE(s)) 1351 || intx == pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1; 1352 } 1353 1354 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx) 1355 { 1356 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS; 1357 if (idx >= max_ints) { 1358 hw_error("Bad interrupt index: %d\n", idx); 1359 } 1360 } 1361 1362 static void vmxnet3_validate_interrupts(VMXNET3State *s) 1363 { 1364 int i; 1365 1366 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx); 1367 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx); 1368 1369 for (i = 0; i < s->txq_num; i++) { 1370 int idx = s->txq_descr[i].intr_idx; 1371 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx); 1372 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1373 } 1374 1375 for (i = 0; i < s->rxq_num; i++) { 1376 int idx = s->rxq_descr[i].intr_idx; 1377 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx); 1378 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1379 } 1380 } 1381 1382 static bool vmxnet3_validate_queues(VMXNET3State *s) 1383 { 1384 /* 1385 * txq_num and rxq_num are total number of queues 1386 * configured by guest. These numbers must not 1387 * exceed corresponding maximal values. 1388 */ 1389 1390 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) { 1391 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad TX queues number: %d\n", 1392 s->txq_num); 1393 return false; 1394 } 1395 1396 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) { 1397 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad RX queues number: %d\n", 1398 s->rxq_num); 1399 return false; 1400 } 1401 1402 return true; 1403 } 1404 1405 static void vmxnet3_activate_device(VMXNET3State *s) 1406 { 1407 int i; 1408 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1; 1409 PCIDevice *d = PCI_DEVICE(s); 1410 hwaddr qdescr_table_pa; 1411 uint64_t pa; 1412 uint32_t size; 1413 1414 /* Verify configuration consistency */ 1415 if (!vmxnet3_verify_driver_magic(d, s->drv_shmem)) { 1416 VMW_ERPRN("Device configuration received from driver is invalid"); 1417 return; 1418 } 1419 1420 /* Verify if device is active */ 1421 if (s->device_active) { 1422 VMW_CFPRN("Vmxnet3 device is active"); 1423 return; 1424 } 1425 1426 s->txq_num = 1427 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numTxQueues); 1428 s->rxq_num = 1429 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numRxQueues); 1430 1431 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num); 1432 if (!vmxnet3_validate_queues(s)) { 1433 return; 1434 } 1435 1436 vmxnet3_adjust_by_guest_type(s); 1437 vmxnet3_update_features(s); 1438 vmxnet3_update_pm_state(s); 1439 vmxnet3_setup_rx_filtering(s); 1440 /* Cache fields from shared memory */ 1441 s->mtu = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.misc.mtu); 1442 assert(VMXNET3_MIN_MTU <= s->mtu && s->mtu <= VMXNET3_MAX_MTU); 1443 VMW_CFPRN("MTU is %u", s->mtu); 1444 1445 s->max_rx_frags = 1446 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, devRead.misc.maxNumRxSG); 1447 1448 if (s->max_rx_frags == 0) { 1449 s->max_rx_frags = 1; 1450 } 1451 1452 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags); 1453 1454 s->event_int_idx = 1455 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.eventIntrIdx); 1456 assert(vmxnet3_verify_intx(s, s->event_int_idx)); 1457 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx); 1458 1459 s->auto_int_masking = 1460 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.autoMask); 1461 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking); 1462 1463 qdescr_table_pa = 1464 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.misc.queueDescPA); 1465 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa); 1466 1467 /* 1468 * Worst-case scenario is a packet that holds all TX rings space so 1469 * we calculate total size of all TX rings for max TX fragments number 1470 */ 1471 s->max_tx_frags = 0; 1472 1473 /* TX queues */ 1474 for (i = 0; i < s->txq_num; i++) { 1475 hwaddr qdescr_pa = 1476 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc); 1477 1478 /* Read interrupt number for this TX queue */ 1479 s->txq_descr[i].intr_idx = 1480 VMXNET3_READ_TX_QUEUE_DESCR8(d, qdescr_pa, conf.intrIdx); 1481 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx)); 1482 1483 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx); 1484 1485 /* Read rings memory locations for TX queues */ 1486 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA); 1487 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.txRingSize); 1488 if (size > VMXNET3_TX_RING_MAX_SIZE) { 1489 size = VMXNET3_TX_RING_MAX_SIZE; 1490 } 1491 1492 vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size, 1493 sizeof(struct Vmxnet3_TxDesc), false); 1494 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring); 1495 1496 s->max_tx_frags += size; 1497 1498 /* TXC ring */ 1499 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA); 1500 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.compRingSize); 1501 if (size > VMXNET3_TC_RING_MAX_SIZE) { 1502 size = VMXNET3_TC_RING_MAX_SIZE; 1503 } 1504 vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size, 1505 sizeof(struct Vmxnet3_TxCompDesc), true); 1506 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring); 1507 1508 s->txq_descr[i].tx_stats_pa = 1509 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats); 1510 1511 memset(&s->txq_descr[i].txq_stats, 0, 1512 sizeof(s->txq_descr[i].txq_stats)); 1513 1514 /* Fill device-managed parameters for queues */ 1515 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa, 1516 ctrl.txThreshold, 1517 VMXNET3_DEF_TX_THRESHOLD); 1518 } 1519 1520 /* Preallocate TX packet wrapper */ 1521 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags); 1522 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags); 1523 net_rx_pkt_init(&s->rx_pkt); 1524 1525 /* Read rings memory locations for RX queues */ 1526 for (i = 0; i < s->rxq_num; i++) { 1527 int j; 1528 hwaddr qd_pa = 1529 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) + 1530 i * sizeof(struct Vmxnet3_RxQueueDesc); 1531 1532 /* Read interrupt number for this RX queue */ 1533 s->rxq_descr[i].intr_idx = 1534 VMXNET3_READ_TX_QUEUE_DESCR8(d, qd_pa, conf.intrIdx); 1535 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx)); 1536 1537 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx); 1538 1539 /* Read rings memory locations */ 1540 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) { 1541 /* RX rings */ 1542 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]); 1543 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.rxRingSize[j]); 1544 if (size > VMXNET3_RX_RING_MAX_SIZE) { 1545 size = VMXNET3_RX_RING_MAX_SIZE; 1546 } 1547 vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size, 1548 sizeof(struct Vmxnet3_RxDesc), false); 1549 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d", 1550 i, j, pa, size); 1551 } 1552 1553 /* RXC ring */ 1554 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA); 1555 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.compRingSize); 1556 if (size > VMXNET3_RC_RING_MAX_SIZE) { 1557 size = VMXNET3_RC_RING_MAX_SIZE; 1558 } 1559 vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size, 1560 sizeof(struct Vmxnet3_RxCompDesc), true); 1561 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size); 1562 1563 s->rxq_descr[i].rx_stats_pa = 1564 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats); 1565 memset(&s->rxq_descr[i].rxq_stats, 0, 1566 sizeof(s->rxq_descr[i].rxq_stats)); 1567 } 1568 1569 vmxnet3_validate_interrupts(s); 1570 1571 /* Make sure everything is in place before device activation */ 1572 smp_wmb(); 1573 1574 vmxnet3_reset_mac(s); 1575 1576 s->device_active = true; 1577 } 1578 1579 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd) 1580 { 1581 s->last_command = cmd; 1582 1583 switch (cmd) { 1584 case VMXNET3_CMD_GET_PERM_MAC_HI: 1585 VMW_CBPRN("Set: Get upper part of permanent MAC"); 1586 break; 1587 1588 case VMXNET3_CMD_GET_PERM_MAC_LO: 1589 VMW_CBPRN("Set: Get lower part of permanent MAC"); 1590 break; 1591 1592 case VMXNET3_CMD_GET_STATS: 1593 VMW_CBPRN("Set: Get device statistics"); 1594 vmxnet3_fill_stats(s); 1595 break; 1596 1597 case VMXNET3_CMD_ACTIVATE_DEV: 1598 VMW_CBPRN("Set: Activating vmxnet3 device"); 1599 vmxnet3_activate_device(s); 1600 break; 1601 1602 case VMXNET3_CMD_UPDATE_RX_MODE: 1603 VMW_CBPRN("Set: Update rx mode"); 1604 vmxnet3_update_rx_mode(s); 1605 break; 1606 1607 case VMXNET3_CMD_UPDATE_VLAN_FILTERS: 1608 VMW_CBPRN("Set: Update VLAN filters"); 1609 vmxnet3_update_vlan_filters(s); 1610 break; 1611 1612 case VMXNET3_CMD_UPDATE_MAC_FILTERS: 1613 VMW_CBPRN("Set: Update MAC filters"); 1614 vmxnet3_update_mcast_filters(s); 1615 break; 1616 1617 case VMXNET3_CMD_UPDATE_FEATURE: 1618 VMW_CBPRN("Set: Update features"); 1619 vmxnet3_update_features(s); 1620 break; 1621 1622 case VMXNET3_CMD_UPDATE_PMCFG: 1623 VMW_CBPRN("Set: Update power management config"); 1624 vmxnet3_update_pm_state(s); 1625 break; 1626 1627 case VMXNET3_CMD_GET_LINK: 1628 VMW_CBPRN("Set: Get link"); 1629 break; 1630 1631 case VMXNET3_CMD_RESET_DEV: 1632 VMW_CBPRN("Set: Reset device"); 1633 vmxnet3_reset(s); 1634 break; 1635 1636 case VMXNET3_CMD_QUIESCE_DEV: 1637 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device"); 1638 vmxnet3_deactivate_device(s); 1639 break; 1640 1641 case VMXNET3_CMD_GET_CONF_INTR: 1642 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration"); 1643 break; 1644 1645 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1646 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - " 1647 "adaptive ring info flags"); 1648 break; 1649 1650 case VMXNET3_CMD_GET_DID_LO: 1651 VMW_CBPRN("Set: Get lower part of device ID"); 1652 break; 1653 1654 case VMXNET3_CMD_GET_DID_HI: 1655 VMW_CBPRN("Set: Get upper part of device ID"); 1656 break; 1657 1658 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1659 VMW_CBPRN("Set: Get device extra info"); 1660 break; 1661 1662 default: 1663 VMW_CBPRN("Received unknown command: %" PRIx64, cmd); 1664 break; 1665 } 1666 } 1667 1668 static uint64_t vmxnet3_get_command_status(VMXNET3State *s) 1669 { 1670 uint64_t ret; 1671 1672 switch (s->last_command) { 1673 case VMXNET3_CMD_ACTIVATE_DEV: 1674 ret = (s->device_active) ? 0 : 1; 1675 VMW_CFPRN("Device active: %" PRIx64, ret); 1676 break; 1677 1678 case VMXNET3_CMD_RESET_DEV: 1679 case VMXNET3_CMD_QUIESCE_DEV: 1680 case VMXNET3_CMD_GET_QUEUE_STATUS: 1681 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1682 ret = 0; 1683 break; 1684 1685 case VMXNET3_CMD_GET_LINK: 1686 ret = s->link_status_and_speed; 1687 VMW_CFPRN("Link and speed: %" PRIx64, ret); 1688 break; 1689 1690 case VMXNET3_CMD_GET_PERM_MAC_LO: 1691 ret = vmxnet3_get_mac_low(&s->perm_mac); 1692 break; 1693 1694 case VMXNET3_CMD_GET_PERM_MAC_HI: 1695 ret = vmxnet3_get_mac_high(&s->perm_mac); 1696 break; 1697 1698 case VMXNET3_CMD_GET_CONF_INTR: 1699 ret = vmxnet3_get_interrupt_config(s); 1700 break; 1701 1702 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1703 ret = VMXNET3_DISABLE_ADAPTIVE_RING; 1704 break; 1705 1706 case VMXNET3_CMD_GET_DID_LO: 1707 ret = PCI_DEVICE_ID_VMWARE_VMXNET3; 1708 break; 1709 1710 case VMXNET3_CMD_GET_DID_HI: 1711 ret = VMXNET3_DEVICE_REVISION; 1712 break; 1713 1714 default: 1715 VMW_WRPRN("Received request for unknown command: %x", s->last_command); 1716 ret = 0; 1717 break; 1718 } 1719 1720 return ret; 1721 } 1722 1723 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val) 1724 { 1725 uint32_t events; 1726 PCIDevice *d = PCI_DEVICE(s); 1727 1728 VMW_CBPRN("Setting events: 0x%x", val); 1729 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) | val; 1730 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events); 1731 } 1732 1733 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val) 1734 { 1735 PCIDevice *d = PCI_DEVICE(s); 1736 uint32_t events; 1737 1738 VMW_CBPRN("Clearing events: 0x%x", val); 1739 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) & ~val; 1740 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events); 1741 } 1742 1743 static void 1744 vmxnet3_io_bar1_write(void *opaque, 1745 hwaddr addr, 1746 uint64_t val, 1747 unsigned size) 1748 { 1749 VMXNET3State *s = opaque; 1750 1751 switch (addr) { 1752 /* Vmxnet3 Revision Report Selection */ 1753 case VMXNET3_REG_VRRS: 1754 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d", 1755 val, size); 1756 break; 1757 1758 /* UPT Version Report Selection */ 1759 case VMXNET3_REG_UVRS: 1760 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d", 1761 val, size); 1762 break; 1763 1764 /* Driver Shared Address Low */ 1765 case VMXNET3_REG_DSAL: 1766 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d", 1767 val, size); 1768 /* 1769 * Guest driver will first write the low part of the shared 1770 * memory address. We save it to temp variable and set the 1771 * shared address only after we get the high part 1772 */ 1773 if (val == 0) { 1774 vmxnet3_deactivate_device(s); 1775 } 1776 s->temp_shared_guest_driver_memory = val; 1777 s->drv_shmem = 0; 1778 break; 1779 1780 /* Driver Shared Address High */ 1781 case VMXNET3_REG_DSAH: 1782 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d", 1783 val, size); 1784 /* 1785 * Set the shared memory between guest driver and device. 1786 * We already should have low address part. 1787 */ 1788 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32); 1789 break; 1790 1791 /* Command */ 1792 case VMXNET3_REG_CMD: 1793 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d", 1794 val, size); 1795 vmxnet3_handle_command(s, val); 1796 break; 1797 1798 /* MAC Address Low */ 1799 case VMXNET3_REG_MACL: 1800 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d", 1801 val, size); 1802 s->temp_mac = val; 1803 break; 1804 1805 /* MAC Address High */ 1806 case VMXNET3_REG_MACH: 1807 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d", 1808 val, size); 1809 vmxnet3_set_variable_mac(s, val, s->temp_mac); 1810 break; 1811 1812 /* Interrupt Cause Register */ 1813 case VMXNET3_REG_ICR: 1814 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d", 1815 val, size); 1816 qemu_log_mask(LOG_GUEST_ERROR, 1817 "%s: write to read-only register VMXNET3_REG_ICR\n", 1818 TYPE_VMXNET3); 1819 break; 1820 1821 /* Event Cause Register */ 1822 case VMXNET3_REG_ECR: 1823 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d", 1824 val, size); 1825 vmxnet3_ack_events(s, val); 1826 break; 1827 1828 default: 1829 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d", 1830 addr, val, size); 1831 break; 1832 } 1833 } 1834 1835 static uint64_t 1836 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size) 1837 { 1838 VMXNET3State *s = opaque; 1839 uint64_t ret = 0; 1840 1841 switch (addr) { 1842 /* Vmxnet3 Revision Report Selection */ 1843 case VMXNET3_REG_VRRS: 1844 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size); 1845 ret = VMXNET3_DEVICE_REVISION; 1846 break; 1847 1848 /* UPT Version Report Selection */ 1849 case VMXNET3_REG_UVRS: 1850 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size); 1851 ret = VMXNET3_UPT_REVISION; 1852 break; 1853 1854 /* Command */ 1855 case VMXNET3_REG_CMD: 1856 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size); 1857 ret = vmxnet3_get_command_status(s); 1858 break; 1859 1860 /* MAC Address Low */ 1861 case VMXNET3_REG_MACL: 1862 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size); 1863 ret = vmxnet3_get_mac_low(&s->conf.macaddr); 1864 break; 1865 1866 /* MAC Address High */ 1867 case VMXNET3_REG_MACH: 1868 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size); 1869 ret = vmxnet3_get_mac_high(&s->conf.macaddr); 1870 break; 1871 1872 /* 1873 * Interrupt Cause Register 1874 * Used for legacy interrupts only so interrupt index always 0 1875 */ 1876 case VMXNET3_REG_ICR: 1877 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size); 1878 if (vmxnet3_interrupt_asserted(s, 0)) { 1879 vmxnet3_clear_interrupt(s, 0); 1880 ret = true; 1881 } else { 1882 ret = false; 1883 } 1884 break; 1885 1886 default: 1887 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size); 1888 break; 1889 } 1890 1891 return ret; 1892 } 1893 1894 static int 1895 vmxnet3_can_receive(NetClientState *nc) 1896 { 1897 VMXNET3State *s = qemu_get_nic_opaque(nc); 1898 return s->device_active && 1899 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP); 1900 } 1901 1902 static inline bool 1903 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data) 1904 { 1905 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK; 1906 if (IS_SPECIAL_VLAN_ID(vlan_tag)) { 1907 return true; 1908 } 1909 1910 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag); 1911 } 1912 1913 static bool 1914 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac) 1915 { 1916 int i; 1917 for (i = 0; i < s->mcast_list_len; i++) { 1918 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) { 1919 return true; 1920 } 1921 } 1922 return false; 1923 } 1924 1925 static bool 1926 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data, 1927 size_t size) 1928 { 1929 struct eth_header *ehdr = PKT_GET_ETH_HDR(data); 1930 1931 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) { 1932 return true; 1933 } 1934 1935 if (!vmxnet3_is_registered_vlan(s, data)) { 1936 return false; 1937 } 1938 1939 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 1940 case ETH_PKT_UCAST: 1941 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) { 1942 return false; 1943 } 1944 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) { 1945 return false; 1946 } 1947 break; 1948 1949 case ETH_PKT_BCAST: 1950 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) { 1951 return false; 1952 } 1953 break; 1954 1955 case ETH_PKT_MCAST: 1956 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) { 1957 return true; 1958 } 1959 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) { 1960 return false; 1961 } 1962 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) { 1963 return false; 1964 } 1965 break; 1966 1967 default: 1968 g_assert_not_reached(); 1969 } 1970 1971 return true; 1972 } 1973 1974 static ssize_t 1975 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1976 { 1977 VMXNET3State *s = qemu_get_nic_opaque(nc); 1978 size_t bytes_indicated; 1979 uint8_t min_buf[MIN_BUF_SIZE]; 1980 1981 if (!vmxnet3_can_receive(nc)) { 1982 VMW_PKPRN("Cannot receive now"); 1983 return -1; 1984 } 1985 1986 if (s->peer_has_vhdr) { 1987 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf); 1988 buf += sizeof(struct virtio_net_hdr); 1989 size -= sizeof(struct virtio_net_hdr); 1990 } 1991 1992 /* Pad to minimum Ethernet frame length */ 1993 if (size < sizeof(min_buf)) { 1994 memcpy(min_buf, buf, size); 1995 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1996 buf = min_buf; 1997 size = sizeof(min_buf); 1998 } 1999 2000 net_rx_pkt_set_packet_type(s->rx_pkt, 2001 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 2002 2003 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) { 2004 net_rx_pkt_set_protocols(s->rx_pkt, buf, size); 2005 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size); 2006 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping); 2007 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1; 2008 if (bytes_indicated < size) { 2009 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size); 2010 } 2011 } else { 2012 VMW_PKPRN("Packet dropped by RX filter"); 2013 bytes_indicated = size; 2014 } 2015 2016 assert(size > 0); 2017 assert(bytes_indicated != 0); 2018 return bytes_indicated; 2019 } 2020 2021 static void vmxnet3_set_link_status(NetClientState *nc) 2022 { 2023 VMXNET3State *s = qemu_get_nic_opaque(nc); 2024 2025 if (nc->link_down) { 2026 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP; 2027 } else { 2028 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP; 2029 } 2030 2031 vmxnet3_set_events(s, VMXNET3_ECR_LINK); 2032 vmxnet3_trigger_interrupt(s, s->event_int_idx); 2033 } 2034 2035 static NetClientInfo net_vmxnet3_info = { 2036 .type = NET_CLIENT_DRIVER_NIC, 2037 .size = sizeof(NICState), 2038 .receive = vmxnet3_receive, 2039 .link_status_changed = vmxnet3_set_link_status, 2040 }; 2041 2042 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s) 2043 { 2044 NetClientState *nc = qemu_get_queue(s->nic); 2045 2046 if (qemu_has_vnet_hdr(nc->peer)) { 2047 return true; 2048 } 2049 2050 return false; 2051 } 2052 2053 static void vmxnet3_net_uninit(VMXNET3State *s) 2054 { 2055 g_free(s->mcast_list); 2056 vmxnet3_deactivate_device(s); 2057 qemu_del_nic(s->nic); 2058 } 2059 2060 static void vmxnet3_net_init(VMXNET3State *s) 2061 { 2062 DeviceState *d = DEVICE(s); 2063 2064 VMW_CBPRN("vmxnet3_net_init called..."); 2065 2066 qemu_macaddr_default_if_unset(&s->conf.macaddr); 2067 2068 /* Windows guest will query the address that was set on init */ 2069 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a)); 2070 2071 s->mcast_list = NULL; 2072 s->mcast_list_len = 0; 2073 2074 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP; 2075 2076 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a)); 2077 2078 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf, 2079 object_get_typename(OBJECT(s)), 2080 d->id, s); 2081 2082 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s); 2083 s->tx_sop = true; 2084 s->skip_current_tx_pkt = false; 2085 s->tx_pkt = NULL; 2086 s->rx_pkt = NULL; 2087 s->rx_vlan_stripping = false; 2088 s->lro_supported = false; 2089 2090 if (s->peer_has_vhdr) { 2091 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer, 2092 sizeof(struct virtio_net_hdr)); 2093 2094 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1); 2095 } 2096 2097 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 2098 } 2099 2100 static void 2101 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors) 2102 { 2103 PCIDevice *d = PCI_DEVICE(s); 2104 int i; 2105 for (i = 0; i < num_vectors; i++) { 2106 msix_vector_unuse(d, i); 2107 } 2108 } 2109 2110 static void 2111 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors) 2112 { 2113 PCIDevice *d = PCI_DEVICE(s); 2114 int i; 2115 for (i = 0; i < num_vectors; i++) { 2116 msix_vector_use(d, i); 2117 } 2118 } 2119 2120 static bool 2121 vmxnet3_init_msix(VMXNET3State *s) 2122 { 2123 PCIDevice *d = PCI_DEVICE(s); 2124 int res = msix_init(d, VMXNET3_MAX_INTRS, 2125 &s->msix_bar, 2126 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE, 2127 &s->msix_bar, 2128 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s), 2129 VMXNET3_MSIX_OFFSET(s), NULL); 2130 2131 if (0 > res) { 2132 VMW_WRPRN("Failed to initialize MSI-X, error %d", res); 2133 s->msix_used = false; 2134 } else { 2135 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS); 2136 s->msix_used = true; 2137 } 2138 return s->msix_used; 2139 } 2140 2141 static void 2142 vmxnet3_cleanup_msix(VMXNET3State *s) 2143 { 2144 PCIDevice *d = PCI_DEVICE(s); 2145 2146 if (s->msix_used) { 2147 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS); 2148 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2149 } 2150 } 2151 2152 static void 2153 vmxnet3_cleanup_msi(VMXNET3State *s) 2154 { 2155 PCIDevice *d = PCI_DEVICE(s); 2156 2157 msi_uninit(d); 2158 } 2159 2160 static const MemoryRegionOps b0_ops = { 2161 .read = vmxnet3_io_bar0_read, 2162 .write = vmxnet3_io_bar0_write, 2163 .endianness = DEVICE_LITTLE_ENDIAN, 2164 .impl = { 2165 .min_access_size = 4, 2166 .max_access_size = 4, 2167 }, 2168 }; 2169 2170 static const MemoryRegionOps b1_ops = { 2171 .read = vmxnet3_io_bar1_read, 2172 .write = vmxnet3_io_bar1_write, 2173 .endianness = DEVICE_LITTLE_ENDIAN, 2174 .impl = { 2175 .min_access_size = 4, 2176 .max_access_size = 4, 2177 }, 2178 }; 2179 2180 static uint64_t vmxnet3_device_serial_num(VMXNET3State *s) 2181 { 2182 uint64_t dsn_payload; 2183 uint8_t *dsnp = (uint8_t *)&dsn_payload; 2184 2185 dsnp[0] = 0xfe; 2186 dsnp[1] = s->conf.macaddr.a[3]; 2187 dsnp[2] = s->conf.macaddr.a[4]; 2188 dsnp[3] = s->conf.macaddr.a[5]; 2189 dsnp[4] = s->conf.macaddr.a[0]; 2190 dsnp[5] = s->conf.macaddr.a[1]; 2191 dsnp[6] = s->conf.macaddr.a[2]; 2192 dsnp[7] = 0xff; 2193 return dsn_payload; 2194 } 2195 2196 2197 #define VMXNET3_USE_64BIT (true) 2198 #define VMXNET3_PER_VECTOR_MASK (false) 2199 2200 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp) 2201 { 2202 VMXNET3State *s = VMXNET3(pci_dev); 2203 int ret; 2204 2205 VMW_CBPRN("Starting init..."); 2206 2207 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s, 2208 "vmxnet3-b0", VMXNET3_PT_REG_SIZE); 2209 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX, 2210 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 2211 2212 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s, 2213 "vmxnet3-b1", VMXNET3_VD_REG_SIZE); 2214 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX, 2215 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1); 2216 2217 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar", 2218 VMXNET3_MSIX_BAR_SIZE); 2219 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX, 2220 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar); 2221 2222 vmxnet3_reset_interrupt_states(s); 2223 2224 /* Interrupt pin A */ 2225 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01; 2226 2227 ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS, 2228 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL); 2229 /* Any error other than -ENOTSUP(board's MSI support is broken) 2230 * is a programming error. Fall back to INTx silently on -ENOTSUP */ 2231 assert(!ret || ret == -ENOTSUP); 2232 2233 if (!vmxnet3_init_msix(s)) { 2234 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent."); 2235 } 2236 2237 vmxnet3_net_init(s); 2238 2239 if (pci_is_express(pci_dev)) { 2240 if (pci_bus_is_express(pci_get_bus(pci_dev))) { 2241 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET); 2242 } 2243 2244 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET, 2245 vmxnet3_device_serial_num(s)); 2246 } 2247 } 2248 2249 static void vmxnet3_instance_init(Object *obj) 2250 { 2251 VMXNET3State *s = VMXNET3(obj); 2252 device_add_bootindex_property(obj, &s->conf.bootindex, 2253 "bootindex", "/ethernet-phy@0", 2254 DEVICE(obj)); 2255 } 2256 2257 static void vmxnet3_pci_uninit(PCIDevice *pci_dev) 2258 { 2259 VMXNET3State *s = VMXNET3(pci_dev); 2260 2261 VMW_CBPRN("Starting uninit..."); 2262 2263 vmxnet3_net_uninit(s); 2264 2265 vmxnet3_cleanup_msix(s); 2266 2267 vmxnet3_cleanup_msi(s); 2268 } 2269 2270 static void vmxnet3_qdev_reset(DeviceState *dev) 2271 { 2272 PCIDevice *d = PCI_DEVICE(dev); 2273 VMXNET3State *s = VMXNET3(d); 2274 2275 VMW_CBPRN("Starting QDEV reset..."); 2276 vmxnet3_reset(s); 2277 } 2278 2279 static bool vmxnet3_mc_list_needed(void *opaque) 2280 { 2281 return true; 2282 } 2283 2284 static int vmxnet3_mcast_list_pre_load(void *opaque) 2285 { 2286 VMXNET3State *s = opaque; 2287 2288 s->mcast_list = g_malloc(s->mcast_list_buff_size); 2289 2290 return 0; 2291 } 2292 2293 2294 static int vmxnet3_pre_save(void *opaque) 2295 { 2296 VMXNET3State *s = opaque; 2297 2298 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr); 2299 2300 return 0; 2301 } 2302 2303 static const VMStateDescription vmxstate_vmxnet3_mcast_list = { 2304 .name = "vmxnet3/mcast_list", 2305 .version_id = 1, 2306 .minimum_version_id = 1, 2307 .pre_load = vmxnet3_mcast_list_pre_load, 2308 .needed = vmxnet3_mc_list_needed, 2309 .fields = (VMStateField[]) { 2310 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 2311 mcast_list_buff_size), 2312 VMSTATE_END_OF_LIST() 2313 } 2314 }; 2315 2316 static const VMStateDescription vmstate_vmxnet3_ring = { 2317 .name = "vmxnet3-ring", 2318 .version_id = 0, 2319 .fields = (VMStateField[]) { 2320 VMSTATE_UINT64(pa, Vmxnet3Ring), 2321 VMSTATE_UINT32(size, Vmxnet3Ring), 2322 VMSTATE_UINT32(cell_size, Vmxnet3Ring), 2323 VMSTATE_UINT32(next, Vmxnet3Ring), 2324 VMSTATE_UINT8(gen, Vmxnet3Ring), 2325 VMSTATE_END_OF_LIST() 2326 } 2327 }; 2328 2329 static const VMStateDescription vmstate_vmxnet3_tx_stats = { 2330 .name = "vmxnet3-tx-stats", 2331 .version_id = 0, 2332 .fields = (VMStateField[]) { 2333 VMSTATE_UINT64(TSOPktsTxOK, struct UPT1_TxStats), 2334 VMSTATE_UINT64(TSOBytesTxOK, struct UPT1_TxStats), 2335 VMSTATE_UINT64(ucastPktsTxOK, struct UPT1_TxStats), 2336 VMSTATE_UINT64(ucastBytesTxOK, struct UPT1_TxStats), 2337 VMSTATE_UINT64(mcastPktsTxOK, struct UPT1_TxStats), 2338 VMSTATE_UINT64(mcastBytesTxOK, struct UPT1_TxStats), 2339 VMSTATE_UINT64(bcastPktsTxOK, struct UPT1_TxStats), 2340 VMSTATE_UINT64(bcastBytesTxOK, struct UPT1_TxStats), 2341 VMSTATE_UINT64(pktsTxError, struct UPT1_TxStats), 2342 VMSTATE_UINT64(pktsTxDiscard, struct UPT1_TxStats), 2343 VMSTATE_END_OF_LIST() 2344 } 2345 }; 2346 2347 static const VMStateDescription vmstate_vmxnet3_txq_descr = { 2348 .name = "vmxnet3-txq-descr", 2349 .version_id = 0, 2350 .fields = (VMStateField[]) { 2351 VMSTATE_STRUCT(tx_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring, 2352 Vmxnet3Ring), 2353 VMSTATE_STRUCT(comp_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring, 2354 Vmxnet3Ring), 2355 VMSTATE_UINT8(intr_idx, Vmxnet3TxqDescr), 2356 VMSTATE_UINT64(tx_stats_pa, Vmxnet3TxqDescr), 2357 VMSTATE_STRUCT(txq_stats, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_tx_stats, 2358 struct UPT1_TxStats), 2359 VMSTATE_END_OF_LIST() 2360 } 2361 }; 2362 2363 static const VMStateDescription vmstate_vmxnet3_rx_stats = { 2364 .name = "vmxnet3-rx-stats", 2365 .version_id = 0, 2366 .fields = (VMStateField[]) { 2367 VMSTATE_UINT64(LROPktsRxOK, struct UPT1_RxStats), 2368 VMSTATE_UINT64(LROBytesRxOK, struct UPT1_RxStats), 2369 VMSTATE_UINT64(ucastPktsRxOK, struct UPT1_RxStats), 2370 VMSTATE_UINT64(ucastBytesRxOK, struct UPT1_RxStats), 2371 VMSTATE_UINT64(mcastPktsRxOK, struct UPT1_RxStats), 2372 VMSTATE_UINT64(mcastBytesRxOK, struct UPT1_RxStats), 2373 VMSTATE_UINT64(bcastPktsRxOK, struct UPT1_RxStats), 2374 VMSTATE_UINT64(bcastBytesRxOK, struct UPT1_RxStats), 2375 VMSTATE_UINT64(pktsRxOutOfBuf, struct UPT1_RxStats), 2376 VMSTATE_UINT64(pktsRxError, struct UPT1_RxStats), 2377 VMSTATE_END_OF_LIST() 2378 } 2379 }; 2380 2381 static const VMStateDescription vmstate_vmxnet3_rxq_descr = { 2382 .name = "vmxnet3-rxq-descr", 2383 .version_id = 0, 2384 .fields = (VMStateField[]) { 2385 VMSTATE_STRUCT_ARRAY(rx_ring, Vmxnet3RxqDescr, 2386 VMXNET3_RX_RINGS_PER_QUEUE, 0, 2387 vmstate_vmxnet3_ring, Vmxnet3Ring), 2388 VMSTATE_STRUCT(comp_ring, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_ring, 2389 Vmxnet3Ring), 2390 VMSTATE_UINT8(intr_idx, Vmxnet3RxqDescr), 2391 VMSTATE_UINT64(rx_stats_pa, Vmxnet3RxqDescr), 2392 VMSTATE_STRUCT(rxq_stats, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_rx_stats, 2393 struct UPT1_RxStats), 2394 VMSTATE_END_OF_LIST() 2395 } 2396 }; 2397 2398 static int vmxnet3_post_load(void *opaque, int version_id) 2399 { 2400 VMXNET3State *s = opaque; 2401 2402 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags); 2403 net_rx_pkt_init(&s->rx_pkt); 2404 2405 if (s->msix_used) { 2406 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS); 2407 } 2408 2409 if (!vmxnet3_validate_queues(s)) { 2410 return -1; 2411 } 2412 vmxnet3_validate_interrupts(s); 2413 2414 return 0; 2415 } 2416 2417 static const VMStateDescription vmstate_vmxnet3_int_state = { 2418 .name = "vmxnet3-int-state", 2419 .version_id = 0, 2420 .fields = (VMStateField[]) { 2421 VMSTATE_BOOL(is_masked, Vmxnet3IntState), 2422 VMSTATE_BOOL(is_pending, Vmxnet3IntState), 2423 VMSTATE_BOOL(is_asserted, Vmxnet3IntState), 2424 VMSTATE_END_OF_LIST() 2425 } 2426 }; 2427 2428 static const VMStateDescription vmstate_vmxnet3 = { 2429 .name = "vmxnet3", 2430 .version_id = 1, 2431 .minimum_version_id = 1, 2432 .pre_save = vmxnet3_pre_save, 2433 .post_load = vmxnet3_post_load, 2434 .fields = (VMStateField[]) { 2435 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State), 2436 VMSTATE_MSIX(parent_obj, VMXNET3State), 2437 VMSTATE_BOOL(rx_packets_compound, VMXNET3State), 2438 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State), 2439 VMSTATE_BOOL(lro_supported, VMXNET3State), 2440 VMSTATE_UINT32(rx_mode, VMXNET3State), 2441 VMSTATE_UINT32(mcast_list_len, VMXNET3State), 2442 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State), 2443 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE), 2444 VMSTATE_UINT32(mtu, VMXNET3State), 2445 VMSTATE_UINT16(max_rx_frags, VMXNET3State), 2446 VMSTATE_UINT32(max_tx_frags, VMXNET3State), 2447 VMSTATE_UINT8(event_int_idx, VMXNET3State), 2448 VMSTATE_BOOL(auto_int_masking, VMXNET3State), 2449 VMSTATE_UINT8(txq_num, VMXNET3State), 2450 VMSTATE_UINT8(rxq_num, VMXNET3State), 2451 VMSTATE_UINT32(device_active, VMXNET3State), 2452 VMSTATE_UINT32(last_command, VMXNET3State), 2453 VMSTATE_UINT32(link_status_and_speed, VMXNET3State), 2454 VMSTATE_UINT32(temp_mac, VMXNET3State), 2455 VMSTATE_UINT64(drv_shmem, VMXNET3State), 2456 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State), 2457 2458 VMSTATE_STRUCT_ARRAY(txq_descr, VMXNET3State, 2459 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, vmstate_vmxnet3_txq_descr, 2460 Vmxnet3TxqDescr), 2461 VMSTATE_STRUCT_ARRAY(rxq_descr, VMXNET3State, 2462 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, vmstate_vmxnet3_rxq_descr, 2463 Vmxnet3RxqDescr), 2464 VMSTATE_STRUCT_ARRAY(interrupt_states, VMXNET3State, 2465 VMXNET3_MAX_INTRS, 0, vmstate_vmxnet3_int_state, 2466 Vmxnet3IntState), 2467 2468 VMSTATE_END_OF_LIST() 2469 }, 2470 .subsections = (const VMStateDescription*[]) { 2471 &vmxstate_vmxnet3_mcast_list, 2472 NULL 2473 } 2474 }; 2475 2476 static Property vmxnet3_properties[] = { 2477 DEFINE_NIC_PROPERTIES(VMXNET3State, conf), 2478 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags, 2479 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false), 2480 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags, 2481 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false), 2482 DEFINE_PROP_END_OF_LIST(), 2483 }; 2484 2485 static void vmxnet3_realize(DeviceState *qdev, Error **errp) 2486 { 2487 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev); 2488 PCIDevice *pci_dev = PCI_DEVICE(qdev); 2489 VMXNET3State *s = VMXNET3(qdev); 2490 2491 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) { 2492 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2493 } 2494 2495 vc->parent_dc_realize(qdev, errp); 2496 } 2497 2498 static void vmxnet3_class_init(ObjectClass *class, void *data) 2499 { 2500 DeviceClass *dc = DEVICE_CLASS(class); 2501 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 2502 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class); 2503 2504 c->realize = vmxnet3_pci_realize; 2505 c->exit = vmxnet3_pci_uninit; 2506 c->vendor_id = PCI_VENDOR_ID_VMWARE; 2507 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2508 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION; 2509 c->romfile = "efi-vmxnet3.rom"; 2510 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 2511 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 2512 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2513 device_class_set_parent_realize(dc, vmxnet3_realize, 2514 &vc->parent_dc_realize); 2515 dc->desc = "VMWare Paravirtualized Ethernet v3"; 2516 dc->reset = vmxnet3_qdev_reset; 2517 dc->vmsd = &vmstate_vmxnet3; 2518 device_class_set_props(dc, vmxnet3_properties); 2519 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 2520 } 2521 2522 static const TypeInfo vmxnet3_info = { 2523 .name = TYPE_VMXNET3, 2524 .parent = TYPE_PCI_DEVICE, 2525 .class_size = sizeof(VMXNET3Class), 2526 .instance_size = sizeof(VMXNET3State), 2527 .class_init = vmxnet3_class_init, 2528 .instance_init = vmxnet3_instance_init, 2529 .interfaces = (InterfaceInfo[]) { 2530 { INTERFACE_PCIE_DEVICE }, 2531 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2532 { } 2533 }, 2534 }; 2535 2536 static void vmxnet3_register_types(void) 2537 { 2538 VMW_CBPRN("vmxnet3_register_types called..."); 2539 type_register_static(&vmxnet3_info); 2540 } 2541 2542 type_init(vmxnet3_register_types) 2543