1 /* 2 * QEMU VMWARE paravirtual devices - auxiliary code 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: 9 * Dmitry Fleytman <dmitry@daynix.com> 10 * Yan Vugenfirer <yan@daynix.com> 11 * 12 * This work is licensed under the terms of the GNU GPL, version 2 or later. 13 * See the COPYING file in the top-level directory. 14 * 15 */ 16 17 #ifndef VMWARE_UTILS_H 18 #define VMWARE_UTILS_H 19 20 #include "qemu/range.h" 21 22 #ifndef VMW_SHPRN 23 #define VMW_SHPRN(fmt, ...) do {} while (0) 24 #endif 25 26 /* 27 * Shared memory access functions with byte swap support 28 * Each function contains printout for reverse-engineering needs 29 * 30 */ 31 static inline void 32 vmw_shmem_read(hwaddr addr, void *buf, int len) 33 { 34 VMW_SHPRN("SHMEM r: %" PRIx64 ", len: %d to %p", addr, len, buf); 35 cpu_physical_memory_read(addr, buf, len); 36 } 37 38 static inline void 39 vmw_shmem_write(hwaddr addr, void *buf, int len) 40 { 41 VMW_SHPRN("SHMEM w: %" PRIx64 ", len: %d to %p", addr, len, buf); 42 cpu_physical_memory_write(addr, buf, len); 43 } 44 45 static inline void 46 vmw_shmem_rw(hwaddr addr, void *buf, int len, int is_write) 47 { 48 VMW_SHPRN("SHMEM r/w: %" PRIx64 ", len: %d (to %p), is write: %d", 49 addr, len, buf, is_write); 50 51 cpu_physical_memory_rw(addr, buf, len, is_write); 52 } 53 54 static inline void 55 vmw_shmem_set(hwaddr addr, uint8 val, int len) 56 { 57 int i; 58 VMW_SHPRN("SHMEM set: %" PRIx64 ", len: %d (value 0x%X)", addr, len, val); 59 60 for (i = 0; i < len; i++) { 61 cpu_physical_memory_write(addr + i, &val, 1); 62 } 63 } 64 65 static inline uint32_t 66 vmw_shmem_ld8(hwaddr addr) 67 { 68 uint8_t res = ldub_phys(addr); 69 VMW_SHPRN("SHMEM load8: %" PRIx64 " (value 0x%X)", addr, res); 70 return res; 71 } 72 73 static inline void 74 vmw_shmem_st8(hwaddr addr, uint8_t value) 75 { 76 VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value); 77 stb_phys(addr, value); 78 } 79 80 static inline uint32_t 81 vmw_shmem_ld16(hwaddr addr) 82 { 83 uint16_t res = lduw_le_phys(addr); 84 VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res); 85 return res; 86 } 87 88 static inline void 89 vmw_shmem_st16(hwaddr addr, uint16_t value) 90 { 91 VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value); 92 stw_le_phys(addr, value); 93 } 94 95 static inline uint32_t 96 vmw_shmem_ld32(hwaddr addr) 97 { 98 uint32_t res = ldl_le_phys(addr); 99 VMW_SHPRN("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res); 100 return res; 101 } 102 103 static inline void 104 vmw_shmem_st32(hwaddr addr, uint32_t value) 105 { 106 VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value); 107 stl_le_phys(addr, value); 108 } 109 110 static inline uint64_t 111 vmw_shmem_ld64(hwaddr addr) 112 { 113 uint64_t res = ldq_le_phys(addr); 114 VMW_SHPRN("SHMEM load64: %" PRIx64 " (value %" PRIx64 ")", addr, res); 115 return res; 116 } 117 118 static inline void 119 vmw_shmem_st64(hwaddr addr, uint64_t value) 120 { 121 VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value); 122 stq_le_phys(addr, value); 123 } 124 125 /* Macros for simplification of operations on array-style registers */ 126 127 /* 128 * Whether <addr> lies inside of array-style register defined by <base>, 129 * number of elements (<cnt>) and element size (<regsize>) 130 * 131 */ 132 #define VMW_IS_MULTIREG_ADDR(addr, base, cnt, regsize) \ 133 range_covers_byte(base, cnt * regsize, addr) 134 135 /* 136 * Returns index of given register (<addr>) in array-style register defined by 137 * <base> and element size (<regsize>) 138 * 139 */ 140 #define VMW_MULTIREG_IDX_BY_ADDR(addr, base, regsize) \ 141 (((addr) - (base)) / (regsize)) 142 143 #endif 144