1# See docs/devel/tracing.txt for syntax documentation. 2 3# hw/net/lance.c 4lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" 5lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" 6 7# hw/net/milkymist-minimac2.c 8milkymist_minimac2_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" 9milkymist_minimac2_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" 10milkymist_minimac2_mdio_write(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr 0x%02x addr 0x%02x value 0x%04x" 11milkymist_minimac2_mdio_read(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr 0x%02x addr 0x%02x value 0x%04x" 12milkymist_minimac2_tx_frame(uint32_t length) "length %u" 13milkymist_minimac2_rx_frame(const void *buf, uint32_t length) "buf %p length %u" 14milkymist_minimac2_rx_transfer(const void *buf, uint32_t length) "buf %p length %d" 15milkymist_minimac2_raise_irq_rx(void) "Raise IRQ RX" 16milkymist_minimac2_lower_irq_rx(void) "Lower IRQ RX" 17milkymist_minimac2_pulse_irq_tx(void) "Pulse IRQ TX" 18 19# hw/net/mipsnet.c 20mipsnet_send(uint32_t size) "sending len=%u" 21mipsnet_receive(uint32_t size) "receiving len=%u" 22mipsnet_read(uint64_t addr, uint32_t val) "read addr=0x%" PRIx64 " val=0x%x" 23mipsnet_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64 24mipsnet_irq(uint32_t isr, uint32_t intctl) "set irq to %d (0x%02x)" 25 26# hw/net/opencores_eth.c 27open_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x" 28open_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x" 29open_eth_update_irq(uint32_t v) "IRQ <- 0x%x" 30open_eth_receive(unsigned len) "RX: len: %u" 31open_eth_receive_mcast(unsigned idx, uint32_t h0, uint32_t h1) "MCAST: idx = %u, hash: %08x:%08x" 32open_eth_receive_reject(void) "RX: rejected" 33open_eth_receive_desc(uint32_t addr, uint32_t len_flags) "RX: 0x%08x, len_flags: 0x%08x" 34open_eth_start_xmit(uint32_t addr, unsigned len, unsigned tx_len) "TX: 0x%08x, len: %u, tx_len: %u" 35open_eth_reg_read(uint32_t addr, uint32_t v) "MAC[0x%02x] -> 0x%08x" 36open_eth_reg_write(uint32_t addr, uint32_t v) "MAC[0x%02x] <- 0x%08x" 37open_eth_desc_read(uint32_t addr, uint32_t v) "DESC[0x%04x] -> 0x%08x" 38open_eth_desc_write(uint32_t addr, uint32_t v) "DESC[0x%04x] <- 0x%08x" 39 40# hw/net/pcnet.c 41pcnet_s_reset(void *s) "s=%p" 42pcnet_user_int(void *s) "s=%p" 43pcnet_isr_change(void *s, uint32_t isr, uint32_t isr_old) "s=%p INTA=%d<=%d" 44pcnet_init(void *s, uint64_t init_addr) "s=%p init_addr=0x%"PRIx64 45pcnet_rlen_tlen(void *s, uint32_t rlen, uint32_t tlen) "s=%p rlen=%d tlen=%d" 46pcnet_ss32_rdra_tdra(void *s, uint32_t ss32, uint32_t rdra, uint32_t rcvrl, uint32_t tdra, uint32_t xmtrl) "s=%p ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]" 47 48# hw/net/pcnet-pci.c 49pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x" 50pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x" 51pcnet_ioport_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d" 52pcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned size) "opaque=%p addr=0x%"PRIx64" data=0x%"PRIx64" size=%d" 53pcnet_mmio_writeb(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x" 54pcnet_mmio_writew(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x" 55pcnet_mmio_writel(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x" 56pcnet_mmio_readb(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x" 57pcnet_mmio_readw(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x" 58pcnet_mmio_readl(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x" 59 60# hw/net/net_rx_pkt.c 61net_rx_pkt_parsed(bool ip4, bool ip6, bool udp, bool tcp, size_t l3o, size_t l4o, size_t l5o) "RX packet parsed: ip4: %d, ip6: %d, udp: %d, tcp: %d, l3 offset: %zu, l4 offset: %zu, l5 offset: %zu" 62net_rx_pkt_l4_csum_validate_entry(void) "Starting L4 checksum validation" 63net_rx_pkt_l4_csum_validate_not_xxp(void) "Not a TCP/UDP packet" 64net_rx_pkt_l4_csum_validate_udp_with_no_checksum(void) "UDP packet without checksum" 65net_rx_pkt_l4_csum_validate_ip4_fragment(void) "IP4 fragment" 66net_rx_pkt_l4_csum_validate_csum(bool csum_valid) "Checksum valid: %d" 67 68net_rx_pkt_l4_csum_calc_entry(void) "Starting L4 checksum calculation" 69net_rx_pkt_l4_csum_calc_ip4_udp(void) "IP4/UDP packet" 70net_rx_pkt_l4_csum_calc_ip4_tcp(void) "IP4/TCP packet" 71net_rx_pkt_l4_csum_calc_ip6_udp(void) "IP6/UDP packet" 72net_rx_pkt_l4_csum_calc_ip6_tcp(void) "IP6/TCP packet" 73net_rx_pkt_l4_csum_calc_ph_csum(uint32_t cntr, uint16_t csl) "Pseudo-header: checksum counter %u, length %u" 74net_rx_pkt_l4_csum_calc_csum(size_t l4hdr_off, uint16_t csl, uint32_t cntr, uint16_t csum) "L4 Checksum: L4 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X" 75 76net_rx_pkt_l4_csum_fix_entry(void) "Starting L4 checksum correction" 77net_rx_pkt_l4_csum_fix_tcp(uint32_t l4_cso) "TCP packet, L4 cso: %u" 78net_rx_pkt_l4_csum_fix_udp(uint32_t l4_cso) "UDP packet, L4 cso: %u" 79net_rx_pkt_l4_csum_fix_not_xxp(void) "Not an IP4 packet" 80net_rx_pkt_l4_csum_fix_ip4_fragment(void) "IP4 fragment" 81net_rx_pkt_l4_csum_fix_udp_with_no_checksum(void) "UDP packet without checksum" 82net_rx_pkt_l4_csum_fix_csum(uint32_t cso, uint16_t csum) "L4 Checksum: Offset: %u, value 0x%X" 83 84net_rx_pkt_l3_csum_validate_entry(void) "Starting L3 checksum validation" 85net_rx_pkt_l3_csum_validate_not_ip4(void) "Not an IP4 packet" 86net_rx_pkt_l3_csum_validate_csum(size_t l3hdr_off, uint32_t csl, uint32_t cntr, uint16_t csum, bool csum_valid) "L3 Checksum: L3 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X, valid: %d" 87 88net_rx_pkt_rss_ip4(void) "Calculating IPv4 RSS hash" 89net_rx_pkt_rss_ip4_tcp(void) "Calculating IPv4/TCP RSS hash" 90net_rx_pkt_rss_ip6_tcp(void) "Calculating IPv6/TCP RSS hash" 91net_rx_pkt_rss_ip6(void) "Calculating IPv6 RSS hash" 92net_rx_pkt_rss_ip6_ex(void) "Calculating IPv6/EX RSS hash" 93net_rx_pkt_rss_hash(size_t rss_length, uint32_t rss_hash) "RSS hash for %zu bytes: 0x%X" 94net_rx_pkt_rss_add_chunk(void* ptr, size_t size, size_t input_offset) "Add RSS chunk %p, %zu bytes, RSS input offset %zu bytes" 95 96# hw/net/e1000x_common.c 97e1000x_rx_can_recv_disabled(bool link_up, bool rx_enabled, bool pci_master) "link_up: %d, rx_enabled %d, pci_master %d" 98e1000x_vlan_is_vlan_pkt(bool is_vlan_pkt, uint16_t eth_proto, uint16_t vet) "Is VLAN packet: %d, ETH proto: 0x%X, VET: 0x%X" 99e1000x_rx_flt_ucast_match(uint32_t idx, uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x" 100e1000x_rx_flt_ucast_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x" 101e1000x_rx_flt_inexact_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint32_t mo, uint32_t mta, uint32_t mta_val) "inexact mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] 0x%x" 102e1000x_rx_link_down(uint32_t status_reg) "Received packet dropped because the link is down STATUS = %u" 103e1000x_rx_disabled(uint32_t rctl_reg) "Received packet dropped because receive is disabled RCTL = %u" 104e1000x_rx_oversized(size_t size) "Received packet dropped because it was oversized (%zu bytes)" 105e1000x_mac_indicate(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Indicating MAC to guest: %02x:%02x:%02x:%02x:%02x:%02x" 106e1000x_link_negotiation_start(void) "Start link auto negotiation" 107e1000x_link_negotiation_done(void) "Auto negotiation is completed" 108 109# hw/net/e1000e_core.c 110e1000e_core_write(uint64_t index, uint32_t size, uint64_t val) "Write to register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 111e1000e_core_read(uint64_t index, uint32_t size, uint64_t val) "Read from register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 112e1000e_core_mdic_read(uint8_t page, uint32_t addr, uint32_t data) "MDIC READ: PHY[%u][%u] = 0x%x" 113e1000e_core_mdic_read_unhandled(uint8_t page, uint32_t addr) "MDIC READ: PHY[%u][%u] UNHANDLED" 114e1000e_core_mdic_write(uint8_t page, uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u][%u] = 0x%x" 115e1000e_core_mdic_write_unhandled(uint8_t page, uint32_t addr) "MDIC WRITE: PHY[%u][%u] UNHANDLED" 116e1000e_core_ctrl_write(uint64_t index, uint32_t val) "Write CTRL register 0x%"PRIx64", value: 0x%X" 117e1000e_core_ctrl_sw_reset(void) "Doing SW reset" 118e1000e_core_ctrl_phy_reset(void) "Doing PHY reset" 119 120e1000e_link_autoneg_flowctl(bool enabled) "Auto-negotiated flow control state is %d" 121e1000e_link_set_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Set link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d" 122e1000e_link_read_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Get link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d" 123e1000e_link_set_ext_params(bool asd_check, bool speed_select_bypass) "Set extended link params: ASD check: %d, Speed select bypass: %d" 124e1000e_link_status(bool link_up, bool full_dplx, uint32_t speed, uint32_t asdv) "Link up: %d, Duplex: %d, Speed: %d, ASDV: %d" 125e1000e_link_status_changed(bool status) "New link status: %d" 126 127e1000e_wrn_regs_write_ro(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to RO register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 128e1000e_wrn_regs_write_unknown(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to unknown register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 129e1000e_wrn_regs_read_unknown(uint64_t index, uint32_t size) "WARNING: Read from unknown register 0x%"PRIx64", %d byte(s)" 130e1000e_wrn_regs_read_trivial(uint32_t index) "WARNING: Reading register at offset: 0x%05x. It is not fully implemented." 131e1000e_wrn_regs_write_trivial(uint32_t index) "WARNING: Writing to register at offset: 0x%05x. It is not fully implemented." 132e1000e_wrn_no_ts_support(void) "WARNING: Guest requested TX timestamping which is not supported" 133e1000e_wrn_no_snap_support(void) "WARNING: Guest requested TX SNAP header update which is not supported" 134e1000e_wrn_iscsi_filtering_not_supported(void) "WARNING: Guest requested iSCSI filtering which is not supported" 135e1000e_wrn_nfsw_filtering_not_supported(void) "WARNING: Guest requested NFS write filtering which is not supported" 136e1000e_wrn_nfsr_filtering_not_supported(void) "WARNING: Guest requested NFS read filtering which is not supported" 137 138e1000e_tx_disabled(void) "TX Disabled" 139e1000e_tx_descr(void *addr, uint32_t lower, uint32_t upper) "%p : %x %x" 140 141e1000e_ring_free_space(int ridx, uint32_t rdlen, uint32_t rdh, uint32_t rdt) "ring #%d: LEN: %u, DH: %u, DT: %u" 142 143e1000e_rx_can_recv_rings_full(void) "Cannot receive: all rings are full" 144e1000e_rx_can_recv(void) "Can receive" 145e1000e_rx_has_buffers(int ridx, uint32_t free_desc, size_t total_size, uint32_t desc_buf_size) "ring #%d: free descr: %u, packet size %zu, descr buffer size %u" 146e1000e_rx_null_descriptor(void) "Null RX descriptor!!" 147e1000e_rx_flt_vlan_mismatch(uint16_t vid) "VID mismatch: 0x%X" 148e1000e_rx_flt_vlan_match(uint16_t vid) "VID match: 0x%X" 149e1000e_rx_desc_ps_read(uint64_t a0, uint64_t a1, uint64_t a2, uint64_t a3) "buffers: [0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64"]" 150e1000e_rx_desc_ps_write(uint16_t a0, uint16_t a1, uint16_t a2, uint16_t a3) "bytes written: [%u, %u, %u, %u]" 151e1000e_rx_desc_buff_sizes(uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3) "buffer sizes: [%u, %u, %u, %u]" 152e1000e_rx_desc_len(uint8_t rx_desc_len) "RX descriptor length: %u" 153e1000e_rx_desc_buff_write(uint8_t idx, uint64_t addr, uint16_t offset, const void* source, uint32_t len) "buffer #%u, addr: 0x%"PRIx64", offset: %u, from: %p, length: %u" 154e1000e_rx_descr(int ridx, uint64_t base, uint8_t len) "Next RX descriptor: ring #%d, PA: 0x%"PRIx64", length: %u" 155e1000e_rx_set_rctl(uint32_t rctl) "RCTL = 0x%x" 156e1000e_rx_receive_iov(int iovcnt) "Received vector of %d fragments" 157e1000e_rx_flt_dropped(void) "Received packet dropped by RX filter" 158e1000e_rx_written_to_guest(uint32_t causes) "Received packet written to guest (ICR causes %u)" 159e1000e_rx_not_written_to_guest(uint32_t causes) "Received packet NOT written to guest (ICR causes %u)" 160e1000e_rx_interrupt_set(uint32_t causes) "Receive interrupt set (ICR causes %u)" 161e1000e_rx_interrupt_delayed(uint32_t causes) "Receive interrupt delayed (ICR causes %u)" 162e1000e_rx_set_cso(int cso_state) "RX CSO state set to %d" 163e1000e_rx_set_rdt(int queue_idx, uint32_t val) "Setting RDT[%d] = %u" 164e1000e_rx_set_rfctl(uint32_t val) "Setting RFCTL = 0x%X" 165e1000e_rx_start_recv(void) 166 167e1000e_rx_rss_started(void) "Starting RSS processing" 168e1000e_rx_rss_disabled(void) "RSS is disabled" 169e1000e_rx_rss_type(uint32_t type) "RSS type is %u" 170e1000e_rx_rss_ip4(bool isfragment, bool istcp, uint32_t mrqc, bool tcpipv4_enabled, bool ipv4_enabled) "RSS IPv4: fragment %d, tcp %d, mrqc 0x%X, tcpipv4 enabled %d, ipv4 enabled %d" 171e1000e_rx_rss_ip6_rfctl(uint32_t rfctl) "RSS IPv6: rfctl 0x%X" 172e1000e_rx_rss_ip6(bool ex_dis, bool new_ex_dis, bool istcp, bool has_ext_headers, bool ex_dst_valid, bool ex_src_valid, uint32_t mrqc, bool tcpipv6_enabled, bool ipv6ex_enabled, bool ipv6_enabled) "RSS IPv6: ex_dis: %d, new_ex_dis: %d, tcp %d, has_ext_headers %d, ex_dst_valid %d, ex_src_valid %d, mrqc 0x%X, tcpipv6 enabled %d, ipv6ex enabled %d, ipv6 enabled %d" 173e1000e_rx_rss_dispatched_to_queue(int queue_idx) "Packet being dispatched to queue %d" 174 175e1000e_rx_metadata_protocols(bool isip4, bool isip6, bool isudp, bool istcp) "protocols: ip4: %d, ip6: %d, udp: %d, tcp: %d" 176e1000e_rx_metadata_vlan(uint16_t vlan_tag) "VLAN tag is 0x%X" 177e1000e_rx_metadata_rss(uint32_t rss, uint32_t mrq) "RSS data: rss: 0x%X, mrq: 0x%X" 178e1000e_rx_metadata_ip_id(uint16_t ip_id) "the IPv4 ID is 0x%X" 179e1000e_rx_metadata_ack(void) "the packet is TCP ACK" 180e1000e_rx_metadata_pkt_type(uint32_t pkt_type) "the packet type is %u" 181e1000e_rx_metadata_no_virthdr(void) "the packet has no virt-header" 182e1000e_rx_metadata_virthdr_no_csum_info(void) "virt-header does not contain checksum info" 183e1000e_rx_metadata_l3_cso_disabled(void) "IP4 CSO is disabled" 184e1000e_rx_metadata_l4_cso_disabled(void) "TCP/UDP CSO is disabled" 185e1000e_rx_metadata_l3_csum_validation_failed(void) "Cannot validate L3 checksum" 186e1000e_rx_metadata_l4_csum_validation_failed(void) "Cannot validate L4 checksum" 187e1000e_rx_metadata_status_flags(uint32_t status_flags) "status_flags is 0x%X" 188e1000e_rx_metadata_ipv6_sum_disabled(void) "IPv6 RX checksummimg disabled by RFCTL" 189e1000e_rx_metadata_ipv6_filtering_disabled(void) "IPv6 RX filtering disabled by RFCTL" 190 191e1000e_vlan_vet(uint16_t vet) "Setting VLAN ethernet type 0x%X" 192 193e1000e_irq_msi_notify(uint32_t cause) "MSI notify 0x%x" 194e1000e_irq_throttling_no_pending_interrupts(void) "No pending interrupts to notify" 195e1000e_irq_msi_notify_postponed(void) "Sending MSI postponed by ITR" 196e1000e_irq_legacy_notify_postponed(void) "Raising legacy IRQ postponed by ITR" 197e1000e_irq_throttling_no_pending_vec(int idx) "No pending interrupts for vector %d" 198e1000e_irq_msix_notify_postponed_vec(int idx) "Sending MSI-X postponed by EITR[%d]" 199e1000e_irq_legacy_notify(bool level) "IRQ line state: %d" 200e1000e_irq_msix_notify_vec(uint32_t vector) "MSI-X notify vector 0x%x" 201e1000e_irq_postponed_by_xitr(uint32_t reg) "Interrupt postponed by [E]ITR register 0x%x" 202e1000e_irq_clear_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Clearing IMS bits 0x%x: 0x%x --> 0x%x" 203e1000e_irq_set_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Setting IMS bits 0x%x: 0x%x --> 0x%x" 204e1000e_irq_fix_icr_asserted(uint32_t new_val) "ICR_ASSERTED bit fixed: 0x%x" 205e1000e_irq_add_msi_other(uint32_t new_val) "ICR_OTHER bit added: 0x%x" 206e1000e_irq_pending_interrupts(uint32_t pending, uint32_t icr, uint32_t ims) "ICR PENDING: 0x%x (ICR: 0x%x, IMS: 0x%x)" 207e1000e_irq_set_cause_entry(uint32_t val, uint32_t icr) "Going to set IRQ cause 0x%x, ICR: 0x%x" 208e1000e_irq_set_cause_exit(uint32_t val, uint32_t icr) "Set IRQ cause 0x%x, ICR: 0x%x" 209e1000e_irq_icr_write(uint32_t bits, uint32_t old_icr, uint32_t new_icr) "Clearing ICR bits 0x%x: 0x%x --> 0x%x" 210e1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x" 211e1000e_irq_icr_process_iame(void) "Clearing IMS bits due to IAME" 212e1000e_irq_read_ics(uint32_t ics) "Current ICS: 0x%x" 213e1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x" 214e1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR read. Current ICR: 0x%x" 215e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0x%x" 216e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS" 217e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME" 218e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X" 219e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bits due to EIAC, ICR: 0x%X, EIAC: 0x%X" 220e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to IMC write 0x%x" 221e1000e_irq_fire_delayed_interrupts(void) "Firing delayed interrupts" 222e1000e_irq_rearm_timer(uint32_t reg, int64_t delay_ns) "Mitigation timer armed for register 0x%X, delay %"PRId64" ns" 223e1000e_irq_throttling_timer(uint32_t reg) "Mitigation timer shot for register 0x%X" 224e1000e_irq_rdtr_fpd_running(void) "FPD written while RDTR was running" 225e1000e_irq_rdtr_fpd_not_running(void) "FPD written while RDTR was not running" 226e1000e_irq_tidv_fpd_running(void) "FPD written while TIDV was running" 227e1000e_irq_tidv_fpd_not_running(void) "FPD written while TIDV was not running" 228e1000e_irq_eitr_set(uint32_t eitr_num, uint32_t val) "EITR[%u] = %u" 229e1000e_irq_itr_set(uint32_t val) "ITR = %u" 230e1000e_irq_fire_all_timers(uint32_t val) "Firing all delay/throttling timers on all interrupts enable (0x%X written to IMS)" 231e1000e_irq_adding_delayed_causes(uint32_t val, uint32_t icr) "Merging delayed causes 0x%X to ICR 0x%X" 232e1000e_irq_msix_pending_clearing(uint32_t cause, uint32_t int_cfg, uint32_t vec) "Clearing MSI-X pending bit for cause 0x%x, IVAR config 0x%x, vector %u" 233 234e1000e_wrn_msix_vec_wrong(uint32_t cause, uint32_t cfg) "Invalid configuration for cause 0x%x: 0x%x" 235e1000e_wrn_msix_invalid(uint32_t cause, uint32_t cfg) "Invalid entry for cause 0x%x: 0x%x" 236 237e1000e_mac_set_permanent(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set permanent MAC: %02x:%02x:%02x:%02x:%02x:%02x" 238e1000e_mac_set_sw(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set SW MAC: %02x:%02x:%02x:%02x:%02x:%02x" 239 240# hw/net/e1000e.c 241e1000e_cb_pci_realize(void) "E1000E PCI realize entry" 242e1000e_cb_pci_uninit(void) "E1000E PCI unit entry" 243e1000e_cb_qdev_reset(void) "E1000E qdev reset entry" 244e1000e_cb_pre_save(void) "E1000E pre save entry" 245e1000e_cb_post_load(void) "E1000E post load entry" 246 247e1000e_io_write_addr(uint64_t addr) "IOADDR write 0x%"PRIx64 248e1000e_io_write_data(uint64_t addr, uint64_t val) "IODATA write 0x%"PRIx64", value: 0x%"PRIx64 249e1000e_io_read_addr(uint64_t addr) "IOADDR read 0x%"PRIx64 250e1000e_io_read_data(uint64_t addr, uint64_t val) "IODATA read 0x%"PRIx64", value: 0x%"PRIx64 251e1000e_wrn_io_write_unknown(uint64_t addr) "IO write unknown address 0x%"PRIx64 252e1000e_wrn_io_read_unknown(uint64_t addr) "IO read unknown address 0x%"PRIx64 253e1000e_wrn_io_addr_undefined(uint64_t addr) "IO undefined register 0x%"PRIx64 254e1000e_wrn_io_addr_flash(uint64_t addr) "IO flash access (0x%"PRIx64") not implemented" 255e1000e_wrn_io_addr_unknown(uint64_t addr) "IO unknown register 0x%"PRIx64 256 257e1000e_msi_init_fail(int32_t res) "Failed to initialize MSI, error %d" 258e1000e_msix_init_fail(int32_t res) "Failed to initialize MSI-X, error %d" 259e1000e_msix_use_vector_fail(uint32_t vec, int32_t res) "Failed to use MSI-X vector %d, error %d" 260 261e1000e_cfg_support_virtio(bool support) "Virtio header supported: %d" 262 263e1000e_vm_state_running(void) "VM state is running" 264e1000e_vm_state_stopped(void) "VM state is stopped" 265 266# hw/net/spapr_llan.c 267spapr_vlan_get_rx_bd_from_pool_found(int pool, int32_t count, uint32_t rx_bufs) "pool=%d count=%"PRId32" rxbufs=%"PRIu32 268spapr_vlan_get_rx_bd_from_page(int buf_ptr, uint64_t bd) "use_buf_ptr=%d bd=0x%016"PRIx64 269spapr_vlan_get_rx_bd_from_page_found(uint32_t use_buf_ptr, uint32_t rx_bufs) "ptr=%"PRIu32" rxbufs=%"PRIu32 270spapr_vlan_receive(const char *id, uint32_t rx_bufs) "[%s] rx_bufs=%"PRIu32 271spapr_vlan_receive_dma_completed(void) "DMA write completed" 272spapr_vlan_receive_wrote(uint64_t ptr, uint64_t hi, uint64_t lo) "rxq entry (ptr=0x%"PRIx64"): 0x%016"PRIx64" 0x%016"PRIx64 273spapr_vlan_add_rxbuf_to_pool_create(int pool, uint64_t len) "created RX pool %d for size %"PRIu64 274spapr_vlan_add_rxbuf_to_pool(int pool, uint64_t len, int32_t count) "add buf using pool %d (size %"PRIu64", count=%"PRId32")" 275spapr_vlan_add_rxbuf_to_page(uint32_t ptr, uint32_t rx_bufs, uint64_t bd) "added buf ptr=%"PRIu32" rx_bufs=%"PRIu32" bd=0x%016"PRIx64 276spapr_vlan_h_add_logical_lan_buffer(uint64_t reg, uint64_t buf) "H_ADD_LOGICAL_LAN_BUFFER(0x%"PRIx64", 0x%"PRIx64")" 277spapr_vlan_h_send_logical_lan(uint64_t reg, uint64_t continue_token) "H_SEND_LOGICAL_LAN(0x%"PRIx64", <bufs>, 0x%"PRIx64")" 278spapr_vlan_h_send_logical_lan_rxbufs(uint32_t rx_bufs) "rxbufs = %"PRIu32 279spapr_vlan_h_send_logical_lan_buf_desc(uint64_t buf) " buf desc: 0x%"PRIx64 280spapr_vlan_h_send_logical_lan_total(int nbufs, unsigned total_len) "%d buffers, total length 0x%x" 281 282# hw/net/sungem.c 283sungem_tx_checksum(uint16_t start, uint16_t off) "TX checksumming from byte %d, inserting at %d" 284sungem_tx_checksum_oob(void) "TX checksum out of packet bounds" 285sungem_tx_unfinished(void) "TX packet started without finishing the previous one" 286sungem_tx_overflow(void) "TX packet queue overflow" 287sungem_tx_finished(uint32_t size) "TX completing %"PRIu32 " bytes packet" 288sungem_tx_kick(void) "TX Kick..." 289sungem_tx_disabled(void) "TX not enabled" 290sungem_tx_process(uint32_t comp, uint32_t kick, uint32_t size) "TX processing comp=%"PRIu32", kick=%"PRIu32" out of %"PRIu32 291sungem_tx_desc(uint32_t comp, uint64_t control, uint64_t buffer) "TX desc %"PRIu32 ": 0x%"PRIx64" 0x%"PRIx64 292sungem_tx_reset(void) "TX reset" 293sungem_rx_mac_disabled(void) "Check RX MAC disabled" 294sungem_rx_txdma_disabled(void) "Check RX TXDMA disabled" 295sungem_rx_check(bool full, uint32_t kick, uint32_t done) "Check RX %d (kick=%"PRIu32", done=%"PRIu32")" 296sungem_rx_mac_check(uint32_t mac0, uint32_t mac1, uint32_t mac2) "Word MAC: 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32 297sungem_rx_mac_multicast(void) "Multicast" 298sungem_rx_mac_compare(uint32_t mac0, uint32_t mac1, uint32_t mac2) "Compare MAC to 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32".." 299sungem_rx_packet(size_t size) "RX got %zu bytes packet" 300sungem_rx_disabled(void) "RX not enabled" 301sungem_rx_bad_frame_size(size_t size) "RX bad frame size %zu, dropped" 302sungem_rx_unmatched(void) "No match, dropped" 303sungem_rx_process(uint32_t done, uint32_t kick, uint32_t size) "RX processing done=%"PRIu32", kick=%"PRIu32" out of %"PRIu32 304sungem_rx_ringfull(void) "RX ring full" 305sungem_rx_desc(uint64_t control, uint64_t buffer) "RX desc: 0x%"PRIx64" 0x%"PRIx64 306sungem_rx_reset(void) "RX reset" 307sungem_rx_kick(uint64_t val) "RXDMA_KICK written to %"PRIu64 308sungem_reset(bool pci_reset) "Full reset (PCI:%d)" 309sungem_mii_write(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII write addr 0x%x reg 0x%02x val 0x%04x" 310sungem_mii_read(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII read addr 0x%x reg 0x%02x val 0x%04x" 311sungem_mii_invalid_sof(uint32_t val) "MII op, invalid SOF field 0x%"PRIx32 312sungem_mii_invalid_op(uint8_t op) "MII op, invalid op field 0x%x" 313sungem_mmio_greg_write(uint64_t addr, uint64_t val) "MMIO greg write to 0x%"PRIx64" val=0x%"PRIx64 314sungem_mmio_greg_read(uint64_t addr, uint64_t val) "MMIO greg read from 0x%"PRIx64" val=0x%"PRIx64 315sungem_mmio_txdma_write(uint64_t addr, uint64_t val) "MMIO txdma write to 0x%"PRIx64" val=0x%"PRIx64 316sungem_mmio_txdma_read(uint64_t addr, uint64_t val) "MMIO txdma read from 0x%"PRIx64" val=0x%"PRIx64 317sungem_mmio_rxdma_write(uint64_t addr, uint64_t val) "MMIO rxdma write to 0x%"PRIx64" val=0x%"PRIx64 318sungem_mmio_rxdma_read(uint64_t addr, uint64_t val) "MMIO rxdma read from 0x%"PRIx64" val=0x%"PRIx64 319sungem_mmio_mac_write(uint64_t addr, uint64_t val) "MMIO mac write to 0x%"PRIx64" val=0x%"PRIx64 320sungem_mmio_mac_read(uint64_t addr, uint64_t val) "MMIO mac read from 0x%"PRIx64" val=0x%"PRIx64 321sungem_mmio_mif_write(uint64_t addr, uint64_t val) "MMIO mif write to 0x%"PRIx64" val=0x%"PRIx64 322sungem_mmio_mif_read(uint64_t addr, uint64_t val) "MMIO mif read from 0x%"PRIx64" val=0x%"PRIx64 323sungem_mmio_pcs_write(uint64_t addr, uint64_t val) "MMIO pcs write to 0x%"PRIx64" val=0x%"PRIx64 324sungem_mmio_pcs_read(uint64_t addr, uint64_t val) "MMIO pcs read from 0x%"PRIx64" val=0x%"PRIx64 325 326# hw/net/sunhme.c 327sunhme_seb_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 328sunhme_seb_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 329sunhme_etx_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 330sunhme_etx_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 331sunhme_erx_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 332sunhme_erx_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 333sunhme_mac_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 334sunhme_mac_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 335sunhme_mii_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 336sunhme_mii_read(uint8_t addr, uint16_t value) "addr 0x%x value 0x%x" 337sunhme_mif_write(uint8_t addr, uint16_t value) "addr 0x%x value 0x%x" 338sunhme_mif_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 339sunhme_tx_desc(uint64_t buffer, uint32_t status, int cr, int nr) "addr 0x%"PRIx64" status 0x%"PRIx32 " (ring %d/%d)" 340sunhme_tx_xsum_add(int offset, int len) "adding xsum at offset %d, len %d" 341sunhme_tx_xsum_stuff(uint16_t xsum, int offset) "stuffing xsum 0x%x at offset %d" 342sunhme_tx_done(int len) "successfully transmitted frame with len %d" 343sunhme_rx_incoming(size_t len) "received incoming frame with len %zu" 344sunhme_rx_filter_destmac(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "received frame for MAC: %02x:%02x:%02x:%02x:%02x:%02x" 345sunhme_rx_filter_local_match(void) "incoming frame matches local MAC address" 346sunhme_rx_filter_bcast_match(void) "incoming frame matches broadcast MAC address" 347sunhme_rx_filter_hash_nomatch(void) "incoming MAC address not in hash table" 348sunhme_rx_filter_hash_match(void) "incoming MAC address found in hash table" 349sunhme_rx_filter_promisc_match(void) "incoming frame accepted due to promiscuous mode" 350sunhme_rx_filter_reject(void) "rejecting incoming frame" 351sunhme_rx_filter_accept(void) "accepting incoming frame" 352sunhme_rx_desc(uint32_t addr, int offset, uint32_t status, int len, int cr, int nr) "addr 0x%"PRIx32"(+0x%x) status 0x%"PRIx32 " len %d (ring %d/%d)" 353sunhme_rx_xsum_calc(uint16_t xsum) "calculated incoming xsum as 0x%x" 354