1# See docs/devel/tracing.rst for syntax documentation. 2 3# allwinner-sun8i-emac.c 4allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32 5allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32 6allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 7allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 8allwinner_sun8i_emac_reset(void) "HW reset" 9allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" 10allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 11allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 12 13# etraxfs_eth.c 14mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x" 15mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x" 16mdio_bitbang(bool mdc, bool mdio, int state, uint16_t cnt, unsigned int drive) "bitbang mdc=%u mdio=%u state=%d cnt=%u drv=%d" 17 18# lance.c 19lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" 20lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" 21 22# mipsnet.c 23mipsnet_send(uint32_t size) "sending len=%u" 24mipsnet_receive(uint32_t size) "receiving len=%u" 25mipsnet_read(uint64_t addr, uint32_t val) "read addr=0x%" PRIx64 " val=0x%x" 26mipsnet_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64 27mipsnet_irq(uint32_t isr, uint32_t intctl) "set irq to %d (0x%02x)" 28 29# ne2000.c 30ne2000_read(uint64_t addr, uint64_t val) "read addr=0x%" PRIx64 " val=0x%" PRIx64 31ne2000_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64 32ne2000_ioport_read(uint64_t addr, uint64_t val) "io read addr=0x%02" PRIx64 " val=0x%02" PRIx64 33ne2000_ioport_write(uint64_t addr, uint64_t val) "io write addr=0x%02" PRIx64 " val=0x%02" PRIx64 34 35# opencores_eth.c 36open_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x" 37open_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x" 38open_eth_update_irq(uint32_t v) "IRQ <- 0x%x" 39open_eth_receive(unsigned len) "RX: len: %u" 40open_eth_receive_mcast(unsigned idx, uint32_t h0, uint32_t h1) "MCAST: idx = %u, hash: %08x:%08x" 41open_eth_receive_reject(void) "RX: rejected" 42open_eth_receive_desc(uint32_t addr, uint32_t len_flags) "RX: 0x%08x, len_flags: 0x%08x" 43open_eth_start_xmit(uint32_t addr, unsigned len, unsigned tx_len) "TX: 0x%08x, len: %u, tx_len: %u" 44open_eth_reg_read(uint32_t addr, uint32_t v) "MAC[0x%02x] -> 0x%08x" 45open_eth_reg_write(uint32_t addr, uint32_t v) "MAC[0x%02x] <- 0x%08x" 46open_eth_desc_read(uint32_t addr, uint32_t v) "DESC[0x%04x] -> 0x%08x" 47open_eth_desc_write(uint32_t addr, uint32_t v) "DESC[0x%04x] <- 0x%08x" 48 49# pcnet.c 50pcnet_s_reset(void *s) "s=%p" 51pcnet_user_int(void *s) "s=%p" 52pcnet_isr_change(void *s, uint32_t isr, uint32_t isr_old) "s=%p INTA=%d<=%d" 53pcnet_init(void *s, uint64_t init_addr) "s=%p init_addr=0x%"PRIx64 54pcnet_rlen_tlen(void *s, uint32_t rlen, uint32_t tlen) "s=%p rlen=%d tlen=%d" 55pcnet_ss32_rdra_tdra(void *s, uint32_t ss32, uint32_t rdra, uint32_t rcvrl, uint32_t tdra, uint32_t xmtrl) "s=%p ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]" 56 57# pcnet-pci.c 58pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x" 59pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x" 60pcnet_ioport_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d" 61pcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned size) "opaque=%p addr=0x%"PRIx64" data=0x%"PRIx64" size=%d" 62 63# net_rx_pkt.c 64net_rx_pkt_parsed(bool ip4, bool ip6, bool udp, bool tcp, size_t l3o, size_t l4o, size_t l5o) "RX packet parsed: ip4: %d, ip6: %d, udp: %d, tcp: %d, l3 offset: %zu, l4 offset: %zu, l5 offset: %zu" 65net_rx_pkt_l4_csum_validate_entry(void) "Starting L4 checksum validation" 66net_rx_pkt_l4_csum_validate_not_xxp(void) "Not a TCP/UDP packet" 67net_rx_pkt_l4_csum_validate_udp_with_no_checksum(void) "UDP packet without checksum" 68net_rx_pkt_l4_csum_validate_ip4_fragment(void) "IP4 fragment" 69net_rx_pkt_l4_csum_validate_csum(bool csum_valid) "Checksum valid: %d" 70 71net_rx_pkt_l4_csum_calc_entry(void) "Starting L4 checksum calculation" 72net_rx_pkt_l4_csum_calc_ip4_udp(void) "IP4/UDP packet" 73net_rx_pkt_l4_csum_calc_ip4_tcp(void) "IP4/TCP packet" 74net_rx_pkt_l4_csum_calc_ip6_udp(void) "IP6/UDP packet" 75net_rx_pkt_l4_csum_calc_ip6_tcp(void) "IP6/TCP packet" 76net_rx_pkt_l4_csum_calc_ph_csum(uint32_t cntr, uint16_t csl) "Pseudo-header: checksum counter %u, length %u" 77net_rx_pkt_l4_csum_calc_csum(size_t l4hdr_off, uint16_t csl, uint32_t cntr, uint16_t csum) "L4 Checksum: L4 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X" 78 79net_rx_pkt_l4_csum_fix_entry(void) "Starting L4 checksum correction" 80net_rx_pkt_l4_csum_fix_tcp(uint32_t l4_cso) "TCP packet, L4 cso: %u" 81net_rx_pkt_l4_csum_fix_udp(uint32_t l4_cso) "UDP packet, L4 cso: %u" 82net_rx_pkt_l4_csum_fix_not_xxp(void) "Not an IP4 packet" 83net_rx_pkt_l4_csum_fix_ip4_fragment(void) "IP4 fragment" 84net_rx_pkt_l4_csum_fix_udp_with_no_checksum(void) "UDP packet without checksum" 85net_rx_pkt_l4_csum_fix_csum(uint32_t cso, uint16_t csum) "L4 Checksum: Offset: %u, value 0x%X" 86 87net_rx_pkt_l3_csum_validate_entry(void) "Starting L3 checksum validation" 88net_rx_pkt_l3_csum_validate_not_ip4(void) "Not an IP4 packet" 89net_rx_pkt_l3_csum_validate_csum(size_t l3hdr_off, uint32_t csl, uint32_t cntr, uint16_t csum, bool csum_valid) "L3 Checksum: L3 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X, valid: %d" 90 91net_rx_pkt_rss_ip4(void) "Calculating IPv4 RSS hash" 92net_rx_pkt_rss_ip4_tcp(void) "Calculating IPv4/TCP RSS hash" 93net_rx_pkt_rss_ip4_udp(void) "Calculating IPv4/UDP RSS hash" 94net_rx_pkt_rss_ip6_tcp(void) "Calculating IPv6/TCP RSS hash" 95net_rx_pkt_rss_ip6_udp(void) "Calculating IPv6/UDP RSS hash" 96net_rx_pkt_rss_ip6(void) "Calculating IPv6 RSS hash" 97net_rx_pkt_rss_ip6_ex(void) "Calculating IPv6/EX RSS hash" 98net_rx_pkt_rss_ip6_ex_tcp(void) "Calculating IPv6/EX/TCP RSS hash" 99net_rx_pkt_rss_ip6_ex_udp(void) "Calculating IPv6/EX/UDP RSS hash" 100net_rx_pkt_rss_hash(size_t rss_length, uint32_t rss_hash) "RSS hash for %zu bytes: 0x%X" 101net_rx_pkt_rss_add_chunk(void* ptr, size_t size, size_t input_offset) "Add RSS chunk %p, %zu bytes, RSS input offset %zu bytes" 102 103# e1000.c 104e1000_receiver_overrun(size_t s, uint32_t rdh, uint32_t rdt) "Receiver overrun: dropped packet of %zu bytes, RDH=%u, RDT=%u" 105 106# e1000x_common.c 107e1000x_rx_can_recv_disabled(bool link_up, bool rx_enabled, bool pci_master) "link_up: %d, rx_enabled %d, pci_master %d" 108e1000x_vlan_is_vlan_pkt(bool is_vlan_pkt, uint16_t eth_proto, uint16_t vet) "Is VLAN packet: %d, ETH proto: 0x%X, VET: 0x%X" 109e1000x_rx_flt_ucast_match(uint32_t idx, uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x" 110e1000x_rx_flt_ucast_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x" 111e1000x_rx_flt_inexact_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint32_t mo, uint32_t mta, uint32_t mta_val) "inexact mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] 0x%x" 112e1000x_rx_link_down(uint32_t status_reg) "Received packet dropped because the link is down STATUS = %u" 113e1000x_rx_disabled(uint32_t rctl_reg) "Received packet dropped because receive is disabled RCTL = %u" 114e1000x_rx_oversized(size_t size) "Received packet dropped because it was oversized (%zu bytes)" 115e1000x_mac_indicate(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Indicating MAC to guest: %02x:%02x:%02x:%02x:%02x:%02x" 116e1000x_link_negotiation_start(void) "Start link auto negotiation" 117e1000x_link_negotiation_done(void) "Auto negotiation is completed" 118 119# e1000e_core.c 120e1000e_core_write(uint64_t index, uint32_t size, uint64_t val) "Write to register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 121e1000e_core_read(uint64_t index, uint32_t size, uint64_t val) "Read from register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 122e1000e_core_mdic_read(uint8_t page, uint32_t addr, uint32_t data) "MDIC READ: PHY[%u][%u] = 0x%x" 123e1000e_core_mdic_read_unhandled(uint8_t page, uint32_t addr) "MDIC READ: PHY[%u][%u] UNHANDLED" 124e1000e_core_mdic_write(uint8_t page, uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u][%u] = 0x%x" 125e1000e_core_mdic_write_unhandled(uint8_t page, uint32_t addr) "MDIC WRITE: PHY[%u][%u] UNHANDLED" 126e1000e_core_ctrl_write(uint64_t index, uint32_t val) "Write CTRL register 0x%"PRIx64", value: 0x%X" 127e1000e_core_ctrl_sw_reset(void) "Doing SW reset" 128e1000e_core_ctrl_phy_reset(void) "Doing PHY reset" 129 130e1000e_link_autoneg_flowctl(bool enabled) "Auto-negotiated flow control state is %d" 131e1000e_link_set_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Set link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d" 132e1000e_link_read_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Get link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d" 133e1000e_link_set_ext_params(bool asd_check, bool speed_select_bypass) "Set extended link params: ASD check: %d, Speed select bypass: %d" 134e1000e_link_status(bool link_up, bool full_dplx, uint32_t speed, uint32_t asdv) "Link up: %d, Duplex: %d, Speed: %d, ASDV: %d" 135e1000e_link_status_changed(bool status) "New link status: %d" 136 137e1000e_wrn_regs_write_ro(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to RO register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 138e1000e_wrn_regs_write_unknown(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to unknown register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 139e1000e_wrn_regs_read_unknown(uint64_t index, uint32_t size) "WARNING: Read from unknown register 0x%"PRIx64", %d byte(s)" 140e1000e_wrn_regs_read_trivial(uint32_t index) "WARNING: Reading register at offset: 0x%05x. It is not fully implemented." 141e1000e_wrn_regs_write_trivial(uint32_t index) "WARNING: Writing to register at offset: 0x%05x. It is not fully implemented." 142e1000e_wrn_no_ts_support(void) "WARNING: Guest requested TX timestamping which is not supported" 143e1000e_wrn_no_snap_support(void) "WARNING: Guest requested TX SNAP header update which is not supported" 144e1000e_wrn_iscsi_filtering_not_supported(void) "WARNING: Guest requested iSCSI filtering which is not supported" 145e1000e_wrn_nfsw_filtering_not_supported(void) "WARNING: Guest requested NFS write filtering which is not supported" 146e1000e_wrn_nfsr_filtering_not_supported(void) "WARNING: Guest requested NFS read filtering which is not supported" 147 148e1000e_tx_disabled(void) "TX Disabled" 149e1000e_tx_descr(void *addr, uint32_t lower, uint32_t upper) "%p : %x %x" 150 151e1000e_ring_free_space(int ridx, uint32_t rdlen, uint32_t rdh, uint32_t rdt) "ring #%d: LEN: %u, DH: %u, DT: %u" 152 153e1000e_rx_can_recv_rings_full(void) "Cannot receive: all rings are full" 154e1000e_rx_can_recv(void) "Can receive" 155e1000e_rx_has_buffers(int ridx, uint32_t free_desc, size_t total_size, uint32_t desc_buf_size) "ring #%d: free descr: %u, packet size %zu, descr buffer size %u" 156e1000e_rx_null_descriptor(void) "Null RX descriptor!!" 157e1000e_rx_flt_vlan_mismatch(uint16_t vid) "VID mismatch: 0x%X" 158e1000e_rx_flt_vlan_match(uint16_t vid) "VID match: 0x%X" 159e1000e_rx_desc_ps_read(uint64_t a0, uint64_t a1, uint64_t a2, uint64_t a3) "buffers: [0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64"]" 160e1000e_rx_desc_ps_write(uint16_t a0, uint16_t a1, uint16_t a2, uint16_t a3) "bytes written: [%u, %u, %u, %u]" 161e1000e_rx_desc_buff_sizes(uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3) "buffer sizes: [%u, %u, %u, %u]" 162e1000e_rx_desc_len(uint8_t rx_desc_len) "RX descriptor length: %u" 163e1000e_rx_desc_buff_write(uint8_t idx, uint64_t addr, uint16_t offset, const void* source, uint32_t len) "buffer #%u, addr: 0x%"PRIx64", offset: %u, from: %p, length: %u" 164e1000e_rx_descr(int ridx, uint64_t base, uint8_t len) "Next RX descriptor: ring #%d, PA: 0x%"PRIx64", length: %u" 165e1000e_rx_set_rctl(uint32_t rctl) "RCTL = 0x%x" 166e1000e_rx_receive_iov(int iovcnt) "Received vector of %d fragments" 167e1000e_rx_flt_dropped(void) "Received packet dropped by RX filter" 168e1000e_rx_written_to_guest(uint32_t causes) "Received packet written to guest (ICR causes %u)" 169e1000e_rx_not_written_to_guest(uint32_t causes) "Received packet NOT written to guest (ICR causes %u)" 170e1000e_rx_interrupt_set(uint32_t causes) "Receive interrupt set (ICR causes %u)" 171e1000e_rx_interrupt_delayed(uint32_t causes) "Receive interrupt delayed (ICR causes %u)" 172e1000e_rx_set_cso(int cso_state) "RX CSO state set to %d" 173e1000e_rx_set_rdt(int queue_idx, uint32_t val) "Setting RDT[%d] = %u" 174e1000e_rx_set_rfctl(uint32_t val) "Setting RFCTL = 0x%X" 175e1000e_rx_start_recv(void) 176 177e1000e_rx_rss_started(void) "Starting RSS processing" 178e1000e_rx_rss_disabled(void) "RSS is disabled" 179e1000e_rx_rss_type(uint32_t type) "RSS type is %u" 180e1000e_rx_rss_ip4(bool isfragment, bool istcp, uint32_t mrqc, bool tcpipv4_enabled, bool ipv4_enabled) "RSS IPv4: fragment %d, tcp %d, mrqc 0x%X, tcpipv4 enabled %d, ipv4 enabled %d" 181e1000e_rx_rss_ip6_rfctl(uint32_t rfctl) "RSS IPv6: rfctl 0x%X" 182e1000e_rx_rss_ip6(bool ex_dis, bool new_ex_dis, bool istcp, bool has_ext_headers, bool ex_dst_valid, bool ex_src_valid, uint32_t mrqc, bool tcpipv6_enabled, bool ipv6ex_enabled, bool ipv6_enabled) "RSS IPv6: ex_dis: %d, new_ex_dis: %d, tcp %d, has_ext_headers %d, ex_dst_valid %d, ex_src_valid %d, mrqc 0x%X, tcpipv6 enabled %d, ipv6ex enabled %d, ipv6 enabled %d" 183e1000e_rx_rss_dispatched_to_queue(int queue_idx) "Packet being dispatched to queue %d" 184 185e1000e_rx_metadata_protocols(bool isip4, bool isip6, bool isudp, bool istcp) "protocols: ip4: %d, ip6: %d, udp: %d, tcp: %d" 186e1000e_rx_metadata_vlan(uint16_t vlan_tag) "VLAN tag is 0x%X" 187e1000e_rx_metadata_rss(uint32_t rss, uint32_t mrq) "RSS data: rss: 0x%X, mrq: 0x%X" 188e1000e_rx_metadata_ip_id(uint16_t ip_id) "the IPv4 ID is 0x%X" 189e1000e_rx_metadata_ack(void) "the packet is TCP ACK" 190e1000e_rx_metadata_pkt_type(uint32_t pkt_type) "the packet type is %u" 191e1000e_rx_metadata_no_virthdr(void) "the packet has no virt-header" 192e1000e_rx_metadata_virthdr_no_csum_info(void) "virt-header does not contain checksum info" 193e1000e_rx_metadata_l3_cso_disabled(void) "IP4 CSO is disabled" 194e1000e_rx_metadata_l4_cso_disabled(void) "TCP/UDP CSO is disabled" 195e1000e_rx_metadata_l3_csum_validation_failed(void) "Cannot validate L3 checksum" 196e1000e_rx_metadata_l4_csum_validation_failed(void) "Cannot validate L4 checksum" 197e1000e_rx_metadata_status_flags(uint32_t status_flags) "status_flags is 0x%X" 198e1000e_rx_metadata_ipv6_sum_disabled(void) "IPv6 RX checksummimg disabled by RFCTL" 199e1000e_rx_metadata_ipv6_filtering_disabled(void) "IPv6 RX filtering disabled by RFCTL" 200 201e1000e_vlan_vet(uint16_t vet) "Setting VLAN ethernet type 0x%X" 202 203e1000e_irq_msi_notify(uint32_t cause) "MSI notify 0x%x" 204e1000e_irq_throttling_no_pending_interrupts(void) "No pending interrupts to notify" 205e1000e_irq_msi_notify_postponed(void) "Sending MSI postponed by ITR" 206e1000e_irq_legacy_notify_postponed(void) "Raising legacy IRQ postponed by ITR" 207e1000e_irq_throttling_no_pending_vec(int idx) "No pending interrupts for vector %d" 208e1000e_irq_msix_notify_postponed_vec(int idx) "Sending MSI-X postponed by EITR[%d]" 209e1000e_irq_legacy_notify(bool level) "IRQ line state: %d" 210e1000e_irq_msix_notify_vec(uint32_t vector) "MSI-X notify vector 0x%x" 211e1000e_irq_postponed_by_xitr(uint32_t reg) "Interrupt postponed by [E]ITR register 0x%x" 212e1000e_irq_clear_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Clearing IMS bits 0x%x: 0x%x --> 0x%x" 213e1000e_irq_set_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Setting IMS bits 0x%x: 0x%x --> 0x%x" 214e1000e_irq_fix_icr_asserted(uint32_t new_val) "ICR_ASSERTED bit fixed: 0x%x" 215e1000e_irq_add_msi_other(uint32_t new_val) "ICR_OTHER bit added: 0x%x" 216e1000e_irq_pending_interrupts(uint32_t pending, uint32_t icr, uint32_t ims) "ICR PENDING: 0x%x (ICR: 0x%x, IMS: 0x%x)" 217e1000e_irq_set_cause_entry(uint32_t val, uint32_t icr) "Going to set IRQ cause 0x%x, ICR: 0x%x" 218e1000e_irq_set_cause_exit(uint32_t val, uint32_t icr) "Set IRQ cause 0x%x, ICR: 0x%x" 219e1000e_irq_icr_write(uint32_t bits, uint32_t old_icr, uint32_t new_icr) "Clearing ICR bits 0x%x: 0x%x --> 0x%x" 220e1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x" 221e1000e_irq_icr_process_iame(void) "Clearing IMS bits due to IAME" 222e1000e_irq_read_ics(uint32_t ics) "Current ICS: 0x%x" 223e1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x" 224e1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR read. Current ICR: 0x%x" 225e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0x%x" 226e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS" 227e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME" 228e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X" 229e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bits due to EIAC, ICR: 0x%X, EIAC: 0x%X" 230e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to IMC write 0x%x" 231e1000e_irq_fire_delayed_interrupts(void) "Firing delayed interrupts" 232e1000e_irq_rearm_timer(uint32_t reg, int64_t delay_ns) "Mitigation timer armed for register 0x%X, delay %"PRId64" ns" 233e1000e_irq_throttling_timer(uint32_t reg) "Mitigation timer shot for register 0x%X" 234e1000e_irq_rdtr_fpd_running(void) "FPD written while RDTR was running" 235e1000e_irq_rdtr_fpd_not_running(void) "FPD written while RDTR was not running" 236e1000e_irq_tidv_fpd_running(void) "FPD written while TIDV was running" 237e1000e_irq_tidv_fpd_not_running(void) "FPD written while TIDV was not running" 238e1000e_irq_eitr_set(uint32_t eitr_num, uint32_t val) "EITR[%u] = %u" 239e1000e_irq_itr_set(uint32_t val) "ITR = %u" 240e1000e_irq_fire_all_timers(uint32_t val) "Firing all delay/throttling timers on all interrupts enable (0x%X written to IMS)" 241e1000e_irq_adding_delayed_causes(uint32_t val, uint32_t icr) "Merging delayed causes 0x%X to ICR 0x%X" 242e1000e_irq_msix_pending_clearing(uint32_t cause, uint32_t int_cfg, uint32_t vec) "Clearing MSI-X pending bit for cause 0x%x, IVAR config 0x%x, vector %u" 243 244e1000e_wrn_msix_vec_wrong(uint32_t cause, uint32_t cfg) "Invalid configuration for cause 0x%x: 0x%x" 245e1000e_wrn_msix_invalid(uint32_t cause, uint32_t cfg) "Invalid entry for cause 0x%x: 0x%x" 246 247e1000e_mac_set_sw(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set SW MAC: %02x:%02x:%02x:%02x:%02x:%02x" 248 249e1000e_vm_state_running(void) "VM state is running" 250e1000e_vm_state_stopped(void) "VM state is stopped" 251 252# e1000e.c 253e1000e_cb_pci_realize(void) "E1000E PCI realize entry" 254e1000e_cb_pci_uninit(void) "E1000E PCI unit entry" 255e1000e_cb_qdev_reset(void) "E1000E qdev reset entry" 256e1000e_cb_pre_save(void) "E1000E pre save entry" 257e1000e_cb_post_load(void) "E1000E post load entry" 258 259e1000e_io_write_addr(uint64_t addr) "IOADDR write 0x%"PRIx64 260e1000e_io_write_data(uint64_t addr, uint64_t val) "IODATA write 0x%"PRIx64", value: 0x%"PRIx64 261e1000e_io_read_addr(uint64_t addr) "IOADDR read 0x%"PRIx64 262e1000e_io_read_data(uint64_t addr, uint64_t val) "IODATA read 0x%"PRIx64", value: 0x%"PRIx64 263e1000e_wrn_io_write_unknown(uint64_t addr) "IO write unknown address 0x%"PRIx64 264e1000e_wrn_io_read_unknown(uint64_t addr) "IO read unknown address 0x%"PRIx64 265e1000e_wrn_io_addr_undefined(uint64_t addr) "IO undefined register 0x%"PRIx64 266e1000e_wrn_io_addr_flash(uint64_t addr) "IO flash access (0x%"PRIx64") not implemented" 267e1000e_wrn_io_addr_unknown(uint64_t addr) "IO unknown register 0x%"PRIx64 268 269e1000e_msi_init_fail(int32_t res) "Failed to initialize MSI, error %d" 270e1000e_msix_init_fail(int32_t res) "Failed to initialize MSI-X, error %d" 271e1000e_msix_use_vector_fail(uint32_t vec, int32_t res) "Failed to use MSI-X vector %d, error %d" 272 273e1000e_mac_set_permanent(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set permanent MAC: %02x:%02x:%02x:%02x:%02x:%02x" 274e1000e_cfg_support_virtio(bool support) "Virtio header supported: %d" 275 276# spapr_llan.c 277spapr_vlan_get_rx_bd_from_pool_found(int pool, int32_t count, uint32_t rx_bufs) "pool=%d count=%"PRId32" rxbufs=%"PRIu32 278spapr_vlan_get_rx_bd_from_page(int buf_ptr, uint64_t bd) "use_buf_ptr=%d bd=0x%016"PRIx64 279spapr_vlan_get_rx_bd_from_page_found(uint32_t use_buf_ptr, uint32_t rx_bufs) "ptr=%"PRIu32" rxbufs=%"PRIu32 280spapr_vlan_receive(const char *id, uint32_t rx_bufs) "[%s] rx_bufs=%"PRIu32 281spapr_vlan_receive_dma_completed(void) "DMA write completed" 282spapr_vlan_receive_wrote(uint64_t ptr, uint64_t hi, uint64_t lo) "rxq entry (ptr=0x%"PRIx64"): 0x%016"PRIx64" 0x%016"PRIx64 283spapr_vlan_add_rxbuf_to_pool_create(int pool, uint64_t len) "created RX pool %d for size %"PRIu64 284spapr_vlan_add_rxbuf_to_pool(int pool, uint64_t len, int32_t count) "add buf using pool %d (size %"PRIu64", count=%"PRId32")" 285spapr_vlan_add_rxbuf_to_page(uint32_t ptr, uint32_t rx_bufs, uint64_t bd) "added buf ptr=%"PRIu32" rx_bufs=%"PRIu32" bd=0x%016"PRIx64 286spapr_vlan_h_add_logical_lan_buffer(uint64_t reg, uint64_t buf) "H_ADD_LOGICAL_LAN_BUFFER(0x%"PRIx64", 0x%"PRIx64")" 287spapr_vlan_h_send_logical_lan(uint64_t reg, uint64_t continue_token) "H_SEND_LOGICAL_LAN(0x%"PRIx64", <bufs>, 0x%"PRIx64")" 288spapr_vlan_h_send_logical_lan_rxbufs(uint32_t rx_bufs) "rxbufs = %"PRIu32 289spapr_vlan_h_send_logical_lan_buf_desc(uint64_t buf) " buf desc: 0x%"PRIx64 290spapr_vlan_h_send_logical_lan_total(int nbufs, unsigned total_len) "%d buffers, total length 0x%x" 291 292# sungem.c 293sungem_tx_checksum(uint16_t start, uint16_t off) "TX checksumming from byte %d, inserting at %d" 294sungem_tx_checksum_oob(void) "TX checksum out of packet bounds" 295sungem_tx_unfinished(void) "TX packet started without finishing the previous one" 296sungem_tx_overflow(void) "TX packet queue overflow" 297sungem_tx_finished(uint32_t size) "TX completing %"PRIu32 " bytes packet" 298sungem_tx_kick(void) "TX Kick..." 299sungem_tx_disabled(void) "TX not enabled" 300sungem_tx_process(uint32_t comp, uint32_t kick, uint32_t size) "TX processing comp=%"PRIu32", kick=%"PRIu32" out of %"PRIu32 301sungem_tx_desc(uint32_t comp, uint64_t control, uint64_t buffer) "TX desc %"PRIu32 ": 0x%"PRIx64" 0x%"PRIx64 302sungem_tx_reset(void) "TX reset" 303sungem_rx_mac_disabled(void) "Check RX MAC disabled" 304sungem_rx_txdma_disabled(void) "Check RX TXDMA disabled" 305sungem_rx_check(bool full, uint32_t kick, uint32_t done) "Check RX %d (kick=%"PRIu32", done=%"PRIu32")" 306sungem_rx_mac_check(uint32_t mac0, uint32_t mac1, uint32_t mac2) "Word MAC: 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32 307sungem_rx_mac_multicast(void) "Multicast" 308sungem_rx_mac_compare(uint32_t mac0, uint32_t mac1, uint32_t mac2) "Compare MAC to 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32".." 309sungem_rx_packet(size_t size) "RX got %zu bytes packet" 310sungem_rx_disabled(void) "RX not enabled" 311sungem_rx_bad_frame_size(size_t size) "RX bad frame size %zu, dropped" 312sungem_rx_unmatched(void) "No match, dropped" 313sungem_rx_process(uint32_t done, uint32_t kick, uint32_t size) "RX processing done=%"PRIu32", kick=%"PRIu32" out of %"PRIu32 314sungem_rx_ringfull(void) "RX ring full" 315sungem_rx_desc(uint64_t control, uint64_t buffer) "RX desc: 0x%"PRIx64" 0x%"PRIx64 316sungem_rx_reset(void) "RX reset" 317sungem_rx_kick(uint64_t val) "RXDMA_KICK written to %"PRIu64 318sungem_reset(bool pci_reset) "Full reset (PCI:%d)" 319sungem_mii_write(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII write addr 0x%x reg 0x%02x val 0x%04x" 320sungem_mii_read(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII read addr 0x%x reg 0x%02x val 0x%04x" 321sungem_mii_invalid_sof(uint32_t val) "MII op, invalid SOF field 0x%"PRIx32 322sungem_mii_invalid_op(uint8_t op) "MII op, invalid op field 0x%x" 323sungem_mmio_greg_write(uint64_t addr, uint64_t val) "MMIO greg write to 0x%"PRIx64" val=0x%"PRIx64 324sungem_mmio_greg_read(uint64_t addr, uint64_t val) "MMIO greg read from 0x%"PRIx64" val=0x%"PRIx64 325sungem_mmio_txdma_write(uint64_t addr, uint64_t val) "MMIO txdma write to 0x%"PRIx64" val=0x%"PRIx64 326sungem_mmio_txdma_read(uint64_t addr, uint64_t val) "MMIO txdma read from 0x%"PRIx64" val=0x%"PRIx64 327sungem_mmio_rxdma_write(uint64_t addr, uint64_t val) "MMIO rxdma write to 0x%"PRIx64" val=0x%"PRIx64 328sungem_mmio_rxdma_read(uint64_t addr, uint64_t val) "MMIO rxdma read from 0x%"PRIx64" val=0x%"PRIx64 329sungem_mmio_mac_write(uint64_t addr, uint64_t val) "MMIO mac write to 0x%"PRIx64" val=0x%"PRIx64 330sungem_mmio_mac_read(uint64_t addr, uint64_t val) "MMIO mac read from 0x%"PRIx64" val=0x%"PRIx64 331sungem_mmio_mif_write(uint64_t addr, uint64_t val) "MMIO mif write to 0x%"PRIx64" val=0x%"PRIx64 332sungem_mmio_mif_read(uint64_t addr, uint64_t val) "MMIO mif read from 0x%"PRIx64" val=0x%"PRIx64 333sungem_mmio_pcs_write(uint64_t addr, uint64_t val) "MMIO pcs write to 0x%"PRIx64" val=0x%"PRIx64 334sungem_mmio_pcs_read(uint64_t addr, uint64_t val) "MMIO pcs read from 0x%"PRIx64" val=0x%"PRIx64 335 336# sunhme.c 337sunhme_seb_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 338sunhme_seb_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 339sunhme_etx_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 340sunhme_etx_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 341sunhme_erx_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 342sunhme_erx_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 343sunhme_mac_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 344sunhme_mac_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 345sunhme_mii_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 346sunhme_mii_read(uint8_t addr, uint16_t value) "addr 0x%x value 0x%x" 347sunhme_mif_write(uint8_t addr, uint16_t value) "addr 0x%x value 0x%x" 348sunhme_mif_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 349sunhme_tx_desc(uint64_t buffer, uint32_t status, int cr, int nr) "addr 0x%"PRIx64" status 0x%"PRIx32 " (ring %d/%d)" 350sunhme_tx_xsum_add(int offset, int len) "adding xsum at offset %d, len %d" 351sunhme_tx_xsum_stuff(uint16_t xsum, int offset) "stuffing xsum 0x%x at offset %d" 352sunhme_tx_done(int len) "successfully transmitted frame with len %d" 353sunhme_rx_incoming(size_t len) "received incoming frame with len %zu" 354sunhme_rx_filter_destmac(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "received frame for MAC: %02x:%02x:%02x:%02x:%02x:%02x" 355sunhme_rx_filter_local_match(void) "incoming frame matches local MAC address" 356sunhme_rx_filter_bcast_match(void) "incoming frame matches broadcast MAC address" 357sunhme_rx_filter_hash_nomatch(void) "incoming MAC address not in hash table" 358sunhme_rx_filter_hash_match(void) "incoming MAC address found in hash table" 359sunhme_rx_filter_promisc_match(void) "incoming frame accepted due to promiscuous mode" 360sunhme_rx_filter_reject(void) "rejecting incoming frame" 361sunhme_rx_filter_accept(void) "accepting incoming frame" 362sunhme_rx_desc(uint32_t addr, int offset, uint32_t status, int len, int cr, int nr) "addr 0x%"PRIx32"(+0x%x) status 0x%"PRIx32 " len %d (ring %d/%d)" 363sunhme_rx_xsum_calc(uint16_t xsum) "calculated incoming xsum as 0x%x" 364sunhme_rx_norxd(void) "no free rx descriptors available" 365sunhme_update_irq(uint32_t mifmask, uint32_t mif, uint32_t sebmask, uint32_t seb, int level) "mifmask: 0x%x mif: 0x%x sebmask: 0x%x seb: 0x%x level: %d" 366 367# virtio-net.c 368virtio_net_announce_notify(void) "" 369virtio_net_announce_timer(int round) "%d" 370virtio_net_handle_announce(int round) "%d" 371virtio_net_post_load_device(void) 372virtio_net_rss_disable(void) 373virtio_net_rss_error(const char *msg, uint32_t value) "%s, value 0x%08x" 374virtio_net_rss_enable(uint32_t p1, uint16_t p2, uint8_t p3) "hashes 0x%x, table of %d, key of %d" 375 376# tulip.c 377tulip_reg_write(uint64_t addr, const char *name, int size, uint64_t val) "addr 0x%02"PRIx64" (%s) size %d value 0x%08"PRIx64 378tulip_reg_read(uint64_t addr, const char *name, int size, uint64_t val) "addr 0x%02"PRIx64" (%s) size %d value 0x%08"PRIx64 379tulip_receive(const uint8_t *buf, size_t len) "buf %p size %zu" 380tulip_descriptor(const char *prefix, uint32_t addr, uint32_t status, uint32_t control, uint32_t len1, uint32_t len2, uint32_t buf1, uint32_t buf2) "%s 0x%08x: status 0x%08x control 0x%03x len1 %4d len2 %4d buf1 0x%08x buf2 0x%08x" 381tulip_rx_state(const char *state) "RX %s" 382tulip_tx_state(const char *state) "TX %s" 383tulip_irq(uint32_t mask, uint32_t en, const char *state) "mask 0x%08x ie 0x%08x %s" 384tulip_mii_write(int phy, int reg, uint16_t data) "phy 0x%x reg 0x%x data 0x%04x" 385tulip_mii_read(int phy, int reg, uint16_t data) "phy 0x%x, reg 0x%x data 0x%04x" 386tulip_reset(void) "" 387tulip_setup_frame(void) "" 388tulip_setup_filter(int n, uint8_t a, uint8_t b, uint8_t c, uint8_t d, uint8_t e, uint8_t f) "%d: %02x:%02x:%02x:%02x:%02x:%02x" 389 390# lasi_i82596.c 391lasi_82596_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64" val=0x%04x" 392lasi_82596_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64" val=0x%04x" 393 394# i82596.c 395i82596_s_reset(void *s) "%p Reset chip" 396i82596_transmit(uint32_t size, uint32_t addr) "size %u from addr 0x%04x" 397i82596_receive_analysis(const char *s) "%s" 398i82596_receive_packet(size_t sz) "len=%zu" 399i82596_new_mac(const char *id_with_mac) "New MAC for: %s" 400i82596_set_multicast(uint16_t count) "Added %d multicast entries" 401i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" 402 403# imx_fec.c 404imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" 405imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" 406imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" 407imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" 408imx_phy_update_link(const char *s) "%s" 409imx_phy_reset(void) "" 410imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" 411imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" 412imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" 413imx_eth_rx_bd_full(void) "RX buffer is full" 414imx_eth_read(int reg, const char *reg_name, uint32_t value) "reg[%d:%s] => 0x%08"PRIx32 415imx_eth_write(int reg, const char *reg_name, uint64_t value) "reg[%d:%s] <= 0x%08"PRIx64 416imx_fec_receive(size_t size) "len %zu" 417imx_fec_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" 418imx_fec_receive_last(int last) "rx frame flags 0x%04x" 419imx_enet_receive(size_t size) "len %zu" 420imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" 421imx_enet_receive_last(int last) "rx frame flags 0x%04x" 422 423# npcm7xx_emc.c 424npcm7xx_emc_reset(int emc_num) "Resetting emc%d" 425npcm7xx_emc_update_tx_irq(int level) "Setting tx irq to %d" 426npcm7xx_emc_update_rx_irq(int level) "Setting rx irq to %d" 427npcm7xx_emc_set_mista(uint32_t flags) "ORing 0x%x into MISTA" 428npcm7xx_emc_cpu_owned_desc(uint32_t addr) "Can't process cpu-owned descriptor @0x%x" 429npcm7xx_emc_sent_packet(uint32_t len) "Sent %u byte packet" 430npcm7xx_emc_tx_done(uint32_t ctxdsa) "TX done, CTXDSA=0x%x" 431npcm7xx_emc_can_receive(int can_receive) "Can receive: %d" 432npcm7xx_emc_packet_filtered_out(const char* fail_reason) "Packet filtered out: %s" 433npcm7xx_emc_packet_dropped(uint32_t len) "%u byte packet dropped" 434npcm7xx_emc_receiving_packet(uint32_t len) "Receiving %u byte packet" 435npcm7xx_emc_received_packet(uint32_t len) "Received %u byte packet" 436npcm7xx_emc_rx_done(uint32_t crxdsa) "RX done, CRXDSA=0x%x" 437npcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int regno) "emc%d: 0x%x = reg[%s/%d]" 438npcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t value) "emc%d: reg[%s/%d] = 0x%x" 439 440# dp8398x.c 441dp8393x_raise_irq(int isr) "raise irq, isr is 0x%04x" 442dp8393x_lower_irq(void) "lower irq" 443dp8393x_load_cam(int idx, int cam0, int cam1, int cam2, int cam3, int cam4, int cam5) "load cam[%d] with 0x%02x0x%02x0x%02x0x%02x0x%02x0x%02x" 444dp8393x_load_cam_done(int cen) "load cam done. cam enable mask 0x%04x" 445dp8393x_read_rra_regs(int crba0, int crba1, int rbwc0, int rbwc1) "CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x" 446dp8393x_transmit_packet(int ttda) "Transmit packet at 0x%"PRIx32 447dp8393x_transmit_txlen_error(int len) "tx_len is %d" 448dp8393x_read(int reg, const char *name, int val, int size) "reg=0x%x [%s] val=0x%04x size=%d" 449dp8393x_write(int reg, const char *name, int val, int size) "reg=0x%x [%s] val=0x%04x size=%d" 450dp8393x_write_invalid(int reg) "writing to reg %d invalid" 451dp8393x_write_invalid_dcr(const char *name) "writing to %s invalid" 452dp8393x_receive_oversize(int size) "oversize packet, pkt_size is %d" 453dp8393x_receive_not_netcard(void) "packet not for netcard" 454dp8393x_receive_packet(int crba) "Receive packet at 0x%"PRIx32 455dp8393x_receive_write_status(int crba) "Write status at 0x%"PRIx32 456