1 /* 2 * QEMU Sun Happy Meal Ethernet emulation 3 * 4 * Copyright (c) 2017 Mark Cave-Ayland 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/pci/pci.h" 28 #include "hw/net/mii.h" 29 #include "net/net.h" 30 #include "net/checksum.h" 31 #include "net/eth.h" 32 #include "sysemu/sysemu.h" 33 #include "trace.h" 34 35 #define HME_REG_SIZE 0x8000 36 37 #define HME_SEB_REG_SIZE 0x2000 38 39 #define HME_SEBI_RESET 0x0 40 #define HME_SEB_RESET_ETX 0x1 41 #define HME_SEB_RESET_ERX 0x2 42 43 #define HME_SEBI_STAT 0x100 44 #define HME_SEBI_STAT_LINUXBUG 0x108 45 #define HME_SEB_STAT_RXTOHOST 0x10000 46 #define HME_SEB_STAT_MIFIRQ 0x800000 47 #define HME_SEB_STAT_HOSTTOTX 0x1000000 48 #define HME_SEB_STAT_TXALL 0x2000000 49 50 #define HME_SEBI_IMASK 0x104 51 #define HME_SEBI_IMASK_LINUXBUG 0x10c 52 53 #define HME_ETX_REG_SIZE 0x2000 54 55 #define HME_ETXI_PENDING 0x0 56 57 #define HME_ETXI_RING 0x8 58 #define HME_ETXI_RING_ADDR 0xffffff00 59 #define HME_ETXI_RING_OFFSET 0xff 60 61 #define HME_ETXI_RSIZE 0x2c 62 63 #define HME_ERX_REG_SIZE 0x2000 64 65 #define HME_ERXI_CFG 0x0 66 #define HME_ERX_CFG_RINGSIZE 0x600 67 #define HME_ERX_CFG_RINGSIZE_SHIFT 9 68 #define HME_ERX_CFG_BYTEOFFSET 0x38 69 #define HME_ERX_CFG_BYTEOFFSET_SHIFT 3 70 #define HME_ERX_CFG_CSUMSTART 0x7f0000 71 #define HME_ERX_CFG_CSUMSHIFT 16 72 73 #define HME_ERXI_RING 0x4 74 #define HME_ERXI_RING_ADDR 0xffffff00 75 #define HME_ERXI_RING_OFFSET 0xff 76 77 #define HME_MAC_REG_SIZE 0x1000 78 79 #define HME_MACI_TXCFG 0x20c 80 #define HME_MAC_TXCFG_ENABLE 0x1 81 82 #define HME_MACI_RXCFG 0x30c 83 #define HME_MAC_RXCFG_ENABLE 0x1 84 #define HME_MAC_RXCFG_PMISC 0x40 85 #define HME_MAC_RXCFG_HENABLE 0x800 86 87 #define HME_MACI_MACADDR2 0x318 88 #define HME_MACI_MACADDR1 0x31c 89 #define HME_MACI_MACADDR0 0x320 90 91 #define HME_MACI_HASHTAB3 0x340 92 #define HME_MACI_HASHTAB2 0x344 93 #define HME_MACI_HASHTAB1 0x348 94 #define HME_MACI_HASHTAB0 0x34c 95 96 #define HME_MIF_REG_SIZE 0x20 97 98 #define HME_MIFI_FO 0xc 99 #define HME_MIF_FO_ST 0xc0000000 100 #define HME_MIF_FO_ST_SHIFT 30 101 #define HME_MIF_FO_OPC 0x30000000 102 #define HME_MIF_FO_OPC_SHIFT 28 103 #define HME_MIF_FO_PHYAD 0x0f800000 104 #define HME_MIF_FO_PHYAD_SHIFT 23 105 #define HME_MIF_FO_REGAD 0x007c0000 106 #define HME_MIF_FO_REGAD_SHIFT 18 107 #define HME_MIF_FO_TAMSB 0x20000 108 #define HME_MIF_FO_TALSB 0x10000 109 #define HME_MIF_FO_DATA 0xffff 110 111 #define HME_MIFI_CFG 0x10 112 #define HME_MIF_CFG_MDI0 0x100 113 #define HME_MIF_CFG_MDI1 0x200 114 115 #define HME_MIFI_IMASK 0x14 116 117 #define HME_MIFI_STAT 0x18 118 119 120 /* Wired HME PHY addresses */ 121 #define HME_PHYAD_INTERNAL 1 122 #define HME_PHYAD_EXTERNAL 0 123 124 #define MII_COMMAND_START 0x1 125 #define MII_COMMAND_READ 0x2 126 #define MII_COMMAND_WRITE 0x1 127 128 #define TYPE_SUNHME "sunhme" 129 #define SUNHME(obj) OBJECT_CHECK(SunHMEState, (obj), TYPE_SUNHME) 130 131 /* Maximum size of buffer */ 132 #define HME_FIFO_SIZE 0x800 133 134 /* Size of TX/RX descriptor */ 135 #define HME_DESC_SIZE 0x8 136 137 #define HME_XD_OWN 0x80000000 138 #define HME_XD_OFL 0x40000000 139 #define HME_XD_SOP 0x40000000 140 #define HME_XD_EOP 0x20000000 141 #define HME_XD_RXLENMSK 0x3fff0000 142 #define HME_XD_RXLENSHIFT 16 143 #define HME_XD_RXCKSUM 0xffff 144 #define HME_XD_TXLENMSK 0x00001fff 145 #define HME_XD_TXCKSUM 0x10000000 146 #define HME_XD_TXCSSTUFF 0xff00000 147 #define HME_XD_TXCSSTUFFSHIFT 20 148 #define HME_XD_TXCSSTART 0xfc000 149 #define HME_XD_TXCSSTARTSHIFT 14 150 151 #define HME_MII_REGS_SIZE 0x20 152 153 typedef struct SunHMEState { 154 /*< private >*/ 155 PCIDevice parent_obj; 156 157 NICState *nic; 158 NICConf conf; 159 160 MemoryRegion hme; 161 MemoryRegion sebreg; 162 MemoryRegion etxreg; 163 MemoryRegion erxreg; 164 MemoryRegion macreg; 165 MemoryRegion mifreg; 166 167 uint32_t sebregs[HME_SEB_REG_SIZE >> 2]; 168 uint32_t etxregs[HME_ETX_REG_SIZE >> 2]; 169 uint32_t erxregs[HME_ERX_REG_SIZE >> 2]; 170 uint32_t macregs[HME_MAC_REG_SIZE >> 2]; 171 uint32_t mifregs[HME_MIF_REG_SIZE >> 2]; 172 173 uint16_t miiregs[HME_MII_REGS_SIZE]; 174 } SunHMEState; 175 176 static Property sunhme_properties[] = { 177 DEFINE_NIC_PROPERTIES(SunHMEState, conf), 178 DEFINE_PROP_END_OF_LIST(), 179 }; 180 181 static void sunhme_reset_tx(SunHMEState *s) 182 { 183 /* Indicate TX reset complete */ 184 s->sebregs[HME_SEBI_RESET] &= ~HME_SEB_RESET_ETX; 185 } 186 187 static void sunhme_reset_rx(SunHMEState *s) 188 { 189 /* Indicate RX reset complete */ 190 s->sebregs[HME_SEBI_RESET] &= ~HME_SEB_RESET_ERX; 191 } 192 193 static void sunhme_update_irq(SunHMEState *s) 194 { 195 PCIDevice *d = PCI_DEVICE(s); 196 int level; 197 198 /* MIF interrupt mask (16-bit) */ 199 uint32_t mifmask = ~(s->mifregs[HME_MIFI_IMASK >> 2]) & 0xffff; 200 uint32_t mif = s->mifregs[HME_MIFI_STAT >> 2] & mifmask; 201 202 /* Main SEB interrupt mask (include MIF status from above) */ 203 uint32_t sebmask = ~(s->sebregs[HME_SEBI_IMASK >> 2]) & 204 ~HME_SEB_STAT_MIFIRQ; 205 uint32_t seb = s->sebregs[HME_SEBI_STAT >> 2] & sebmask; 206 if (mif) { 207 seb |= HME_SEB_STAT_MIFIRQ; 208 } 209 210 level = (seb ? 1 : 0); 211 pci_set_irq(d, level); 212 } 213 214 static void sunhme_seb_write(void *opaque, hwaddr addr, 215 uint64_t val, unsigned size) 216 { 217 SunHMEState *s = SUNHME(opaque); 218 219 trace_sunhme_seb_write(addr, val); 220 221 /* Handly buggy Linux drivers before 4.13 which have 222 the wrong offsets for HME_SEBI_STAT and HME_SEBI_IMASK */ 223 switch (addr) { 224 case HME_SEBI_STAT_LINUXBUG: 225 addr = HME_SEBI_STAT; 226 break; 227 case HME_SEBI_IMASK_LINUXBUG: 228 addr = HME_SEBI_IMASK; 229 break; 230 default: 231 break; 232 } 233 234 switch (addr) { 235 case HME_SEBI_RESET: 236 if (val & HME_SEB_RESET_ETX) { 237 sunhme_reset_tx(s); 238 } 239 if (val & HME_SEB_RESET_ERX) { 240 sunhme_reset_rx(s); 241 } 242 val = s->sebregs[HME_SEBI_RESET >> 2]; 243 break; 244 } 245 246 s->sebregs[addr >> 2] = val; 247 } 248 249 static uint64_t sunhme_seb_read(void *opaque, hwaddr addr, 250 unsigned size) 251 { 252 SunHMEState *s = SUNHME(opaque); 253 uint64_t val; 254 255 /* Handly buggy Linux drivers before 4.13 which have 256 the wrong offsets for HME_SEBI_STAT and HME_SEBI_IMASK */ 257 switch (addr) { 258 case HME_SEBI_STAT_LINUXBUG: 259 addr = HME_SEBI_STAT; 260 break; 261 case HME_SEBI_IMASK_LINUXBUG: 262 addr = HME_SEBI_IMASK; 263 break; 264 default: 265 break; 266 } 267 268 val = s->sebregs[addr >> 2]; 269 270 switch (addr) { 271 case HME_SEBI_STAT: 272 /* Autoclear status (except MIF) */ 273 s->sebregs[HME_SEBI_STAT >> 2] &= HME_SEB_STAT_MIFIRQ; 274 sunhme_update_irq(s); 275 break; 276 } 277 278 trace_sunhme_seb_read(addr, val); 279 280 return val; 281 } 282 283 static const MemoryRegionOps sunhme_seb_ops = { 284 .read = sunhme_seb_read, 285 .write = sunhme_seb_write, 286 .endianness = DEVICE_LITTLE_ENDIAN, 287 .valid = { 288 .min_access_size = 4, 289 .max_access_size = 4, 290 }, 291 }; 292 293 static void sunhme_transmit(SunHMEState *s); 294 295 static void sunhme_etx_write(void *opaque, hwaddr addr, 296 uint64_t val, unsigned size) 297 { 298 SunHMEState *s = SUNHME(opaque); 299 300 trace_sunhme_etx_write(addr, val); 301 302 switch (addr) { 303 case HME_ETXI_PENDING: 304 if (val) { 305 sunhme_transmit(s); 306 } 307 break; 308 } 309 310 s->etxregs[addr >> 2] = val; 311 } 312 313 static uint64_t sunhme_etx_read(void *opaque, hwaddr addr, 314 unsigned size) 315 { 316 SunHMEState *s = SUNHME(opaque); 317 uint64_t val; 318 319 val = s->etxregs[addr >> 2]; 320 321 trace_sunhme_etx_read(addr, val); 322 323 return val; 324 } 325 326 static const MemoryRegionOps sunhme_etx_ops = { 327 .read = sunhme_etx_read, 328 .write = sunhme_etx_write, 329 .endianness = DEVICE_LITTLE_ENDIAN, 330 .valid = { 331 .min_access_size = 4, 332 .max_access_size = 4, 333 }, 334 }; 335 336 static void sunhme_erx_write(void *opaque, hwaddr addr, 337 uint64_t val, unsigned size) 338 { 339 SunHMEState *s = SUNHME(opaque); 340 341 trace_sunhme_erx_write(addr, val); 342 343 s->erxregs[addr >> 2] = val; 344 } 345 346 static uint64_t sunhme_erx_read(void *opaque, hwaddr addr, 347 unsigned size) 348 { 349 SunHMEState *s = SUNHME(opaque); 350 uint64_t val; 351 352 val = s->erxregs[addr >> 2]; 353 354 trace_sunhme_erx_read(addr, val); 355 356 return val; 357 } 358 359 static const MemoryRegionOps sunhme_erx_ops = { 360 .read = sunhme_erx_read, 361 .write = sunhme_erx_write, 362 .endianness = DEVICE_LITTLE_ENDIAN, 363 .valid = { 364 .min_access_size = 4, 365 .max_access_size = 4, 366 }, 367 }; 368 369 static void sunhme_mac_write(void *opaque, hwaddr addr, 370 uint64_t val, unsigned size) 371 { 372 SunHMEState *s = SUNHME(opaque); 373 374 trace_sunhme_mac_write(addr, val); 375 376 s->macregs[addr >> 2] = val; 377 } 378 379 static uint64_t sunhme_mac_read(void *opaque, hwaddr addr, 380 unsigned size) 381 { 382 SunHMEState *s = SUNHME(opaque); 383 uint64_t val; 384 385 val = s->macregs[addr >> 2]; 386 387 trace_sunhme_mac_read(addr, val); 388 389 return val; 390 } 391 392 static const MemoryRegionOps sunhme_mac_ops = { 393 .read = sunhme_mac_read, 394 .write = sunhme_mac_write, 395 .endianness = DEVICE_LITTLE_ENDIAN, 396 .valid = { 397 .min_access_size = 4, 398 .max_access_size = 4, 399 }, 400 }; 401 402 static void sunhme_mii_write(SunHMEState *s, uint8_t reg, uint16_t data) 403 { 404 trace_sunhme_mii_write(reg, data); 405 406 switch (reg) { 407 case MII_BMCR: 408 if (data & MII_BMCR_RESET) { 409 /* Autoclear reset bit, enable auto negotiation */ 410 data &= ~MII_BMCR_RESET; 411 data |= MII_BMCR_AUTOEN; 412 } 413 if (data & MII_BMCR_ANRESTART) { 414 /* Autoclear auto negotiation restart */ 415 data &= ~MII_BMCR_ANRESTART; 416 417 /* Indicate negotiation complete */ 418 s->miiregs[MII_BMSR] |= MII_BMSR_AN_COMP; 419 420 if (!qemu_get_queue(s->nic)->link_down) { 421 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD; 422 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; 423 } 424 } 425 break; 426 } 427 428 s->miiregs[reg] = data; 429 } 430 431 static uint16_t sunhme_mii_read(SunHMEState *s, uint8_t reg) 432 { 433 uint16_t data = s->miiregs[reg]; 434 435 trace_sunhme_mii_read(reg, data); 436 437 return data; 438 } 439 440 static void sunhme_mif_write(void *opaque, hwaddr addr, 441 uint64_t val, unsigned size) 442 { 443 SunHMEState *s = SUNHME(opaque); 444 uint8_t cmd, reg; 445 uint16_t data; 446 447 trace_sunhme_mif_write(addr, val); 448 449 switch (addr) { 450 case HME_MIFI_CFG: 451 /* Mask the read-only bits */ 452 val &= ~(HME_MIF_CFG_MDI0 | HME_MIF_CFG_MDI1); 453 val |= s->mifregs[HME_MIFI_CFG >> 2] & 454 (HME_MIF_CFG_MDI0 | HME_MIF_CFG_MDI1); 455 break; 456 case HME_MIFI_FO: 457 /* Detect start of MII command */ 458 if ((val & HME_MIF_FO_ST) >> HME_MIF_FO_ST_SHIFT 459 != MII_COMMAND_START) { 460 val |= HME_MIF_FO_TALSB; 461 break; 462 } 463 464 /* Internal phy only */ 465 if ((val & HME_MIF_FO_PHYAD) >> HME_MIF_FO_PHYAD_SHIFT 466 != HME_PHYAD_INTERNAL) { 467 val |= HME_MIF_FO_TALSB; 468 break; 469 } 470 471 cmd = (val & HME_MIF_FO_OPC) >> HME_MIF_FO_OPC_SHIFT; 472 reg = (val & HME_MIF_FO_REGAD) >> HME_MIF_FO_REGAD_SHIFT; 473 data = (val & HME_MIF_FO_DATA); 474 475 switch (cmd) { 476 case MII_COMMAND_WRITE: 477 sunhme_mii_write(s, reg, data); 478 break; 479 480 case MII_COMMAND_READ: 481 val &= ~HME_MIF_FO_DATA; 482 val |= sunhme_mii_read(s, reg); 483 break; 484 } 485 486 val |= HME_MIF_FO_TALSB; 487 break; 488 } 489 490 s->mifregs[addr >> 2] = val; 491 } 492 493 static uint64_t sunhme_mif_read(void *opaque, hwaddr addr, 494 unsigned size) 495 { 496 SunHMEState *s = SUNHME(opaque); 497 uint64_t val; 498 499 val = s->mifregs[addr >> 2]; 500 501 switch (addr) { 502 case HME_MIFI_STAT: 503 /* Autoclear MIF interrupt status */ 504 s->mifregs[HME_MIFI_STAT >> 2] = 0; 505 sunhme_update_irq(s); 506 break; 507 } 508 509 trace_sunhme_mif_read(addr, val); 510 511 return val; 512 } 513 514 static const MemoryRegionOps sunhme_mif_ops = { 515 .read = sunhme_mif_read, 516 .write = sunhme_mif_write, 517 .endianness = DEVICE_LITTLE_ENDIAN, 518 .valid = { 519 .min_access_size = 4, 520 .max_access_size = 4, 521 }, 522 }; 523 524 static void sunhme_transmit_frame(SunHMEState *s, uint8_t *buf, int size) 525 { 526 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 527 } 528 529 static inline int sunhme_get_tx_ring_count(SunHMEState *s) 530 { 531 return (s->etxregs[HME_ETXI_RSIZE >> 2] + 1) << 4; 532 } 533 534 static inline int sunhme_get_tx_ring_nr(SunHMEState *s) 535 { 536 return s->etxregs[HME_ETXI_RING >> 2] & HME_ETXI_RING_OFFSET; 537 } 538 539 static inline void sunhme_set_tx_ring_nr(SunHMEState *s, int i) 540 { 541 uint32_t ring = s->etxregs[HME_ETXI_RING >> 2] & ~HME_ETXI_RING_OFFSET; 542 ring |= i & HME_ETXI_RING_OFFSET; 543 544 s->etxregs[HME_ETXI_RING >> 2] = ring; 545 } 546 547 static void sunhme_transmit(SunHMEState *s) 548 { 549 PCIDevice *d = PCI_DEVICE(s); 550 dma_addr_t tb, addr; 551 uint32_t intstatus, status, buffer, sum = 0; 552 int cr, nr, len, xmit_pos, csum_offset = 0, csum_stuff_offset = 0; 553 uint16_t csum = 0; 554 uint8_t xmit_buffer[HME_FIFO_SIZE]; 555 556 tb = s->etxregs[HME_ETXI_RING >> 2] & HME_ETXI_RING_ADDR; 557 nr = sunhme_get_tx_ring_count(s); 558 cr = sunhme_get_tx_ring_nr(s); 559 560 pci_dma_read(d, tb + cr * HME_DESC_SIZE, &status, 4); 561 pci_dma_read(d, tb + cr * HME_DESC_SIZE + 4, &buffer, 4); 562 563 xmit_pos = 0; 564 while (status & HME_XD_OWN) { 565 trace_sunhme_tx_desc(buffer, status, cr, nr); 566 567 /* Copy data into transmit buffer */ 568 addr = buffer; 569 len = status & HME_XD_TXLENMSK; 570 571 if (xmit_pos + len > HME_FIFO_SIZE) { 572 len = HME_FIFO_SIZE - xmit_pos; 573 } 574 575 pci_dma_read(d, addr, &xmit_buffer[xmit_pos], len); 576 xmit_pos += len; 577 578 /* Detect start of packet for TX checksum */ 579 if (status & HME_XD_SOP) { 580 sum = 0; 581 csum_offset = (status & HME_XD_TXCSSTART) >> HME_XD_TXCSSTARTSHIFT; 582 csum_stuff_offset = (status & HME_XD_TXCSSTUFF) >> 583 HME_XD_TXCSSTUFFSHIFT; 584 } 585 586 if (status & HME_XD_TXCKSUM) { 587 /* Only start calculation from csum_offset */ 588 if (xmit_pos - len <= csum_offset && xmit_pos > csum_offset) { 589 sum += net_checksum_add(xmit_pos - csum_offset, 590 xmit_buffer + csum_offset); 591 trace_sunhme_tx_xsum_add(csum_offset, xmit_pos - csum_offset); 592 } else { 593 sum += net_checksum_add(len, xmit_buffer + xmit_pos - len); 594 trace_sunhme_tx_xsum_add(xmit_pos - len, len); 595 } 596 } 597 598 /* Detect end of packet for TX checksum */ 599 if (status & HME_XD_EOP) { 600 /* Stuff the checksum if required */ 601 if (status & HME_XD_TXCKSUM) { 602 csum = net_checksum_finish(sum); 603 stw_be_p(xmit_buffer + csum_stuff_offset, csum); 604 trace_sunhme_tx_xsum_stuff(csum, csum_stuff_offset); 605 } 606 607 if (s->macregs[HME_MACI_TXCFG >> 2] & HME_MAC_TXCFG_ENABLE) { 608 sunhme_transmit_frame(s, xmit_buffer, xmit_pos); 609 trace_sunhme_tx_done(xmit_pos); 610 } 611 } 612 613 /* Update status */ 614 status &= ~HME_XD_OWN; 615 pci_dma_write(d, tb + cr * HME_DESC_SIZE, &status, 4); 616 617 /* Move onto next descriptor */ 618 cr++; 619 if (cr >= nr) { 620 cr = 0; 621 } 622 sunhme_set_tx_ring_nr(s, cr); 623 624 pci_dma_read(d, tb + cr * HME_DESC_SIZE, &status, 4); 625 pci_dma_read(d, tb + cr * HME_DESC_SIZE + 4, &buffer, 4); 626 627 /* Indicate TX complete */ 628 intstatus = s->sebregs[HME_SEBI_STAT >> 2]; 629 intstatus |= HME_SEB_STAT_HOSTTOTX; 630 s->sebregs[HME_SEBI_STAT >> 2] = intstatus; 631 632 /* Autoclear TX pending */ 633 s->etxregs[HME_ETXI_PENDING >> 2] = 0; 634 635 sunhme_update_irq(s); 636 } 637 638 /* TX FIFO now clear */ 639 intstatus = s->sebregs[HME_SEBI_STAT >> 2]; 640 intstatus |= HME_SEB_STAT_TXALL; 641 s->sebregs[HME_SEBI_STAT >> 2] = intstatus; 642 sunhme_update_irq(s); 643 } 644 645 static int sunhme_can_receive(NetClientState *nc) 646 { 647 SunHMEState *s = qemu_get_nic_opaque(nc); 648 649 return s->macregs[HME_MAC_RXCFG_ENABLE >> 2] & HME_MAC_RXCFG_ENABLE; 650 } 651 652 static void sunhme_link_status_changed(NetClientState *nc) 653 { 654 SunHMEState *s = qemu_get_nic_opaque(nc); 655 656 if (nc->link_down) { 657 s->miiregs[MII_ANLPAR] &= ~MII_ANLPAR_TXFD; 658 s->miiregs[MII_BMSR] &= ~MII_BMSR_LINK_ST; 659 } else { 660 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD; 661 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; 662 } 663 664 /* Exact bits unknown */ 665 s->mifregs[HME_MIFI_STAT >> 2] = 0xffff; 666 sunhme_update_irq(s); 667 } 668 669 static inline int sunhme_get_rx_ring_count(SunHMEState *s) 670 { 671 uint32_t rings = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_RINGSIZE) 672 >> HME_ERX_CFG_RINGSIZE_SHIFT; 673 674 switch (rings) { 675 case 0: 676 return 32; 677 case 1: 678 return 64; 679 case 2: 680 return 128; 681 case 3: 682 return 256; 683 } 684 685 return 0; 686 } 687 688 static inline int sunhme_get_rx_ring_nr(SunHMEState *s) 689 { 690 return s->erxregs[HME_ERXI_RING >> 2] & HME_ERXI_RING_OFFSET; 691 } 692 693 static inline void sunhme_set_rx_ring_nr(SunHMEState *s, int i) 694 { 695 uint32_t ring = s->erxregs[HME_ERXI_RING >> 2] & ~HME_ERXI_RING_OFFSET; 696 ring |= i & HME_ERXI_RING_OFFSET; 697 698 s->erxregs[HME_ERXI_RING >> 2] = ring; 699 } 700 701 #define POLYNOMIAL_LE 0xedb88320 702 static uint32_t sunhme_crc32_le(const uint8_t *p, int len) 703 { 704 uint32_t crc; 705 int carry, i, j; 706 uint8_t b; 707 708 crc = 0xffffffff; 709 for (i = 0; i < len; i++) { 710 b = *p++; 711 for (j = 0; j < 8; j++) { 712 carry = (crc & 0x1) ^ (b & 0x01); 713 crc >>= 1; 714 b >>= 1; 715 if (carry) { 716 crc = crc ^ POLYNOMIAL_LE; 717 } 718 } 719 } 720 721 return crc; 722 } 723 724 #define MIN_BUF_SIZE 60 725 726 static ssize_t sunhme_receive(NetClientState *nc, const uint8_t *buf, 727 size_t size) 728 { 729 SunHMEState *s = qemu_get_nic_opaque(nc); 730 PCIDevice *d = PCI_DEVICE(s); 731 dma_addr_t rb, addr; 732 uint32_t intstatus, status, buffer, buffersize, sum; 733 uint16_t csum; 734 uint8_t buf1[60]; 735 int nr, cr, len, rxoffset, csum_offset; 736 737 trace_sunhme_rx_incoming(size); 738 739 /* Do nothing if MAC RX disabled */ 740 if (!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_ENABLE)) { 741 return -1; 742 } 743 744 trace_sunhme_rx_filter_destmac(buf[0], buf[1], buf[2], 745 buf[3], buf[4], buf[5]); 746 747 /* Check destination MAC address */ 748 if (!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_PMISC)) { 749 /* Try and match local MAC address */ 750 if (((s->macregs[HME_MACI_MACADDR0 >> 2] & 0xff00) >> 8) == buf[0] && 751 (s->macregs[HME_MACI_MACADDR0 >> 2] & 0xff) == buf[1] && 752 ((s->macregs[HME_MACI_MACADDR1 >> 2] & 0xff00) >> 8) == buf[2] && 753 (s->macregs[HME_MACI_MACADDR1 >> 2] & 0xff) == buf[3] && 754 ((s->macregs[HME_MACI_MACADDR2 >> 2] & 0xff00) >> 8) == buf[4] && 755 (s->macregs[HME_MACI_MACADDR2 >> 2] & 0xff) == buf[5]) { 756 /* Matched local MAC address */ 757 trace_sunhme_rx_filter_local_match(); 758 } else if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff && 759 buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) { 760 /* Matched broadcast address */ 761 trace_sunhme_rx_filter_bcast_match(); 762 } else if (s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_HENABLE) { 763 /* Didn't match local address, check hash filter */ 764 int mcast_idx = sunhme_crc32_le(buf, 6) >> 26; 765 if (!(s->macregs[(HME_MACI_HASHTAB0 >> 2) - (mcast_idx >> 4)] & 766 (1 << (mcast_idx & 0xf)))) { 767 /* Didn't match hash filter */ 768 trace_sunhme_rx_filter_hash_nomatch(); 769 trace_sunhme_rx_filter_reject(); 770 return 0; 771 } else { 772 trace_sunhme_rx_filter_hash_match(); 773 } 774 } else { 775 /* Not for us */ 776 trace_sunhme_rx_filter_reject(); 777 return 0; 778 } 779 } else { 780 trace_sunhme_rx_filter_promisc_match(); 781 } 782 783 trace_sunhme_rx_filter_accept(); 784 785 /* If too small buffer, then expand it */ 786 if (size < MIN_BUF_SIZE) { 787 memcpy(buf1, buf, size); 788 memset(buf1 + size, 0, MIN_BUF_SIZE - size); 789 buf = buf1; 790 size = MIN_BUF_SIZE; 791 } 792 793 rb = s->erxregs[HME_ERXI_RING >> 2] & HME_ERXI_RING_ADDR; 794 nr = sunhme_get_rx_ring_count(s); 795 cr = sunhme_get_rx_ring_nr(s); 796 797 pci_dma_read(d, rb + cr * HME_DESC_SIZE, &status, 4); 798 pci_dma_read(d, rb + cr * HME_DESC_SIZE + 4, &buffer, 4); 799 800 rxoffset = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_BYTEOFFSET) >> 801 HME_ERX_CFG_BYTEOFFSET_SHIFT; 802 803 addr = buffer + rxoffset; 804 buffersize = (status & HME_XD_RXLENMSK) >> HME_XD_RXLENSHIFT; 805 806 /* Detect receive overflow */ 807 len = size; 808 if (size > buffersize) { 809 status |= HME_XD_OFL; 810 len = buffersize; 811 } 812 813 pci_dma_write(d, addr, buf, len); 814 815 trace_sunhme_rx_desc(buffer, rxoffset, status, len, cr, nr); 816 817 /* Calculate the receive checksum */ 818 csum_offset = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_CSUMSTART) >> 819 HME_ERX_CFG_CSUMSHIFT << 1; 820 sum = 0; 821 sum += net_checksum_add(len - csum_offset, (uint8_t *)buf + csum_offset); 822 csum = net_checksum_finish(sum); 823 824 trace_sunhme_rx_xsum_calc(csum); 825 826 /* Update status */ 827 status &= ~HME_XD_OWN; 828 status &= ~HME_XD_RXLENMSK; 829 status |= len << HME_XD_RXLENSHIFT; 830 status &= ~HME_XD_RXCKSUM; 831 status |= csum; 832 833 pci_dma_write(d, rb + cr * HME_DESC_SIZE, &status, 4); 834 835 cr++; 836 if (cr >= nr) { 837 cr = 0; 838 } 839 840 sunhme_set_rx_ring_nr(s, cr); 841 842 /* Indicate RX complete */ 843 intstatus = s->sebregs[HME_SEBI_STAT >> 2]; 844 intstatus |= HME_SEB_STAT_RXTOHOST; 845 s->sebregs[HME_SEBI_STAT >> 2] = intstatus; 846 847 sunhme_update_irq(s); 848 849 return len; 850 } 851 852 static NetClientInfo net_sunhme_info = { 853 .type = NET_CLIENT_DRIVER_NIC, 854 .size = sizeof(NICState), 855 .can_receive = sunhme_can_receive, 856 .receive = sunhme_receive, 857 .link_status_changed = sunhme_link_status_changed, 858 }; 859 860 static void sunhme_realize(PCIDevice *pci_dev, Error **errp) 861 { 862 SunHMEState *s = SUNHME(pci_dev); 863 DeviceState *d = DEVICE(pci_dev); 864 uint8_t *pci_conf; 865 866 pci_conf = pci_dev->config; 867 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 868 869 memory_region_init(&s->hme, OBJECT(pci_dev), "sunhme", HME_REG_SIZE); 870 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->hme); 871 872 memory_region_init_io(&s->sebreg, OBJECT(pci_dev), &sunhme_seb_ops, s, 873 "sunhme.seb", HME_SEB_REG_SIZE); 874 memory_region_add_subregion(&s->hme, 0, &s->sebreg); 875 876 memory_region_init_io(&s->etxreg, OBJECT(pci_dev), &sunhme_etx_ops, s, 877 "sunhme.etx", HME_ETX_REG_SIZE); 878 memory_region_add_subregion(&s->hme, 0x2000, &s->etxreg); 879 880 memory_region_init_io(&s->erxreg, OBJECT(pci_dev), &sunhme_erx_ops, s, 881 "sunhme.erx", HME_ERX_REG_SIZE); 882 memory_region_add_subregion(&s->hme, 0x4000, &s->erxreg); 883 884 memory_region_init_io(&s->macreg, OBJECT(pci_dev), &sunhme_mac_ops, s, 885 "sunhme.mac", HME_MAC_REG_SIZE); 886 memory_region_add_subregion(&s->hme, 0x6000, &s->macreg); 887 888 memory_region_init_io(&s->mifreg, OBJECT(pci_dev), &sunhme_mif_ops, s, 889 "sunhme.mif", HME_MIF_REG_SIZE); 890 memory_region_add_subregion(&s->hme, 0x7000, &s->mifreg); 891 892 qemu_macaddr_default_if_unset(&s->conf.macaddr); 893 s->nic = qemu_new_nic(&net_sunhme_info, &s->conf, 894 object_get_typename(OBJECT(d)), d->id, s); 895 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 896 } 897 898 static void sunhme_instance_init(Object *obj) 899 { 900 SunHMEState *s = SUNHME(obj); 901 902 device_add_bootindex_property(obj, &s->conf.bootindex, 903 "bootindex", "/ethernet-phy@0", 904 DEVICE(obj), NULL); 905 } 906 907 static void sunhme_reset(DeviceState *ds) 908 { 909 SunHMEState *s = SUNHME(ds); 910 911 /* Configure internal transceiver */ 912 s->mifregs[HME_MIFI_CFG >> 2] |= HME_MIF_CFG_MDI0; 913 914 /* Advetise auto, 100Mbps FD */ 915 s->miiregs[MII_ANAR] = MII_ANAR_TXFD; 916 s->miiregs[MII_BMSR] = MII_BMSR_AUTONEG | MII_BMSR_100TX_FD | 917 MII_BMSR_AN_COMP; 918 919 if (!qemu_get_queue(s->nic)->link_down) { 920 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD; 921 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; 922 } 923 924 /* Set manufacturer */ 925 s->miiregs[MII_PHYID1] = DP83840_PHYID1; 926 s->miiregs[MII_PHYID2] = DP83840_PHYID2; 927 928 /* Configure default interrupt mask */ 929 s->mifregs[HME_MIFI_IMASK >> 2] = 0xffff; 930 s->sebregs[HME_SEBI_IMASK >> 2] = 0xff7fffff; 931 } 932 933 static const VMStateDescription vmstate_hme = { 934 .name = "sunhme", 935 .version_id = 0, 936 .minimum_version_id = 0, 937 .fields = (VMStateField[]) { 938 VMSTATE_PCI_DEVICE(parent_obj, SunHMEState), 939 VMSTATE_MACADDR(conf.macaddr, SunHMEState), 940 VMSTATE_UINT32_ARRAY(sebregs, SunHMEState, (HME_SEB_REG_SIZE >> 2)), 941 VMSTATE_UINT32_ARRAY(etxregs, SunHMEState, (HME_ETX_REG_SIZE >> 2)), 942 VMSTATE_UINT32_ARRAY(erxregs, SunHMEState, (HME_ERX_REG_SIZE >> 2)), 943 VMSTATE_UINT32_ARRAY(macregs, SunHMEState, (HME_MAC_REG_SIZE >> 2)), 944 VMSTATE_UINT32_ARRAY(mifregs, SunHMEState, (HME_MIF_REG_SIZE >> 2)), 945 VMSTATE_UINT16_ARRAY(miiregs, SunHMEState, HME_MII_REGS_SIZE), 946 VMSTATE_END_OF_LIST() 947 } 948 }; 949 950 static void sunhme_class_init(ObjectClass *klass, void *data) 951 { 952 DeviceClass *dc = DEVICE_CLASS(klass); 953 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 954 955 k->realize = sunhme_realize; 956 k->vendor_id = PCI_VENDOR_ID_SUN; 957 k->device_id = PCI_DEVICE_ID_SUN_HME; 958 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 959 dc->vmsd = &vmstate_hme; 960 dc->reset = sunhme_reset; 961 dc->props = sunhme_properties; 962 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 963 } 964 965 static const TypeInfo sunhme_info = { 966 .name = TYPE_SUNHME, 967 .parent = TYPE_PCI_DEVICE, 968 .class_init = sunhme_class_init, 969 .instance_size = sizeof(SunHMEState), 970 .instance_init = sunhme_instance_init, 971 .interfaces = (InterfaceInfo[]) { 972 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 973 { } 974 } 975 }; 976 977 static void sunhme_register_types(void) 978 { 979 type_register_static(&sunhme_info); 980 } 981 982 type_init(sunhme_register_types) 983