1 /* 2 * Luminary Micro Stellaris Ethernet Controller 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/irq.h" 12 #include "hw/qdev-properties.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "net/net.h" 16 #include "qemu/log.h" 17 #include "qemu/module.h" 18 #include <zlib.h> 19 #include "qom/object.h" 20 21 //#define DEBUG_STELLARIS_ENET 1 22 23 #ifdef DEBUG_STELLARIS_ENET 24 #define DPRINTF(fmt, ...) \ 25 do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0) 26 #define BADF(fmt, ...) \ 27 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 28 #else 29 #define DPRINTF(fmt, ...) do {} while(0) 30 #define BADF(fmt, ...) \ 31 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0) 32 #endif 33 34 #define SE_INT_RX 0x01 35 #define SE_INT_TXER 0x02 36 #define SE_INT_TXEMP 0x04 37 #define SE_INT_FOV 0x08 38 #define SE_INT_RXER 0x10 39 #define SE_INT_MD 0x20 40 #define SE_INT_PHY 0x40 41 42 #define SE_RCTL_RXEN 0x01 43 #define SE_RCTL_AMUL 0x02 44 #define SE_RCTL_PRMS 0x04 45 #define SE_RCTL_BADCRC 0x08 46 #define SE_RCTL_RSTFIFO 0x10 47 48 #define SE_TCTL_TXEN 0x01 49 #define SE_TCTL_PADEN 0x02 50 #define SE_TCTL_CRC 0x04 51 #define SE_TCTL_DUPLEX 0x08 52 53 #define TYPE_STELLARIS_ENET "stellaris_enet" 54 typedef struct stellaris_enet_state stellaris_enet_state; 55 DECLARE_INSTANCE_CHECKER(stellaris_enet_state, STELLARIS_ENET, 56 TYPE_STELLARIS_ENET) 57 58 typedef struct { 59 uint8_t data[2048]; 60 uint32_t len; 61 } StellarisEnetRxFrame; 62 63 struct stellaris_enet_state { 64 SysBusDevice parent_obj; 65 66 uint32_t ris; 67 uint32_t im; 68 uint32_t rctl; 69 uint32_t tctl; 70 uint32_t thr; 71 uint32_t mctl; 72 uint32_t mdv; 73 uint32_t mtxd; 74 uint32_t mrxd; 75 uint32_t np; 76 uint32_t tx_fifo_len; 77 uint8_t tx_fifo[2048]; 78 /* Real hardware has a 2k fifo, which works out to be at most 31 packets. 79 We implement a full 31 packet fifo. */ 80 StellarisEnetRxFrame rx[31]; 81 uint32_t rx_fifo_offset; 82 uint32_t next_packet; 83 NICState *nic; 84 NICConf conf; 85 qemu_irq irq; 86 MemoryRegion mmio; 87 }; 88 89 static const VMStateDescription vmstate_rx_frame = { 90 .name = "stellaris_enet/rx_frame", 91 .version_id = 1, 92 .minimum_version_id = 1, 93 .fields = (VMStateField[]) { 94 VMSTATE_UINT8_ARRAY(data, StellarisEnetRxFrame, 2048), 95 VMSTATE_UINT32(len, StellarisEnetRxFrame), 96 VMSTATE_END_OF_LIST() 97 } 98 }; 99 100 static int stellaris_enet_post_load(void *opaque, int version_id) 101 { 102 stellaris_enet_state *s = opaque; 103 int i; 104 105 /* Sanitize inbound state. Note that next_packet is an index but 106 * np is a size; hence their valid upper bounds differ. 107 */ 108 if (s->next_packet >= ARRAY_SIZE(s->rx)) { 109 return -1; 110 } 111 112 if (s->np > ARRAY_SIZE(s->rx)) { 113 return -1; 114 } 115 116 for (i = 0; i < ARRAY_SIZE(s->rx); i++) { 117 if (s->rx[i].len > ARRAY_SIZE(s->rx[i].data)) { 118 return -1; 119 } 120 } 121 122 if (s->rx_fifo_offset > ARRAY_SIZE(s->rx[0].data) - 4) { 123 return -1; 124 } 125 126 if (s->tx_fifo_len > ARRAY_SIZE(s->tx_fifo)) { 127 return -1; 128 } 129 130 return 0; 131 } 132 133 static const VMStateDescription vmstate_stellaris_enet = { 134 .name = "stellaris_enet", 135 .version_id = 2, 136 .minimum_version_id = 2, 137 .post_load = stellaris_enet_post_load, 138 .fields = (VMStateField[]) { 139 VMSTATE_UINT32(ris, stellaris_enet_state), 140 VMSTATE_UINT32(im, stellaris_enet_state), 141 VMSTATE_UINT32(rctl, stellaris_enet_state), 142 VMSTATE_UINT32(tctl, stellaris_enet_state), 143 VMSTATE_UINT32(thr, stellaris_enet_state), 144 VMSTATE_UINT32(mctl, stellaris_enet_state), 145 VMSTATE_UINT32(mdv, stellaris_enet_state), 146 VMSTATE_UINT32(mtxd, stellaris_enet_state), 147 VMSTATE_UINT32(mrxd, stellaris_enet_state), 148 VMSTATE_UINT32(np, stellaris_enet_state), 149 VMSTATE_UINT32(tx_fifo_len, stellaris_enet_state), 150 VMSTATE_UINT8_ARRAY(tx_fifo, stellaris_enet_state, 2048), 151 VMSTATE_STRUCT_ARRAY(rx, stellaris_enet_state, 31, 1, 152 vmstate_rx_frame, StellarisEnetRxFrame), 153 VMSTATE_UINT32(rx_fifo_offset, stellaris_enet_state), 154 VMSTATE_UINT32(next_packet, stellaris_enet_state), 155 VMSTATE_END_OF_LIST() 156 } 157 }; 158 159 static void stellaris_enet_update(stellaris_enet_state *s) 160 { 161 qemu_set_irq(s->irq, (s->ris & s->im) != 0); 162 } 163 164 /* Return the data length of the packet currently being assembled 165 * in the TX fifo. 166 */ 167 static inline int stellaris_txpacket_datalen(stellaris_enet_state *s) 168 { 169 return s->tx_fifo[0] | (s->tx_fifo[1] << 8); 170 } 171 172 /* Return true if the packet currently in the TX FIFO is complete, 173 * ie the FIFO holds enough bytes for the data length, ethernet header, 174 * payload and optionally CRC. 175 */ 176 static inline bool stellaris_txpacket_complete(stellaris_enet_state *s) 177 { 178 int framelen = stellaris_txpacket_datalen(s); 179 framelen += 16; 180 if (!(s->tctl & SE_TCTL_CRC)) { 181 framelen += 4; 182 } 183 /* Cover the corner case of a 2032 byte payload with auto-CRC disabled: 184 * this requires more bytes than will fit in the FIFO. It's not totally 185 * clear how the h/w handles this, but if using threshold-based TX 186 * it will definitely try to transmit something. 187 */ 188 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo)); 189 return s->tx_fifo_len >= framelen; 190 } 191 192 /* Return true if the TX FIFO threshold is enabled and the FIFO 193 * has filled enough to reach it. 194 */ 195 static inline bool stellaris_tx_thr_reached(stellaris_enet_state *s) 196 { 197 return (s->thr < 0x3f && 198 (s->tx_fifo_len >= 4 * (s->thr * 8 + 1))); 199 } 200 201 /* Send the packet currently in the TX FIFO */ 202 static void stellaris_enet_send(stellaris_enet_state *s) 203 { 204 int framelen = stellaris_txpacket_datalen(s); 205 206 /* Ethernet header is in the FIFO but not in the datacount. 207 * We don't implement explicit CRC, so just ignore any 208 * CRC value in the FIFO. 209 */ 210 framelen += 14; 211 if ((s->tctl & SE_TCTL_PADEN) && framelen < 60) { 212 memset(&s->tx_fifo[framelen + 2], 0, 60 - framelen); 213 framelen = 60; 214 } 215 /* This MIN will have no effect unless the FIFO data is corrupt 216 * (eg bad data from an incoming migration); otherwise the check 217 * on the datalen at the start of writing the data into the FIFO 218 * will have caught this. Silently write a corrupt half-packet, 219 * which is what the hardware does in FIFO underrun situations. 220 */ 221 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo) - 2); 222 qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo + 2, framelen); 223 s->tx_fifo_len = 0; 224 s->ris |= SE_INT_TXEMP; 225 stellaris_enet_update(s); 226 DPRINTF("Done TX\n"); 227 } 228 229 /* TODO: Implement MAC address filtering. */ 230 static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size) 231 { 232 stellaris_enet_state *s = qemu_get_nic_opaque(nc); 233 int n; 234 uint8_t *p; 235 uint32_t crc; 236 237 if ((s->rctl & SE_RCTL_RXEN) == 0) 238 return -1; 239 if (s->np >= 31) { 240 return 0; 241 } 242 243 DPRINTF("Received packet len=%zu\n", size); 244 n = s->next_packet + s->np; 245 if (n >= 31) 246 n -= 31; 247 248 if (size >= sizeof(s->rx[n].data) - 6) { 249 /* If the packet won't fit into the 250 * emulated 2K RAM, this is reported 251 * as a FIFO overrun error. 252 */ 253 s->ris |= SE_INT_FOV; 254 stellaris_enet_update(s); 255 return -1; 256 } 257 258 s->np++; 259 s->rx[n].len = size + 6; 260 p = s->rx[n].data; 261 *(p++) = (size + 6); 262 *(p++) = (size + 6) >> 8; 263 memcpy (p, buf, size); 264 p += size; 265 crc = crc32(~0, buf, size); 266 *(p++) = crc; 267 *(p++) = crc >> 8; 268 *(p++) = crc >> 16; 269 *(p++) = crc >> 24; 270 /* Clear the remaining bytes in the last word. */ 271 if ((size & 3) != 2) { 272 memset(p, 0, (6 - size) & 3); 273 } 274 275 s->ris |= SE_INT_RX; 276 stellaris_enet_update(s); 277 278 return size; 279 } 280 281 static int stellaris_enet_can_receive(stellaris_enet_state *s) 282 { 283 return (s->np < 31); 284 } 285 286 static uint64_t stellaris_enet_read(void *opaque, hwaddr offset, 287 unsigned size) 288 { 289 stellaris_enet_state *s = (stellaris_enet_state *)opaque; 290 uint32_t val; 291 292 switch (offset) { 293 case 0x00: /* RIS */ 294 DPRINTF("IRQ status %02x\n", s->ris); 295 return s->ris; 296 case 0x04: /* IM */ 297 return s->im; 298 case 0x08: /* RCTL */ 299 return s->rctl; 300 case 0x0c: /* TCTL */ 301 return s->tctl; 302 case 0x10: /* DATA */ 303 { 304 uint8_t *rx_fifo; 305 306 if (s->np == 0) { 307 BADF("RX underflow\n"); 308 return 0; 309 } 310 311 rx_fifo = s->rx[s->next_packet].data + s->rx_fifo_offset; 312 313 val = rx_fifo[0] | (rx_fifo[1] << 8) | (rx_fifo[2] << 16) 314 | (rx_fifo[3] << 24); 315 s->rx_fifo_offset += 4; 316 if (s->rx_fifo_offset >= s->rx[s->next_packet].len) { 317 s->rx_fifo_offset = 0; 318 s->next_packet++; 319 if (s->next_packet >= 31) 320 s->next_packet = 0; 321 s->np--; 322 DPRINTF("RX done np=%d\n", s->np); 323 if (!s->np && stellaris_enet_can_receive(s)) { 324 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 325 } 326 } 327 return val; 328 } 329 case 0x14: /* IA0 */ 330 return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8) 331 | (s->conf.macaddr.a[2] << 16) 332 | ((uint32_t)s->conf.macaddr.a[3] << 24); 333 case 0x18: /* IA1 */ 334 return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8); 335 case 0x1c: /* THR */ 336 return s->thr; 337 case 0x20: /* MCTL */ 338 return s->mctl; 339 case 0x24: /* MDV */ 340 return s->mdv; 341 case 0x28: /* MADD */ 342 return 0; 343 case 0x2c: /* MTXD */ 344 return s->mtxd; 345 case 0x30: /* MRXD */ 346 return s->mrxd; 347 case 0x34: /* NP */ 348 return s->np; 349 case 0x38: /* TR */ 350 return 0; 351 case 0x3c: /* Undocumented: Timestamp? */ 352 return 0; 353 default: 354 qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_rd%d: Illegal register" 355 " 0x02%" HWADDR_PRIx "\n", 356 size * 8, offset); 357 return 0; 358 } 359 } 360 361 static void stellaris_enet_write(void *opaque, hwaddr offset, 362 uint64_t value, unsigned size) 363 { 364 stellaris_enet_state *s = (stellaris_enet_state *)opaque; 365 366 switch (offset) { 367 case 0x00: /* IACK */ 368 s->ris &= ~value; 369 DPRINTF("IRQ ack %02" PRIx64 "/%02x\n", value, s->ris); 370 stellaris_enet_update(s); 371 /* Clearing TXER also resets the TX fifo. */ 372 if (value & SE_INT_TXER) { 373 s->tx_fifo_len = 0; 374 } 375 break; 376 case 0x04: /* IM */ 377 DPRINTF("IRQ mask %02" PRIx64 "/%02x\n", value, s->ris); 378 s->im = value; 379 stellaris_enet_update(s); 380 break; 381 case 0x08: /* RCTL */ 382 s->rctl = value; 383 if (value & SE_RCTL_RSTFIFO) { 384 s->np = 0; 385 s->rx_fifo_offset = 0; 386 stellaris_enet_update(s); 387 } 388 break; 389 case 0x0c: /* TCTL */ 390 s->tctl = value; 391 break; 392 case 0x10: /* DATA */ 393 if (s->tx_fifo_len == 0) { 394 /* The first word is special, it contains the data length */ 395 int framelen = value & 0xffff; 396 if (framelen > 2032) { 397 DPRINTF("TX frame too long (%d)\n", framelen); 398 s->ris |= SE_INT_TXER; 399 stellaris_enet_update(s); 400 break; 401 } 402 } 403 404 if (s->tx_fifo_len + 4 <= ARRAY_SIZE(s->tx_fifo)) { 405 s->tx_fifo[s->tx_fifo_len++] = value; 406 s->tx_fifo[s->tx_fifo_len++] = value >> 8; 407 s->tx_fifo[s->tx_fifo_len++] = value >> 16; 408 s->tx_fifo[s->tx_fifo_len++] = value >> 24; 409 } 410 411 if (stellaris_tx_thr_reached(s) && stellaris_txpacket_complete(s)) { 412 stellaris_enet_send(s); 413 } 414 break; 415 case 0x14: /* IA0 */ 416 s->conf.macaddr.a[0] = value; 417 s->conf.macaddr.a[1] = value >> 8; 418 s->conf.macaddr.a[2] = value >> 16; 419 s->conf.macaddr.a[3] = value >> 24; 420 break; 421 case 0x18: /* IA1 */ 422 s->conf.macaddr.a[4] = value; 423 s->conf.macaddr.a[5] = value >> 8; 424 break; 425 case 0x1c: /* THR */ 426 s->thr = value; 427 break; 428 case 0x20: /* MCTL */ 429 /* TODO: MII registers aren't modelled. 430 * Clear START, indicating that the operation completes immediately. 431 */ 432 s->mctl = value & ~1; 433 break; 434 case 0x24: /* MDV */ 435 s->mdv = value; 436 break; 437 case 0x28: /* MADD */ 438 /* ignored. */ 439 break; 440 case 0x2c: /* MTXD */ 441 s->mtxd = value & 0xff; 442 break; 443 case 0x38: /* TR */ 444 if (value & 1) { 445 stellaris_enet_send(s); 446 } 447 break; 448 case 0x30: /* MRXD */ 449 case 0x34: /* NP */ 450 /* Ignored. */ 451 case 0x3c: /* Undocuented: Timestamp? */ 452 /* Ignored. */ 453 break; 454 default: 455 qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_wr%d: Illegal register " 456 "0x02%" HWADDR_PRIx " = 0x%" PRIx64 "\n", 457 size * 8, offset, value); 458 } 459 } 460 461 static const MemoryRegionOps stellaris_enet_ops = { 462 .read = stellaris_enet_read, 463 .write = stellaris_enet_write, 464 .endianness = DEVICE_NATIVE_ENDIAN, 465 }; 466 467 static void stellaris_enet_reset(DeviceState *dev) 468 { 469 stellaris_enet_state *s = STELLARIS_ENET(dev); 470 471 s->mdv = 0x80; 472 s->rctl = SE_RCTL_BADCRC; 473 s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP 474 | SE_INT_TXER | SE_INT_RX; 475 s->thr = 0x3f; 476 s->tx_fifo_len = 0; 477 } 478 479 static NetClientInfo net_stellaris_enet_info = { 480 .type = NET_CLIENT_DRIVER_NIC, 481 .size = sizeof(NICState), 482 .receive = stellaris_enet_receive, 483 }; 484 485 static void stellaris_enet_realize(DeviceState *dev, Error **errp) 486 { 487 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 488 stellaris_enet_state *s = STELLARIS_ENET(dev); 489 490 memory_region_init_io(&s->mmio, OBJECT(s), &stellaris_enet_ops, s, 491 "stellaris_enet", 0x1000); 492 sysbus_init_mmio(sbd, &s->mmio); 493 sysbus_init_irq(sbd, &s->irq); 494 qemu_macaddr_default_if_unset(&s->conf.macaddr); 495 496 s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf, 497 object_get_typename(OBJECT(dev)), dev->id, s); 498 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 499 } 500 501 static Property stellaris_enet_properties[] = { 502 DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf), 503 DEFINE_PROP_END_OF_LIST(), 504 }; 505 506 static void stellaris_enet_class_init(ObjectClass *klass, void *data) 507 { 508 DeviceClass *dc = DEVICE_CLASS(klass); 509 510 dc->realize = stellaris_enet_realize; 511 dc->reset = stellaris_enet_reset; 512 device_class_set_props(dc, stellaris_enet_properties); 513 dc->vmsd = &vmstate_stellaris_enet; 514 } 515 516 static const TypeInfo stellaris_enet_info = { 517 .name = TYPE_STELLARIS_ENET, 518 .parent = TYPE_SYS_BUS_DEVICE, 519 .instance_size = sizeof(stellaris_enet_state), 520 .class_init = stellaris_enet_class_init, 521 }; 522 523 static void stellaris_enet_register_types(void) 524 { 525 type_register_static(&stellaris_enet_info); 526 } 527 528 type_init(stellaris_enet_register_types) 529