1 /* 2 * Luminary Micro Stellaris Ethernet Controller 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/irq.h" 12 #include "hw/sysbus.h" 13 #include "net/net.h" 14 #include "qemu/log.h" 15 #include "qemu/module.h" 16 #include <zlib.h> 17 18 //#define DEBUG_STELLARIS_ENET 1 19 20 #ifdef DEBUG_STELLARIS_ENET 21 #define DPRINTF(fmt, ...) \ 22 do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0) 23 #define BADF(fmt, ...) \ 24 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 25 #else 26 #define DPRINTF(fmt, ...) do {} while(0) 27 #define BADF(fmt, ...) \ 28 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0) 29 #endif 30 31 #define SE_INT_RX 0x01 32 #define SE_INT_TXER 0x02 33 #define SE_INT_TXEMP 0x04 34 #define SE_INT_FOV 0x08 35 #define SE_INT_RXER 0x10 36 #define SE_INT_MD 0x20 37 #define SE_INT_PHY 0x40 38 39 #define SE_RCTL_RXEN 0x01 40 #define SE_RCTL_AMUL 0x02 41 #define SE_RCTL_PRMS 0x04 42 #define SE_RCTL_BADCRC 0x08 43 #define SE_RCTL_RSTFIFO 0x10 44 45 #define SE_TCTL_TXEN 0x01 46 #define SE_TCTL_PADEN 0x02 47 #define SE_TCTL_CRC 0x04 48 #define SE_TCTL_DUPLEX 0x08 49 50 #define TYPE_STELLARIS_ENET "stellaris_enet" 51 #define STELLARIS_ENET(obj) \ 52 OBJECT_CHECK(stellaris_enet_state, (obj), TYPE_STELLARIS_ENET) 53 54 typedef struct { 55 uint8_t data[2048]; 56 uint32_t len; 57 } StellarisEnetRxFrame; 58 59 typedef struct { 60 SysBusDevice parent_obj; 61 62 uint32_t ris; 63 uint32_t im; 64 uint32_t rctl; 65 uint32_t tctl; 66 uint32_t thr; 67 uint32_t mctl; 68 uint32_t mdv; 69 uint32_t mtxd; 70 uint32_t mrxd; 71 uint32_t np; 72 uint32_t tx_fifo_len; 73 uint8_t tx_fifo[2048]; 74 /* Real hardware has a 2k fifo, which works out to be at most 31 packets. 75 We implement a full 31 packet fifo. */ 76 StellarisEnetRxFrame rx[31]; 77 uint32_t rx_fifo_offset; 78 uint32_t next_packet; 79 NICState *nic; 80 NICConf conf; 81 qemu_irq irq; 82 MemoryRegion mmio; 83 } stellaris_enet_state; 84 85 static const VMStateDescription vmstate_rx_frame = { 86 .name = "stellaris_enet/rx_frame", 87 .version_id = 1, 88 .minimum_version_id = 1, 89 .fields = (VMStateField[]) { 90 VMSTATE_UINT8_ARRAY(data, StellarisEnetRxFrame, 2048), 91 VMSTATE_UINT32(len, StellarisEnetRxFrame), 92 VMSTATE_END_OF_LIST() 93 } 94 }; 95 96 static int stellaris_enet_post_load(void *opaque, int version_id) 97 { 98 stellaris_enet_state *s = opaque; 99 int i; 100 101 /* Sanitize inbound state. Note that next_packet is an index but 102 * np is a size; hence their valid upper bounds differ. 103 */ 104 if (s->next_packet >= ARRAY_SIZE(s->rx)) { 105 return -1; 106 } 107 108 if (s->np > ARRAY_SIZE(s->rx)) { 109 return -1; 110 } 111 112 for (i = 0; i < ARRAY_SIZE(s->rx); i++) { 113 if (s->rx[i].len > ARRAY_SIZE(s->rx[i].data)) { 114 return -1; 115 } 116 } 117 118 if (s->rx_fifo_offset > ARRAY_SIZE(s->rx[0].data) - 4) { 119 return -1; 120 } 121 122 if (s->tx_fifo_len > ARRAY_SIZE(s->tx_fifo)) { 123 return -1; 124 } 125 126 return 0; 127 } 128 129 static const VMStateDescription vmstate_stellaris_enet = { 130 .name = "stellaris_enet", 131 .version_id = 2, 132 .minimum_version_id = 2, 133 .post_load = stellaris_enet_post_load, 134 .fields = (VMStateField[]) { 135 VMSTATE_UINT32(ris, stellaris_enet_state), 136 VMSTATE_UINT32(im, stellaris_enet_state), 137 VMSTATE_UINT32(rctl, stellaris_enet_state), 138 VMSTATE_UINT32(tctl, stellaris_enet_state), 139 VMSTATE_UINT32(thr, stellaris_enet_state), 140 VMSTATE_UINT32(mctl, stellaris_enet_state), 141 VMSTATE_UINT32(mdv, stellaris_enet_state), 142 VMSTATE_UINT32(mtxd, stellaris_enet_state), 143 VMSTATE_UINT32(mrxd, stellaris_enet_state), 144 VMSTATE_UINT32(np, stellaris_enet_state), 145 VMSTATE_UINT32(tx_fifo_len, stellaris_enet_state), 146 VMSTATE_UINT8_ARRAY(tx_fifo, stellaris_enet_state, 2048), 147 VMSTATE_STRUCT_ARRAY(rx, stellaris_enet_state, 31, 1, 148 vmstate_rx_frame, StellarisEnetRxFrame), 149 VMSTATE_UINT32(rx_fifo_offset, stellaris_enet_state), 150 VMSTATE_UINT32(next_packet, stellaris_enet_state), 151 VMSTATE_END_OF_LIST() 152 } 153 }; 154 155 static void stellaris_enet_update(stellaris_enet_state *s) 156 { 157 qemu_set_irq(s->irq, (s->ris & s->im) != 0); 158 } 159 160 /* Return the data length of the packet currently being assembled 161 * in the TX fifo. 162 */ 163 static inline int stellaris_txpacket_datalen(stellaris_enet_state *s) 164 { 165 return s->tx_fifo[0] | (s->tx_fifo[1] << 8); 166 } 167 168 /* Return true if the packet currently in the TX FIFO is complete, 169 * ie the FIFO holds enough bytes for the data length, ethernet header, 170 * payload and optionally CRC. 171 */ 172 static inline bool stellaris_txpacket_complete(stellaris_enet_state *s) 173 { 174 int framelen = stellaris_txpacket_datalen(s); 175 framelen += 16; 176 if (!(s->tctl & SE_TCTL_CRC)) { 177 framelen += 4; 178 } 179 /* Cover the corner case of a 2032 byte payload with auto-CRC disabled: 180 * this requires more bytes than will fit in the FIFO. It's not totally 181 * clear how the h/w handles this, but if using threshold-based TX 182 * it will definitely try to transmit something. 183 */ 184 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo)); 185 return s->tx_fifo_len >= framelen; 186 } 187 188 /* Return true if the TX FIFO threshold is enabled and the FIFO 189 * has filled enough to reach it. 190 */ 191 static inline bool stellaris_tx_thr_reached(stellaris_enet_state *s) 192 { 193 return (s->thr < 0x3f && 194 (s->tx_fifo_len >= 4 * (s->thr * 8 + 1))); 195 } 196 197 /* Send the packet currently in the TX FIFO */ 198 static void stellaris_enet_send(stellaris_enet_state *s) 199 { 200 int framelen = stellaris_txpacket_datalen(s); 201 202 /* Ethernet header is in the FIFO but not in the datacount. 203 * We don't implement explicit CRC, so just ignore any 204 * CRC value in the FIFO. 205 */ 206 framelen += 14; 207 if ((s->tctl & SE_TCTL_PADEN) && framelen < 60) { 208 memset(&s->tx_fifo[framelen + 2], 0, 60 - framelen); 209 framelen = 60; 210 } 211 /* This MIN will have no effect unless the FIFO data is corrupt 212 * (eg bad data from an incoming migration); otherwise the check 213 * on the datalen at the start of writing the data into the FIFO 214 * will have caught this. Silently write a corrupt half-packet, 215 * which is what the hardware does in FIFO underrun situations. 216 */ 217 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo) - 2); 218 qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo + 2, framelen); 219 s->tx_fifo_len = 0; 220 s->ris |= SE_INT_TXEMP; 221 stellaris_enet_update(s); 222 DPRINTF("Done TX\n"); 223 } 224 225 /* TODO: Implement MAC address filtering. */ 226 static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size) 227 { 228 stellaris_enet_state *s = qemu_get_nic_opaque(nc); 229 int n; 230 uint8_t *p; 231 uint32_t crc; 232 233 if ((s->rctl & SE_RCTL_RXEN) == 0) 234 return -1; 235 if (s->np >= 31) { 236 return 0; 237 } 238 239 DPRINTF("Received packet len=%zu\n", size); 240 n = s->next_packet + s->np; 241 if (n >= 31) 242 n -= 31; 243 244 if (size >= sizeof(s->rx[n].data) - 6) { 245 /* If the packet won't fit into the 246 * emulated 2K RAM, this is reported 247 * as a FIFO overrun error. 248 */ 249 s->ris |= SE_INT_FOV; 250 stellaris_enet_update(s); 251 return -1; 252 } 253 254 s->np++; 255 s->rx[n].len = size + 6; 256 p = s->rx[n].data; 257 *(p++) = (size + 6); 258 *(p++) = (size + 6) >> 8; 259 memcpy (p, buf, size); 260 p += size; 261 crc = crc32(~0, buf, size); 262 *(p++) = crc; 263 *(p++) = crc >> 8; 264 *(p++) = crc >> 16; 265 *(p++) = crc >> 24; 266 /* Clear the remaining bytes in the last word. */ 267 if ((size & 3) != 2) { 268 memset(p, 0, (6 - size) & 3); 269 } 270 271 s->ris |= SE_INT_RX; 272 stellaris_enet_update(s); 273 274 return size; 275 } 276 277 static int stellaris_enet_can_receive(stellaris_enet_state *s) 278 { 279 return (s->np < 31); 280 } 281 282 static uint64_t stellaris_enet_read(void *opaque, hwaddr offset, 283 unsigned size) 284 { 285 stellaris_enet_state *s = (stellaris_enet_state *)opaque; 286 uint32_t val; 287 288 switch (offset) { 289 case 0x00: /* RIS */ 290 DPRINTF("IRQ status %02x\n", s->ris); 291 return s->ris; 292 case 0x04: /* IM */ 293 return s->im; 294 case 0x08: /* RCTL */ 295 return s->rctl; 296 case 0x0c: /* TCTL */ 297 return s->tctl; 298 case 0x10: /* DATA */ 299 { 300 uint8_t *rx_fifo; 301 302 if (s->np == 0) { 303 BADF("RX underflow\n"); 304 return 0; 305 } 306 307 rx_fifo = s->rx[s->next_packet].data + s->rx_fifo_offset; 308 309 val = rx_fifo[0] | (rx_fifo[1] << 8) | (rx_fifo[2] << 16) 310 | (rx_fifo[3] << 24); 311 s->rx_fifo_offset += 4; 312 if (s->rx_fifo_offset >= s->rx[s->next_packet].len) { 313 s->rx_fifo_offset = 0; 314 s->next_packet++; 315 if (s->next_packet >= 31) 316 s->next_packet = 0; 317 s->np--; 318 DPRINTF("RX done np=%d\n", s->np); 319 if (!s->np && stellaris_enet_can_receive(s)) { 320 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 321 } 322 } 323 return val; 324 } 325 case 0x14: /* IA0 */ 326 return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8) 327 | (s->conf.macaddr.a[2] << 16) 328 | ((uint32_t)s->conf.macaddr.a[3] << 24); 329 case 0x18: /* IA1 */ 330 return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8); 331 case 0x1c: /* THR */ 332 return s->thr; 333 case 0x20: /* MCTL */ 334 return s->mctl; 335 case 0x24: /* MDV */ 336 return s->mdv; 337 case 0x28: /* MADD */ 338 return 0; 339 case 0x2c: /* MTXD */ 340 return s->mtxd; 341 case 0x30: /* MRXD */ 342 return s->mrxd; 343 case 0x34: /* NP */ 344 return s->np; 345 case 0x38: /* TR */ 346 return 0; 347 case 0x3c: /* Undocumented: Timestamp? */ 348 return 0; 349 default: 350 qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_rd%d: Illegal register" 351 " 0x02%" HWADDR_PRIx "\n", 352 size * 8, offset); 353 return 0; 354 } 355 } 356 357 static void stellaris_enet_write(void *opaque, hwaddr offset, 358 uint64_t value, unsigned size) 359 { 360 stellaris_enet_state *s = (stellaris_enet_state *)opaque; 361 362 switch (offset) { 363 case 0x00: /* IACK */ 364 s->ris &= ~value; 365 DPRINTF("IRQ ack %02" PRIx64 "/%02x\n", value, s->ris); 366 stellaris_enet_update(s); 367 /* Clearing TXER also resets the TX fifo. */ 368 if (value & SE_INT_TXER) { 369 s->tx_fifo_len = 0; 370 } 371 break; 372 case 0x04: /* IM */ 373 DPRINTF("IRQ mask %02" PRIx64 "/%02x\n", value, s->ris); 374 s->im = value; 375 stellaris_enet_update(s); 376 break; 377 case 0x08: /* RCTL */ 378 s->rctl = value; 379 if (value & SE_RCTL_RSTFIFO) { 380 s->np = 0; 381 s->rx_fifo_offset = 0; 382 stellaris_enet_update(s); 383 } 384 break; 385 case 0x0c: /* TCTL */ 386 s->tctl = value; 387 break; 388 case 0x10: /* DATA */ 389 if (s->tx_fifo_len == 0) { 390 /* The first word is special, it contains the data length */ 391 int framelen = value & 0xffff; 392 if (framelen > 2032) { 393 DPRINTF("TX frame too long (%d)\n", framelen); 394 s->ris |= SE_INT_TXER; 395 stellaris_enet_update(s); 396 break; 397 } 398 } 399 400 if (s->tx_fifo_len + 4 <= ARRAY_SIZE(s->tx_fifo)) { 401 s->tx_fifo[s->tx_fifo_len++] = value; 402 s->tx_fifo[s->tx_fifo_len++] = value >> 8; 403 s->tx_fifo[s->tx_fifo_len++] = value >> 16; 404 s->tx_fifo[s->tx_fifo_len++] = value >> 24; 405 } 406 407 if (stellaris_tx_thr_reached(s) && stellaris_txpacket_complete(s)) { 408 stellaris_enet_send(s); 409 } 410 break; 411 case 0x14: /* IA0 */ 412 s->conf.macaddr.a[0] = value; 413 s->conf.macaddr.a[1] = value >> 8; 414 s->conf.macaddr.a[2] = value >> 16; 415 s->conf.macaddr.a[3] = value >> 24; 416 break; 417 case 0x18: /* IA1 */ 418 s->conf.macaddr.a[4] = value; 419 s->conf.macaddr.a[5] = value >> 8; 420 break; 421 case 0x1c: /* THR */ 422 s->thr = value; 423 break; 424 case 0x20: /* MCTL */ 425 /* TODO: MII registers aren't modelled. 426 * Clear START, indicating that the operation completes immediately. 427 */ 428 s->mctl = value & ~1; 429 break; 430 case 0x24: /* MDV */ 431 s->mdv = value; 432 break; 433 case 0x28: /* MADD */ 434 /* ignored. */ 435 break; 436 case 0x2c: /* MTXD */ 437 s->mtxd = value & 0xff; 438 break; 439 case 0x38: /* TR */ 440 if (value & 1) { 441 stellaris_enet_send(s); 442 } 443 break; 444 case 0x30: /* MRXD */ 445 case 0x34: /* NP */ 446 /* Ignored. */ 447 case 0x3c: /* Undocuented: Timestamp? */ 448 /* Ignored. */ 449 break; 450 default: 451 qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_wr%d: Illegal register " 452 "0x02%" HWADDR_PRIx " = 0x%" PRIx64 "\n", 453 size * 8, offset, value); 454 } 455 } 456 457 static const MemoryRegionOps stellaris_enet_ops = { 458 .read = stellaris_enet_read, 459 .write = stellaris_enet_write, 460 .endianness = DEVICE_NATIVE_ENDIAN, 461 }; 462 463 static void stellaris_enet_reset(DeviceState *dev) 464 { 465 stellaris_enet_state *s = STELLARIS_ENET(dev); 466 467 s->mdv = 0x80; 468 s->rctl = SE_RCTL_BADCRC; 469 s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP 470 | SE_INT_TXER | SE_INT_RX; 471 s->thr = 0x3f; 472 s->tx_fifo_len = 0; 473 } 474 475 static NetClientInfo net_stellaris_enet_info = { 476 .type = NET_CLIENT_DRIVER_NIC, 477 .size = sizeof(NICState), 478 .receive = stellaris_enet_receive, 479 }; 480 481 static void stellaris_enet_realize(DeviceState *dev, Error **errp) 482 { 483 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 484 stellaris_enet_state *s = STELLARIS_ENET(dev); 485 486 memory_region_init_io(&s->mmio, OBJECT(s), &stellaris_enet_ops, s, 487 "stellaris_enet", 0x1000); 488 sysbus_init_mmio(sbd, &s->mmio); 489 sysbus_init_irq(sbd, &s->irq); 490 qemu_macaddr_default_if_unset(&s->conf.macaddr); 491 492 s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf, 493 object_get_typename(OBJECT(dev)), dev->id, s); 494 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 495 } 496 497 static Property stellaris_enet_properties[] = { 498 DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf), 499 DEFINE_PROP_END_OF_LIST(), 500 }; 501 502 static void stellaris_enet_class_init(ObjectClass *klass, void *data) 503 { 504 DeviceClass *dc = DEVICE_CLASS(klass); 505 506 dc->realize = stellaris_enet_realize; 507 dc->reset = stellaris_enet_reset; 508 dc->props = stellaris_enet_properties; 509 dc->vmsd = &vmstate_stellaris_enet; 510 } 511 512 static const TypeInfo stellaris_enet_info = { 513 .name = TYPE_STELLARIS_ENET, 514 .parent = TYPE_SYS_BUS_DEVICE, 515 .instance_size = sizeof(stellaris_enet_state), 516 .class_init = stellaris_enet_class_init, 517 }; 518 519 static void stellaris_enet_register_types(void) 520 { 521 type_register_static(&stellaris_enet_info); 522 } 523 524 type_init(stellaris_enet_register_types) 525