1 /* 2 * Luminary Micro Stellaris Ethernet Controller 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/sysbus.h" 12 #include "net/net.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include <zlib.h> 16 17 //#define DEBUG_STELLARIS_ENET 1 18 19 #ifdef DEBUG_STELLARIS_ENET 20 #define DPRINTF(fmt, ...) \ 21 do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0) 22 #define BADF(fmt, ...) \ 23 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 24 #else 25 #define DPRINTF(fmt, ...) do {} while(0) 26 #define BADF(fmt, ...) \ 27 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0) 28 #endif 29 30 #define SE_INT_RX 0x01 31 #define SE_INT_TXER 0x02 32 #define SE_INT_TXEMP 0x04 33 #define SE_INT_FOV 0x08 34 #define SE_INT_RXER 0x10 35 #define SE_INT_MD 0x20 36 #define SE_INT_PHY 0x40 37 38 #define SE_RCTL_RXEN 0x01 39 #define SE_RCTL_AMUL 0x02 40 #define SE_RCTL_PRMS 0x04 41 #define SE_RCTL_BADCRC 0x08 42 #define SE_RCTL_RSTFIFO 0x10 43 44 #define SE_TCTL_TXEN 0x01 45 #define SE_TCTL_PADEN 0x02 46 #define SE_TCTL_CRC 0x04 47 #define SE_TCTL_DUPLEX 0x08 48 49 #define TYPE_STELLARIS_ENET "stellaris_enet" 50 #define STELLARIS_ENET(obj) \ 51 OBJECT_CHECK(stellaris_enet_state, (obj), TYPE_STELLARIS_ENET) 52 53 typedef struct { 54 uint8_t data[2048]; 55 uint32_t len; 56 } StellarisEnetRxFrame; 57 58 typedef struct { 59 SysBusDevice parent_obj; 60 61 uint32_t ris; 62 uint32_t im; 63 uint32_t rctl; 64 uint32_t tctl; 65 uint32_t thr; 66 uint32_t mctl; 67 uint32_t mdv; 68 uint32_t mtxd; 69 uint32_t mrxd; 70 uint32_t np; 71 uint32_t tx_fifo_len; 72 uint8_t tx_fifo[2048]; 73 /* Real hardware has a 2k fifo, which works out to be at most 31 packets. 74 We implement a full 31 packet fifo. */ 75 StellarisEnetRxFrame rx[31]; 76 uint32_t rx_fifo_offset; 77 uint32_t next_packet; 78 NICState *nic; 79 NICConf conf; 80 qemu_irq irq; 81 MemoryRegion mmio; 82 } stellaris_enet_state; 83 84 static const VMStateDescription vmstate_rx_frame = { 85 .name = "stellaris_enet/rx_frame", 86 .version_id = 1, 87 .minimum_version_id = 1, 88 .fields = (VMStateField[]) { 89 VMSTATE_UINT8_ARRAY(data, StellarisEnetRxFrame, 2048), 90 VMSTATE_UINT32(len, StellarisEnetRxFrame), 91 VMSTATE_END_OF_LIST() 92 } 93 }; 94 95 static int stellaris_enet_post_load(void *opaque, int version_id) 96 { 97 stellaris_enet_state *s = opaque; 98 int i; 99 100 /* Sanitize inbound state. Note that next_packet is an index but 101 * np is a size; hence their valid upper bounds differ. 102 */ 103 if (s->next_packet >= ARRAY_SIZE(s->rx)) { 104 return -1; 105 } 106 107 if (s->np > ARRAY_SIZE(s->rx)) { 108 return -1; 109 } 110 111 for (i = 0; i < ARRAY_SIZE(s->rx); i++) { 112 if (s->rx[i].len > ARRAY_SIZE(s->rx[i].data)) { 113 return -1; 114 } 115 } 116 117 if (s->rx_fifo_offset > ARRAY_SIZE(s->rx[0].data) - 4) { 118 return -1; 119 } 120 121 if (s->tx_fifo_len > ARRAY_SIZE(s->tx_fifo)) { 122 return -1; 123 } 124 125 return 0; 126 } 127 128 static const VMStateDescription vmstate_stellaris_enet = { 129 .name = "stellaris_enet", 130 .version_id = 2, 131 .minimum_version_id = 2, 132 .post_load = stellaris_enet_post_load, 133 .fields = (VMStateField[]) { 134 VMSTATE_UINT32(ris, stellaris_enet_state), 135 VMSTATE_UINT32(im, stellaris_enet_state), 136 VMSTATE_UINT32(rctl, stellaris_enet_state), 137 VMSTATE_UINT32(tctl, stellaris_enet_state), 138 VMSTATE_UINT32(thr, stellaris_enet_state), 139 VMSTATE_UINT32(mctl, stellaris_enet_state), 140 VMSTATE_UINT32(mdv, stellaris_enet_state), 141 VMSTATE_UINT32(mtxd, stellaris_enet_state), 142 VMSTATE_UINT32(mrxd, stellaris_enet_state), 143 VMSTATE_UINT32(np, stellaris_enet_state), 144 VMSTATE_UINT32(tx_fifo_len, stellaris_enet_state), 145 VMSTATE_UINT8_ARRAY(tx_fifo, stellaris_enet_state, 2048), 146 VMSTATE_STRUCT_ARRAY(rx, stellaris_enet_state, 31, 1, 147 vmstate_rx_frame, StellarisEnetRxFrame), 148 VMSTATE_UINT32(rx_fifo_offset, stellaris_enet_state), 149 VMSTATE_UINT32(next_packet, stellaris_enet_state), 150 VMSTATE_END_OF_LIST() 151 } 152 }; 153 154 static void stellaris_enet_update(stellaris_enet_state *s) 155 { 156 qemu_set_irq(s->irq, (s->ris & s->im) != 0); 157 } 158 159 /* Return the data length of the packet currently being assembled 160 * in the TX fifo. 161 */ 162 static inline int stellaris_txpacket_datalen(stellaris_enet_state *s) 163 { 164 return s->tx_fifo[0] | (s->tx_fifo[1] << 8); 165 } 166 167 /* Return true if the packet currently in the TX FIFO is complete, 168 * ie the FIFO holds enough bytes for the data length, ethernet header, 169 * payload and optionally CRC. 170 */ 171 static inline bool stellaris_txpacket_complete(stellaris_enet_state *s) 172 { 173 int framelen = stellaris_txpacket_datalen(s); 174 framelen += 16; 175 if (!(s->tctl & SE_TCTL_CRC)) { 176 framelen += 4; 177 } 178 /* Cover the corner case of a 2032 byte payload with auto-CRC disabled: 179 * this requires more bytes than will fit in the FIFO. It's not totally 180 * clear how the h/w handles this, but if using threshold-based TX 181 * it will definitely try to transmit something. 182 */ 183 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo)); 184 return s->tx_fifo_len >= framelen; 185 } 186 187 /* Return true if the TX FIFO threshold is enabled and the FIFO 188 * has filled enough to reach it. 189 */ 190 static inline bool stellaris_tx_thr_reached(stellaris_enet_state *s) 191 { 192 return (s->thr < 0x3f && 193 (s->tx_fifo_len >= 4 * (s->thr * 8 + 1))); 194 } 195 196 /* Send the packet currently in the TX FIFO */ 197 static void stellaris_enet_send(stellaris_enet_state *s) 198 { 199 int framelen = stellaris_txpacket_datalen(s); 200 201 /* Ethernet header is in the FIFO but not in the datacount. 202 * We don't implement explicit CRC, so just ignore any 203 * CRC value in the FIFO. 204 */ 205 framelen += 14; 206 if ((s->tctl & SE_TCTL_PADEN) && framelen < 60) { 207 memset(&s->tx_fifo[framelen + 2], 0, 60 - framelen); 208 framelen = 60; 209 } 210 /* This MIN will have no effect unless the FIFO data is corrupt 211 * (eg bad data from an incoming migration); otherwise the check 212 * on the datalen at the start of writing the data into the FIFO 213 * will have caught this. Silently write a corrupt half-packet, 214 * which is what the hardware does in FIFO underrun situations. 215 */ 216 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo) - 2); 217 qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo + 2, framelen); 218 s->tx_fifo_len = 0; 219 s->ris |= SE_INT_TXEMP; 220 stellaris_enet_update(s); 221 DPRINTF("Done TX\n"); 222 } 223 224 /* TODO: Implement MAC address filtering. */ 225 static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size) 226 { 227 stellaris_enet_state *s = qemu_get_nic_opaque(nc); 228 int n; 229 uint8_t *p; 230 uint32_t crc; 231 232 if ((s->rctl & SE_RCTL_RXEN) == 0) 233 return -1; 234 if (s->np >= 31) { 235 return 0; 236 } 237 238 DPRINTF("Received packet len=%zu\n", size); 239 n = s->next_packet + s->np; 240 if (n >= 31) 241 n -= 31; 242 243 if (size >= sizeof(s->rx[n].data) - 6) { 244 /* If the packet won't fit into the 245 * emulated 2K RAM, this is reported 246 * as a FIFO overrun error. 247 */ 248 s->ris |= SE_INT_FOV; 249 stellaris_enet_update(s); 250 return -1; 251 } 252 253 s->np++; 254 s->rx[n].len = size + 6; 255 p = s->rx[n].data; 256 *(p++) = (size + 6); 257 *(p++) = (size + 6) >> 8; 258 memcpy (p, buf, size); 259 p += size; 260 crc = crc32(~0, buf, size); 261 *(p++) = crc; 262 *(p++) = crc >> 8; 263 *(p++) = crc >> 16; 264 *(p++) = crc >> 24; 265 /* Clear the remaining bytes in the last word. */ 266 if ((size & 3) != 2) { 267 memset(p, 0, (6 - size) & 3); 268 } 269 270 s->ris |= SE_INT_RX; 271 stellaris_enet_update(s); 272 273 return size; 274 } 275 276 static int stellaris_enet_can_receive(stellaris_enet_state *s) 277 { 278 return (s->np < 31); 279 } 280 281 static uint64_t stellaris_enet_read(void *opaque, hwaddr offset, 282 unsigned size) 283 { 284 stellaris_enet_state *s = (stellaris_enet_state *)opaque; 285 uint32_t val; 286 287 switch (offset) { 288 case 0x00: /* RIS */ 289 DPRINTF("IRQ status %02x\n", s->ris); 290 return s->ris; 291 case 0x04: /* IM */ 292 return s->im; 293 case 0x08: /* RCTL */ 294 return s->rctl; 295 case 0x0c: /* TCTL */ 296 return s->tctl; 297 case 0x10: /* DATA */ 298 { 299 uint8_t *rx_fifo; 300 301 if (s->np == 0) { 302 BADF("RX underflow\n"); 303 return 0; 304 } 305 306 rx_fifo = s->rx[s->next_packet].data + s->rx_fifo_offset; 307 308 val = rx_fifo[0] | (rx_fifo[1] << 8) | (rx_fifo[2] << 16) 309 | (rx_fifo[3] << 24); 310 s->rx_fifo_offset += 4; 311 if (s->rx_fifo_offset >= s->rx[s->next_packet].len) { 312 s->rx_fifo_offset = 0; 313 s->next_packet++; 314 if (s->next_packet >= 31) 315 s->next_packet = 0; 316 s->np--; 317 DPRINTF("RX done np=%d\n", s->np); 318 if (!s->np && stellaris_enet_can_receive(s)) { 319 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 320 } 321 } 322 return val; 323 } 324 case 0x14: /* IA0 */ 325 return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8) 326 | (s->conf.macaddr.a[2] << 16) 327 | ((uint32_t)s->conf.macaddr.a[3] << 24); 328 case 0x18: /* IA1 */ 329 return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8); 330 case 0x1c: /* THR */ 331 return s->thr; 332 case 0x20: /* MCTL */ 333 return s->mctl; 334 case 0x24: /* MDV */ 335 return s->mdv; 336 case 0x28: /* MADD */ 337 return 0; 338 case 0x2c: /* MTXD */ 339 return s->mtxd; 340 case 0x30: /* MRXD */ 341 return s->mrxd; 342 case 0x34: /* NP */ 343 return s->np; 344 case 0x38: /* TR */ 345 return 0; 346 case 0x3c: /* Undocumented: Timestamp? */ 347 return 0; 348 default: 349 qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_rd%d: Illegal register" 350 " 0x02%" HWADDR_PRIx "\n", 351 size * 8, offset); 352 return 0; 353 } 354 } 355 356 static void stellaris_enet_write(void *opaque, hwaddr offset, 357 uint64_t value, unsigned size) 358 { 359 stellaris_enet_state *s = (stellaris_enet_state *)opaque; 360 361 switch (offset) { 362 case 0x00: /* IACK */ 363 s->ris &= ~value; 364 DPRINTF("IRQ ack %02" PRIx64 "/%02x\n", value, s->ris); 365 stellaris_enet_update(s); 366 /* Clearing TXER also resets the TX fifo. */ 367 if (value & SE_INT_TXER) { 368 s->tx_fifo_len = 0; 369 } 370 break; 371 case 0x04: /* IM */ 372 DPRINTF("IRQ mask %02" PRIx64 "/%02x\n", value, s->ris); 373 s->im = value; 374 stellaris_enet_update(s); 375 break; 376 case 0x08: /* RCTL */ 377 s->rctl = value; 378 if (value & SE_RCTL_RSTFIFO) { 379 s->np = 0; 380 s->rx_fifo_offset = 0; 381 stellaris_enet_update(s); 382 } 383 break; 384 case 0x0c: /* TCTL */ 385 s->tctl = value; 386 break; 387 case 0x10: /* DATA */ 388 if (s->tx_fifo_len == 0) { 389 /* The first word is special, it contains the data length */ 390 int framelen = value & 0xffff; 391 if (framelen > 2032) { 392 DPRINTF("TX frame too long (%d)\n", framelen); 393 s->ris |= SE_INT_TXER; 394 stellaris_enet_update(s); 395 break; 396 } 397 } 398 399 if (s->tx_fifo_len + 4 <= ARRAY_SIZE(s->tx_fifo)) { 400 s->tx_fifo[s->tx_fifo_len++] = value; 401 s->tx_fifo[s->tx_fifo_len++] = value >> 8; 402 s->tx_fifo[s->tx_fifo_len++] = value >> 16; 403 s->tx_fifo[s->tx_fifo_len++] = value >> 24; 404 } 405 406 if (stellaris_tx_thr_reached(s) && stellaris_txpacket_complete(s)) { 407 stellaris_enet_send(s); 408 } 409 break; 410 case 0x14: /* IA0 */ 411 s->conf.macaddr.a[0] = value; 412 s->conf.macaddr.a[1] = value >> 8; 413 s->conf.macaddr.a[2] = value >> 16; 414 s->conf.macaddr.a[3] = value >> 24; 415 break; 416 case 0x18: /* IA1 */ 417 s->conf.macaddr.a[4] = value; 418 s->conf.macaddr.a[5] = value >> 8; 419 break; 420 case 0x1c: /* THR */ 421 s->thr = value; 422 break; 423 case 0x20: /* MCTL */ 424 /* TODO: MII registers aren't modelled. 425 * Clear START, indicating that the operation completes immediately. 426 */ 427 s->mctl = value & ~1; 428 break; 429 case 0x24: /* MDV */ 430 s->mdv = value; 431 break; 432 case 0x28: /* MADD */ 433 /* ignored. */ 434 break; 435 case 0x2c: /* MTXD */ 436 s->mtxd = value & 0xff; 437 break; 438 case 0x38: /* TR */ 439 if (value & 1) { 440 stellaris_enet_send(s); 441 } 442 break; 443 case 0x30: /* MRXD */ 444 case 0x34: /* NP */ 445 /* Ignored. */ 446 case 0x3c: /* Undocuented: Timestamp? */ 447 /* Ignored. */ 448 break; 449 default: 450 qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_wr%d: Illegal register " 451 "0x02%" HWADDR_PRIx " = 0x%" PRIx64 "\n", 452 size * 8, offset, value); 453 } 454 } 455 456 static const MemoryRegionOps stellaris_enet_ops = { 457 .read = stellaris_enet_read, 458 .write = stellaris_enet_write, 459 .endianness = DEVICE_NATIVE_ENDIAN, 460 }; 461 462 static void stellaris_enet_reset(DeviceState *dev) 463 { 464 stellaris_enet_state *s = STELLARIS_ENET(dev); 465 466 s->mdv = 0x80; 467 s->rctl = SE_RCTL_BADCRC; 468 s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP 469 | SE_INT_TXER | SE_INT_RX; 470 s->thr = 0x3f; 471 s->tx_fifo_len = 0; 472 } 473 474 static NetClientInfo net_stellaris_enet_info = { 475 .type = NET_CLIENT_DRIVER_NIC, 476 .size = sizeof(NICState), 477 .receive = stellaris_enet_receive, 478 }; 479 480 static void stellaris_enet_realize(DeviceState *dev, Error **errp) 481 { 482 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 483 stellaris_enet_state *s = STELLARIS_ENET(dev); 484 485 memory_region_init_io(&s->mmio, OBJECT(s), &stellaris_enet_ops, s, 486 "stellaris_enet", 0x1000); 487 sysbus_init_mmio(sbd, &s->mmio); 488 sysbus_init_irq(sbd, &s->irq); 489 qemu_macaddr_default_if_unset(&s->conf.macaddr); 490 491 s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf, 492 object_get_typename(OBJECT(dev)), dev->id, s); 493 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 494 } 495 496 static Property stellaris_enet_properties[] = { 497 DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf), 498 DEFINE_PROP_END_OF_LIST(), 499 }; 500 501 static void stellaris_enet_class_init(ObjectClass *klass, void *data) 502 { 503 DeviceClass *dc = DEVICE_CLASS(klass); 504 505 dc->realize = stellaris_enet_realize; 506 dc->reset = stellaris_enet_reset; 507 dc->props = stellaris_enet_properties; 508 dc->vmsd = &vmstate_stellaris_enet; 509 } 510 511 static const TypeInfo stellaris_enet_info = { 512 .name = TYPE_STELLARIS_ENET, 513 .parent = TYPE_SYS_BUS_DEVICE, 514 .instance_size = sizeof(stellaris_enet_state), 515 .class_init = stellaris_enet_class_init, 516 }; 517 518 static void stellaris_enet_register_types(void) 519 { 520 type_register_static(&stellaris_enet_info); 521 } 522 523 type_init(stellaris_enet_register_types) 524