1 /** 2 * QEMU RTL8139 emulation 3 * 4 * Copyright (c) 2006 Igor Kovalenko 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 24 * Modifications: 25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver) 26 * 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver 28 * HW revision ID changes for FreeBSD driver 29 * 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver 31 * Corrected packet transfer reassembly routine for 8139C+ mode 32 * Rearranged debugging print statements 33 * Implemented PCI timer interrupt (disabled by default) 34 * Implemented Tally Counters, increased VM load/save version 35 * Implemented IP/TCP/UDP checksum task offloading 36 * 37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading 38 * Fixed MTU=1500 for produced ethernet frames 39 * 40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing 41 * segmentation offloading 42 * Removed slirp.h dependency 43 * Added rx/tx buffer reset when enabling rx/tx operation 44 * 45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only 46 * when strictly needed (required for 47 * Darwin) 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading 49 */ 50 51 /* For crc32 */ 52 53 #include "qemu/osdep.h" 54 #include <zlib.h> 55 56 #include "hw/pci/pci_device.h" 57 #include "hw/qdev-properties.h" 58 #include "migration/vmstate.h" 59 #include "sysemu/dma.h" 60 #include "qemu/module.h" 61 #include "qemu/timer.h" 62 #include "net/net.h" 63 #include "net/eth.h" 64 #include "sysemu/sysemu.h" 65 #include "qom/object.h" 66 67 /* debug RTL8139 card */ 68 //#define DEBUG_RTL8139 1 69 70 #define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */ 71 72 #define SET_MASKED(input, mask, curr) \ 73 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) 74 75 /* arg % size for size which is a power of 2 */ 76 #define MOD2(input, size) \ 77 ( ( input ) & ( size - 1 ) ) 78 79 #define ETHER_TYPE_LEN 2 80 81 #define VLAN_TCI_LEN 2 82 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) 83 84 #if defined (DEBUG_RTL8139) 85 # define DPRINTF(fmt, ...) \ 86 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) 87 #else 88 static inline G_GNUC_PRINTF(1, 2) int DPRINTF(const char *fmt, ...) 89 { 90 return 0; 91 } 92 #endif 93 94 #define TYPE_RTL8139 "rtl8139" 95 96 OBJECT_DECLARE_SIMPLE_TYPE(RTL8139State, RTL8139) 97 98 /* Symbolic offsets to registers. */ 99 enum RTL8139_registers { 100 MAC0 = 0, /* Ethernet hardware address. */ 101 MAR0 = 8, /* Multicast filter. */ 102 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ 103 /* Dump Tally Counter control register(64bit). C+ mode only */ 104 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 105 RxBuf = 0x30, 106 ChipCmd = 0x37, 107 RxBufPtr = 0x38, 108 RxBufAddr = 0x3A, 109 IntrMask = 0x3C, 110 IntrStatus = 0x3E, 111 TxConfig = 0x40, 112 RxConfig = 0x44, 113 Timer = 0x48, /* A general-purpose counter. */ 114 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 115 Cfg9346 = 0x50, 116 Config0 = 0x51, 117 Config1 = 0x52, 118 FlashReg = 0x54, 119 MediaStatus = 0x58, 120 Config3 = 0x59, 121 Config4 = 0x5A, /* absent on RTL-8139A */ 122 HltClk = 0x5B, 123 MultiIntr = 0x5C, 124 PCIRevisionID = 0x5E, 125 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ 126 BasicModeCtrl = 0x62, 127 BasicModeStatus = 0x64, 128 NWayAdvert = 0x66, 129 NWayLPAR = 0x68, 130 NWayExpansion = 0x6A, 131 /* Undocumented registers, but required for proper operation. */ 132 FIFOTMS = 0x70, /* FIFO Control and test. */ 133 CSCR = 0x74, /* Chip Status and Configuration Register. */ 134 PARA78 = 0x78, 135 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 136 Config5 = 0xD8, /* absent on RTL-8139A */ 137 /* C+ mode */ 138 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ 139 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ 140 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ 141 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ 142 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ 143 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ 144 TxThresh = 0xEC, /* Early Tx threshold */ 145 }; 146 147 enum ClearBitMasks { 148 MultiIntrClear = 0xF000, 149 ChipCmdClear = 0xE2, 150 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 151 }; 152 153 enum ChipCmdBits { 154 CmdReset = 0x10, 155 CmdRxEnb = 0x08, 156 CmdTxEnb = 0x04, 157 RxBufEmpty = 0x01, 158 }; 159 160 /* C+ mode */ 161 enum CplusCmdBits { 162 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ 163 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ 164 CPlusRxEnb = 0x0002, 165 CPlusTxEnb = 0x0001, 166 }; 167 168 /* Interrupt register bits, using my own meaningful names. */ 169 enum IntrStatusBits { 170 PCIErr = 0x8000, 171 PCSTimeout = 0x4000, 172 RxFIFOOver = 0x40, 173 RxUnderrun = 0x20, /* Packet Underrun / Link Change */ 174 RxOverflow = 0x10, 175 TxErr = 0x08, 176 TxOK = 0x04, 177 RxErr = 0x02, 178 RxOK = 0x01, 179 180 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 181 }; 182 183 enum TxStatusBits { 184 TxHostOwns = 0x2000, 185 TxUnderrun = 0x4000, 186 TxStatOK = 0x8000, 187 TxOutOfWindow = 0x20000000, 188 TxAborted = 0x40000000, 189 TxCarrierLost = 0x80000000, 190 }; 191 enum RxStatusBits { 192 RxMulticast = 0x8000, 193 RxPhysical = 0x4000, 194 RxBroadcast = 0x2000, 195 RxBadSymbol = 0x0020, 196 RxRunt = 0x0010, 197 RxTooLong = 0x0008, 198 RxCRCErr = 0x0004, 199 RxBadAlign = 0x0002, 200 RxStatusOK = 0x0001, 201 }; 202 203 /* Bits in RxConfig. */ 204 enum rx_mode_bits { 205 AcceptErr = 0x20, 206 AcceptRunt = 0x10, 207 AcceptBroadcast = 0x08, 208 AcceptMulticast = 0x04, 209 AcceptMyPhys = 0x02, 210 AcceptAllPhys = 0x01, 211 }; 212 213 /* Bits in TxConfig. */ 214 enum tx_config_bits { 215 216 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 217 TxIFGShift = 24, 218 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 219 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 220 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 221 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 222 223 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 224 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ 225 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 226 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ 227 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ 228 229 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 230 }; 231 232 233 /* Transmit Status of All Descriptors (TSAD) Register */ 234 enum TSAD_bits { 235 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 236 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 237 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 238 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 239 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 240 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 241 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 242 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 243 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 244 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 245 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 246 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 247 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 248 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 249 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 250 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 251 }; 252 253 254 /* Bits in Config1 */ 255 enum Config1Bits { 256 Cfg1_PM_Enable = 0x01, 257 Cfg1_VPD_Enable = 0x02, 258 Cfg1_PIO = 0x04, 259 Cfg1_MMIO = 0x08, 260 LWAKE = 0x10, /* not on 8139, 8139A */ 261 Cfg1_Driver_Load = 0x20, 262 Cfg1_LED0 = 0x40, 263 Cfg1_LED1 = 0x80, 264 SLEEP = (1 << 1), /* only on 8139, 8139A */ 265 PWRDN = (1 << 0), /* only on 8139, 8139A */ 266 }; 267 268 /* Bits in Config3 */ 269 enum Config3Bits { 270 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 271 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 272 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 273 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 274 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 275 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 276 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 277 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 278 }; 279 280 /* Bits in Config4 */ 281 enum Config4Bits { 282 LWPTN = (1 << 2), /* not on 8139, 8139A */ 283 }; 284 285 /* Bits in Config5 */ 286 enum Config5Bits { 287 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 288 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 289 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 290 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ 291 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 292 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 293 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 294 }; 295 296 enum RxConfigBits { 297 /* rx fifo threshold */ 298 RxCfgFIFOShift = 13, 299 RxCfgFIFONone = (7 << RxCfgFIFOShift), 300 301 /* Max DMA burst */ 302 RxCfgDMAShift = 8, 303 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 304 305 /* rx ring buffer length */ 306 RxCfgRcv8K = 0, 307 RxCfgRcv16K = (1 << 11), 308 RxCfgRcv32K = (1 << 12), 309 RxCfgRcv64K = (1 << 11) | (1 << 12), 310 311 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 312 RxNoWrap = (1 << 7), 313 }; 314 315 /* Twister tuning parameters from RealTek. 316 Completely undocumented, but required to tune bad links on some boards. */ 317 /* 318 enum CSCRBits { 319 CSCR_LinkOKBit = 0x0400, 320 CSCR_LinkChangeBit = 0x0800, 321 CSCR_LinkStatusBits = 0x0f000, 322 CSCR_LinkDownOffCmd = 0x003c0, 323 CSCR_LinkDownCmd = 0x0f3c0, 324 */ 325 enum CSCRBits { 326 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ 327 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ 328 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ 329 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ 330 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ 331 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ 332 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ 333 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ 334 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ 335 }; 336 337 enum Cfg9346Bits { 338 Cfg9346_Normal = 0x00, 339 Cfg9346_Autoload = 0x40, 340 Cfg9346_Programming = 0x80, 341 Cfg9346_ConfigWrite = 0xC0, 342 }; 343 344 typedef enum { 345 CH_8139 = 0, 346 CH_8139_K, 347 CH_8139A, 348 CH_8139A_G, 349 CH_8139B, 350 CH_8130, 351 CH_8139C, 352 CH_8100, 353 CH_8100B_8139D, 354 CH_8101, 355 } chip_t; 356 357 enum chip_flags { 358 HasHltClk = (1 << 0), 359 HasLWake = (1 << 1), 360 }; 361 362 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 363 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 364 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 365 366 #define RTL8139_PCI_REVID_8139 0x10 367 #define RTL8139_PCI_REVID_8139CPLUS 0x20 368 369 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS 370 371 /* Size is 64 * 16bit words */ 372 #define EEPROM_9346_ADDR_BITS 6 373 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) 374 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) 375 376 enum Chip9346Operation 377 { 378 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ 379 Chip9346_op_read = 0x80, /* 10 AAAAAA */ 380 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ 381 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ 382 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ 383 Chip9346_op_write_all = 0x10, /* 00 01zzzz */ 384 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ 385 }; 386 387 enum Chip9346Mode 388 { 389 Chip9346_none = 0, 390 Chip9346_enter_command_mode, 391 Chip9346_read_command, 392 Chip9346_data_read, /* from output register */ 393 Chip9346_data_write, /* to input register, then to contents at specified address */ 394 Chip9346_data_write_all, /* to input register, then filling contents */ 395 }; 396 397 typedef struct EEprom9346 398 { 399 uint16_t contents[EEPROM_9346_SIZE]; 400 int mode; 401 uint32_t tick; 402 uint8_t address; 403 uint16_t input; 404 uint16_t output; 405 406 uint8_t eecs; 407 uint8_t eesk; 408 uint8_t eedi; 409 uint8_t eedo; 410 } EEprom9346; 411 412 typedef struct RTL8139TallyCounters 413 { 414 /* Tally counters */ 415 uint64_t TxOk; 416 uint64_t RxOk; 417 uint64_t TxERR; 418 uint32_t RxERR; 419 uint16_t MissPkt; 420 uint16_t FAE; 421 uint32_t Tx1Col; 422 uint32_t TxMCol; 423 uint64_t RxOkPhy; 424 uint64_t RxOkBrd; 425 uint32_t RxOkMul; 426 uint16_t TxAbt; 427 uint16_t TxUndrn; 428 } RTL8139TallyCounters; 429 430 /* Clears all tally counters */ 431 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); 432 433 struct RTL8139State { 434 /*< private >*/ 435 PCIDevice parent_obj; 436 /*< public >*/ 437 438 uint8_t phys[8]; /* mac address */ 439 uint8_t mult[8]; /* multicast mask array */ 440 441 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ 442 uint32_t TxAddr[4]; /* TxAddr0 */ 443 uint32_t RxBuf; /* Receive buffer */ 444 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */ 445 uint32_t RxBufPtr; 446 uint32_t RxBufAddr; 447 448 uint16_t IntrStatus; 449 uint16_t IntrMask; 450 451 uint32_t TxConfig; 452 uint32_t RxConfig; 453 uint32_t RxMissed; 454 455 uint16_t CSCR; 456 457 uint8_t Cfg9346; 458 uint8_t Config0; 459 uint8_t Config1; 460 uint8_t Config3; 461 uint8_t Config4; 462 uint8_t Config5; 463 464 uint8_t clock_enabled; 465 uint8_t bChipCmdState; 466 467 uint16_t MultiIntr; 468 469 uint16_t BasicModeCtrl; 470 uint16_t BasicModeStatus; 471 uint16_t NWayAdvert; 472 uint16_t NWayLPAR; 473 uint16_t NWayExpansion; 474 475 uint16_t CpCmd; 476 uint8_t TxThresh; 477 478 NICState *nic; 479 NICConf conf; 480 481 /* C ring mode */ 482 uint32_t currTxDesc; 483 484 /* C+ mode */ 485 uint32_t cplus_enabled; 486 487 uint32_t currCPlusRxDesc; 488 uint32_t currCPlusTxDesc; 489 490 uint32_t RxRingAddrLO; 491 uint32_t RxRingAddrHI; 492 493 EEprom9346 eeprom; 494 495 uint32_t TCTR; 496 uint32_t TimerInt; 497 int64_t TCTR_base; 498 499 /* Tally counters */ 500 RTL8139TallyCounters tally_counters; 501 502 /* Non-persistent data */ 503 uint8_t *cplus_txbuffer; 504 int cplus_txbuffer_len; 505 int cplus_txbuffer_offset; 506 507 /* PCI interrupt timer */ 508 QEMUTimer *timer; 509 510 MemoryRegion bar_io; 511 MemoryRegion bar_mem; 512 513 /* Support migration to/from old versions */ 514 int rtl8139_mmio_io_addr_dummy; 515 }; 516 517 /* Writes tally counters to memory via DMA */ 518 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr); 519 520 static void rtl8139_set_next_tctr_time(RTL8139State *s); 521 522 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) 523 { 524 DPRINTF("eeprom command 0x%02x\n", command); 525 526 switch (command & Chip9346_op_mask) 527 { 528 case Chip9346_op_read: 529 { 530 eeprom->address = command & EEPROM_9346_ADDR_MASK; 531 eeprom->output = eeprom->contents[eeprom->address]; 532 eeprom->eedo = 0; 533 eeprom->tick = 0; 534 eeprom->mode = Chip9346_data_read; 535 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", 536 eeprom->address, eeprom->output); 537 } 538 break; 539 540 case Chip9346_op_write: 541 { 542 eeprom->address = command & EEPROM_9346_ADDR_MASK; 543 eeprom->input = 0; 544 eeprom->tick = 0; 545 eeprom->mode = Chip9346_none; /* Chip9346_data_write */ 546 DPRINTF("eeprom begin write to address 0x%02x\n", 547 eeprom->address); 548 } 549 break; 550 default: 551 eeprom->mode = Chip9346_none; 552 switch (command & Chip9346_op_ext_mask) 553 { 554 case Chip9346_op_write_enable: 555 DPRINTF("eeprom write enabled\n"); 556 break; 557 case Chip9346_op_write_all: 558 DPRINTF("eeprom begin write all\n"); 559 break; 560 case Chip9346_op_write_disable: 561 DPRINTF("eeprom write disabled\n"); 562 break; 563 } 564 break; 565 } 566 } 567 568 static void prom9346_shift_clock(EEprom9346 *eeprom) 569 { 570 int bit = eeprom->eedi?1:0; 571 572 ++ eeprom->tick; 573 574 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, 575 eeprom->eedo); 576 577 switch (eeprom->mode) 578 { 579 case Chip9346_enter_command_mode: 580 if (bit) 581 { 582 eeprom->mode = Chip9346_read_command; 583 eeprom->tick = 0; 584 eeprom->input = 0; 585 DPRINTF("eeprom: +++ synchronized, begin command read\n"); 586 } 587 break; 588 589 case Chip9346_read_command: 590 eeprom->input = (eeprom->input << 1) | (bit & 1); 591 if (eeprom->tick == 8) 592 { 593 prom9346_decode_command(eeprom, eeprom->input & 0xff); 594 } 595 break; 596 597 case Chip9346_data_read: 598 eeprom->eedo = (eeprom->output & 0x8000)?1:0; 599 eeprom->output <<= 1; 600 if (eeprom->tick == 16) 601 { 602 #if 1 603 // the FreeBSD drivers (rl and re) don't explicitly toggle 604 // CS between reads (or does setting Cfg9346 to 0 count too?), 605 // so we need to enter wait-for-command state here 606 eeprom->mode = Chip9346_enter_command_mode; 607 eeprom->input = 0; 608 eeprom->tick = 0; 609 610 DPRINTF("eeprom: +++ end of read, awaiting next command\n"); 611 #else 612 // original behaviour 613 ++eeprom->address; 614 eeprom->address &= EEPROM_9346_ADDR_MASK; 615 eeprom->output = eeprom->contents[eeprom->address]; 616 eeprom->tick = 0; 617 618 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", 619 eeprom->address, eeprom->output); 620 #endif 621 } 622 break; 623 624 case Chip9346_data_write: 625 eeprom->input = (eeprom->input << 1) | (bit & 1); 626 if (eeprom->tick == 16) 627 { 628 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n", 629 eeprom->address, eeprom->input); 630 631 eeprom->contents[eeprom->address] = eeprom->input; 632 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ 633 eeprom->tick = 0; 634 eeprom->input = 0; 635 } 636 break; 637 638 case Chip9346_data_write_all: 639 eeprom->input = (eeprom->input << 1) | (bit & 1); 640 if (eeprom->tick == 16) 641 { 642 int i; 643 for (i = 0; i < EEPROM_9346_SIZE; i++) 644 { 645 eeprom->contents[i] = eeprom->input; 646 } 647 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); 648 649 eeprom->mode = Chip9346_enter_command_mode; 650 eeprom->tick = 0; 651 eeprom->input = 0; 652 } 653 break; 654 655 default: 656 break; 657 } 658 } 659 660 static int prom9346_get_wire(RTL8139State *s) 661 { 662 EEprom9346 *eeprom = &s->eeprom; 663 if (!eeprom->eecs) 664 return 0; 665 666 return eeprom->eedo; 667 } 668 669 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */ 670 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) 671 { 672 EEprom9346 *eeprom = &s->eeprom; 673 uint8_t old_eecs = eeprom->eecs; 674 uint8_t old_eesk = eeprom->eesk; 675 676 eeprom->eecs = eecs; 677 eeprom->eesk = eesk; 678 eeprom->eedi = eedi; 679 680 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, 681 eeprom->eesk, eeprom->eedi, eeprom->eedo); 682 683 if (!old_eecs && eecs) 684 { 685 /* Synchronize start */ 686 eeprom->tick = 0; 687 eeprom->input = 0; 688 eeprom->output = 0; 689 eeprom->mode = Chip9346_enter_command_mode; 690 691 DPRINTF("=== eeprom: begin access, enter command mode\n"); 692 } 693 694 if (!eecs) 695 { 696 DPRINTF("=== eeprom: end access\n"); 697 return; 698 } 699 700 if (!old_eesk && eesk) 701 { 702 /* SK front rules */ 703 prom9346_shift_clock(eeprom); 704 } 705 } 706 707 static void rtl8139_update_irq(RTL8139State *s) 708 { 709 PCIDevice *d = PCI_DEVICE(s); 710 int isr; 711 isr = (s->IntrStatus & s->IntrMask) & 0xffff; 712 713 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, 714 s->IntrMask); 715 716 pci_set_irq(d, (isr != 0)); 717 } 718 719 static int rtl8139_RxWrap(RTL8139State *s) 720 { 721 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */ 722 return (s->RxConfig & (1 << 7)); 723 } 724 725 static int rtl8139_receiver_enabled(RTL8139State *s) 726 { 727 return s->bChipCmdState & CmdRxEnb; 728 } 729 730 static int rtl8139_transmitter_enabled(RTL8139State *s) 731 { 732 return s->bChipCmdState & CmdTxEnb; 733 } 734 735 static int rtl8139_cp_receiver_enabled(RTL8139State *s) 736 { 737 return s->CpCmd & CPlusRxEnb; 738 } 739 740 static int rtl8139_cp_transmitter_enabled(RTL8139State *s) 741 { 742 return s->CpCmd & CPlusTxEnb; 743 } 744 745 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) 746 { 747 PCIDevice *d = PCI_DEVICE(s); 748 749 if (s->RxBufAddr + size > s->RxBufferSize) 750 { 751 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); 752 753 /* write packet data */ 754 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) 755 { 756 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped); 757 758 if (size > wrapped) 759 { 760 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 761 buf, size-wrapped); 762 } 763 764 /* reset buffer pointer */ 765 s->RxBufAddr = 0; 766 767 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 768 buf + (size-wrapped), wrapped); 769 770 s->RxBufAddr = wrapped; 771 772 return; 773 } 774 } 775 776 /* non-wrapping path or overwrapping enabled */ 777 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size); 778 779 s->RxBufAddr += size; 780 } 781 782 #define MIN_BUF_SIZE 60 783 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high) 784 { 785 return low | ((uint64_t)high << 32); 786 } 787 788 /* Workaround for buggy guest driver such as linux who allocates rx 789 * rings after the receiver were enabled. */ 790 static bool rtl8139_cp_rx_valid(RTL8139State *s) 791 { 792 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0); 793 } 794 795 static bool rtl8139_can_receive(NetClientState *nc) 796 { 797 RTL8139State *s = qemu_get_nic_opaque(nc); 798 int avail; 799 800 /* Receive (drop) packets if card is disabled. */ 801 if (!s->clock_enabled) { 802 return true; 803 } 804 if (!rtl8139_receiver_enabled(s)) { 805 return true; 806 } 807 808 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) { 809 /* ??? Flow control not implemented in c+ mode. 810 This is a hack to work around slirp deficiencies anyway. */ 811 return true; 812 } 813 814 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, 815 s->RxBufferSize); 816 return avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow); 817 } 818 819 static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) 820 { 821 RTL8139State *s = qemu_get_nic_opaque(nc); 822 PCIDevice *d = PCI_DEVICE(s); 823 /* size is the length of the buffer passed to the driver */ 824 size_t size = size_; 825 const uint8_t *dot1q_buf = NULL; 826 827 uint32_t packet_header = 0; 828 829 static const uint8_t broadcast_macaddr[6] = 830 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 831 832 DPRINTF(">>> received len=%zu\n", size); 833 834 /* test if board clock is stopped */ 835 if (!s->clock_enabled) 836 { 837 DPRINTF("stopped ==========================\n"); 838 return -1; 839 } 840 841 /* first check if receiver is enabled */ 842 843 if (!rtl8139_receiver_enabled(s)) 844 { 845 DPRINTF("receiver disabled ================\n"); 846 return -1; 847 } 848 849 /* XXX: check this */ 850 if (s->RxConfig & AcceptAllPhys) { 851 /* promiscuous: receive all */ 852 DPRINTF(">>> packet received in promiscuous mode\n"); 853 854 } else { 855 if (!memcmp(buf, broadcast_macaddr, 6)) { 856 /* broadcast address */ 857 if (!(s->RxConfig & AcceptBroadcast)) 858 { 859 DPRINTF(">>> broadcast packet rejected\n"); 860 861 /* update tally counter */ 862 ++s->tally_counters.RxERR; 863 864 return size; 865 } 866 867 packet_header |= RxBroadcast; 868 869 DPRINTF(">>> broadcast packet received\n"); 870 871 /* update tally counter */ 872 ++s->tally_counters.RxOkBrd; 873 874 } else if (buf[0] & 0x01) { 875 /* multicast */ 876 if (!(s->RxConfig & AcceptMulticast)) 877 { 878 DPRINTF(">>> multicast packet rejected\n"); 879 880 /* update tally counter */ 881 ++s->tally_counters.RxERR; 882 883 return size; 884 } 885 886 int mcast_idx = net_crc32(buf, ETH_ALEN) >> 26; 887 888 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) 889 { 890 DPRINTF(">>> multicast address mismatch\n"); 891 892 /* update tally counter */ 893 ++s->tally_counters.RxERR; 894 895 return size; 896 } 897 898 packet_header |= RxMulticast; 899 900 DPRINTF(">>> multicast packet received\n"); 901 902 /* update tally counter */ 903 ++s->tally_counters.RxOkMul; 904 905 } else if (s->phys[0] == buf[0] && 906 s->phys[1] == buf[1] && 907 s->phys[2] == buf[2] && 908 s->phys[3] == buf[3] && 909 s->phys[4] == buf[4] && 910 s->phys[5] == buf[5]) { 911 /* match */ 912 if (!(s->RxConfig & AcceptMyPhys)) 913 { 914 DPRINTF(">>> rejecting physical address matching packet\n"); 915 916 /* update tally counter */ 917 ++s->tally_counters.RxERR; 918 919 return size; 920 } 921 922 packet_header |= RxPhysical; 923 924 DPRINTF(">>> physical address matching packet received\n"); 925 926 /* update tally counter */ 927 ++s->tally_counters.RxOkPhy; 928 929 } else { 930 931 DPRINTF(">>> unknown packet\n"); 932 933 /* update tally counter */ 934 ++s->tally_counters.RxERR; 935 936 return size; 937 } 938 } 939 940 if (rtl8139_cp_receiver_enabled(s)) 941 { 942 if (!rtl8139_cp_rx_valid(s)) { 943 return size; 944 } 945 946 DPRINTF("in C+ Rx mode ================\n"); 947 948 /* begin C+ receiver mode */ 949 950 /* w0 ownership flag */ 951 #define CP_RX_OWN (1<<31) 952 /* w0 end of ring flag */ 953 #define CP_RX_EOR (1<<30) 954 /* w0 bits 0...12 : buffer size */ 955 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) 956 /* w1 tag available flag */ 957 #define CP_RX_TAVA (1<<16) 958 /* w1 bits 0...15 : VLAN tag */ 959 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) 960 /* w2 low 32bit of Rx buffer ptr */ 961 /* w3 high 32bit of Rx buffer ptr */ 962 963 int descriptor = s->currCPlusRxDesc; 964 dma_addr_t cplus_rx_ring_desc; 965 966 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); 967 cplus_rx_ring_desc += 16 * descriptor; 968 969 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at " 970 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI, 971 s->RxRingAddrLO, cplus_rx_ring_desc); 972 973 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; 974 975 pci_dma_read(d, cplus_rx_ring_desc, &val, 4); 976 rxdw0 = le32_to_cpu(val); 977 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4); 978 rxdw1 = le32_to_cpu(val); 979 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4); 980 rxbufLO = le32_to_cpu(val); 981 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4); 982 rxbufHI = le32_to_cpu(val); 983 984 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", 985 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); 986 987 if (!(rxdw0 & CP_RX_OWN)) 988 { 989 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n", 990 descriptor); 991 992 s->IntrStatus |= RxOverflow; 993 ++s->RxMissed; 994 995 /* update tally counter */ 996 ++s->tally_counters.RxERR; 997 ++s->tally_counters.MissPkt; 998 999 rtl8139_update_irq(s); 1000 return size_; 1001 } 1002 1003 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; 1004 1005 /* write VLAN info to descriptor variables. */ 1006 if (s->CpCmd & CPlusRxVLAN && 1007 lduw_be_p(&buf[ETH_ALEN * 2]) == ETH_P_VLAN) { 1008 dot1q_buf = &buf[ETH_ALEN * 2]; 1009 size -= VLAN_HLEN; 1010 /* if too small buffer, use the tailroom added duing expansion */ 1011 if (size < MIN_BUF_SIZE) { 1012 size = MIN_BUF_SIZE; 1013 } 1014 1015 rxdw1 &= ~CP_RX_VLAN_TAG_MASK; 1016 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */ 1017 rxdw1 |= CP_RX_TAVA | lduw_le_p(&dot1q_buf[ETHER_TYPE_LEN]); 1018 1019 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", 1020 lduw_be_p(&dot1q_buf[ETHER_TYPE_LEN])); 1021 } else { 1022 /* reset VLAN tag flag */ 1023 rxdw1 &= ~CP_RX_TAVA; 1024 } 1025 1026 /* TODO: scatter the packet over available receive ring descriptors space */ 1027 1028 if (size+4 > rx_space) 1029 { 1030 DPRINTF("C+ Rx mode : descriptor %d size %d received %zu + 4\n", 1031 descriptor, rx_space, size); 1032 1033 s->IntrStatus |= RxOverflow; 1034 ++s->RxMissed; 1035 1036 /* update tally counter */ 1037 ++s->tally_counters.RxERR; 1038 ++s->tally_counters.MissPkt; 1039 1040 rtl8139_update_irq(s); 1041 return size_; 1042 } 1043 1044 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); 1045 1046 /* receive/copy to target memory */ 1047 if (dot1q_buf) { 1048 pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN); 1049 pci_dma_write(d, rx_addr + 2 * ETH_ALEN, 1050 buf + 2 * ETH_ALEN + VLAN_HLEN, 1051 size - 2 * ETH_ALEN); 1052 } else { 1053 pci_dma_write(d, rx_addr, buf, size); 1054 } 1055 1056 if (s->CpCmd & CPlusRxChkSum) 1057 { 1058 /* do some packet checksumming */ 1059 } 1060 1061 /* write checksum */ 1062 val = cpu_to_le32(crc32(0, buf, size_)); 1063 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4); 1064 1065 /* first segment of received packet flag */ 1066 #define CP_RX_STATUS_FS (1<<29) 1067 /* last segment of received packet flag */ 1068 #define CP_RX_STATUS_LS (1<<28) 1069 /* multicast packet flag */ 1070 #define CP_RX_STATUS_MAR (1<<26) 1071 /* physical-matching packet flag */ 1072 #define CP_RX_STATUS_PAM (1<<25) 1073 /* broadcast packet flag */ 1074 #define CP_RX_STATUS_BAR (1<<24) 1075 /* runt packet flag */ 1076 #define CP_RX_STATUS_RUNT (1<<19) 1077 /* crc error flag */ 1078 #define CP_RX_STATUS_CRC (1<<18) 1079 /* IP checksum error flag */ 1080 #define CP_RX_STATUS_IPF (1<<15) 1081 /* UDP checksum error flag */ 1082 #define CP_RX_STATUS_UDPF (1<<14) 1083 /* TCP checksum error flag */ 1084 #define CP_RX_STATUS_TCPF (1<<13) 1085 1086 /* transfer ownership to target */ 1087 rxdw0 &= ~CP_RX_OWN; 1088 1089 /* set first segment bit */ 1090 rxdw0 |= CP_RX_STATUS_FS; 1091 1092 /* set last segment bit */ 1093 rxdw0 |= CP_RX_STATUS_LS; 1094 1095 /* set received packet type flags */ 1096 if (packet_header & RxBroadcast) 1097 rxdw0 |= CP_RX_STATUS_BAR; 1098 if (packet_header & RxMulticast) 1099 rxdw0 |= CP_RX_STATUS_MAR; 1100 if (packet_header & RxPhysical) 1101 rxdw0 |= CP_RX_STATUS_PAM; 1102 1103 /* set received size */ 1104 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; 1105 rxdw0 |= (size+4); 1106 1107 /* update ring data */ 1108 val = cpu_to_le32(rxdw0); 1109 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4); 1110 val = cpu_to_le32(rxdw1); 1111 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4); 1112 1113 /* update tally counter */ 1114 ++s->tally_counters.RxOk; 1115 1116 /* seek to next Rx descriptor */ 1117 if (rxdw0 & CP_RX_EOR) 1118 { 1119 s->currCPlusRxDesc = 0; 1120 } 1121 else 1122 { 1123 ++s->currCPlusRxDesc; 1124 } 1125 1126 DPRINTF("done C+ Rx mode ----------------\n"); 1127 1128 } 1129 else 1130 { 1131 DPRINTF("in ring Rx mode ================\n"); 1132 1133 /* begin ring receiver mode */ 1134 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); 1135 1136 /* if receiver buffer is empty then avail == 0 */ 1137 1138 #define RX_ALIGN(x) (((x) + 3) & ~0x3) 1139 1140 if (avail != 0 && RX_ALIGN(size + 8) >= avail) 1141 { 1142 DPRINTF("rx overflow: rx buffer length %d head 0x%04x " 1143 "read 0x%04x === available 0x%04x need 0x%04zx\n", 1144 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); 1145 1146 s->IntrStatus |= RxOverflow; 1147 ++s->RxMissed; 1148 rtl8139_update_irq(s); 1149 return 0; 1150 } 1151 1152 packet_header |= RxStatusOK; 1153 1154 packet_header |= (((size+4) << 16) & 0xffff0000); 1155 1156 /* write header */ 1157 uint32_t val = cpu_to_le32(packet_header); 1158 1159 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1160 1161 rtl8139_write_buffer(s, buf, size); 1162 1163 /* write checksum */ 1164 val = cpu_to_le32(crc32(0, buf, size)); 1165 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1166 1167 /* correct buffer write pointer */ 1168 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize); 1169 1170 /* now we can signal we have received something */ 1171 1172 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n", 1173 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 1174 } 1175 1176 s->IntrStatus |= RxOK; 1177 1178 if (do_interrupt) 1179 { 1180 rtl8139_update_irq(s); 1181 } 1182 1183 return size_; 1184 } 1185 1186 static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1187 { 1188 return rtl8139_do_receive(nc, buf, size, 1); 1189 } 1190 1191 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) 1192 { 1193 s->RxBufferSize = bufferSize; 1194 s->RxBufPtr = 0; 1195 s->RxBufAddr = 0; 1196 } 1197 1198 static void rtl8139_reset_phy(RTL8139State *s) 1199 { 1200 s->BasicModeStatus = 0x7809; 1201 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ 1202 /* preserve link state */ 1203 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04; 1204 1205 s->NWayAdvert = 0x05e1; /* all modes, full duplex */ 1206 s->NWayLPAR = 0x05e1; /* all modes, full duplex */ 1207 s->NWayExpansion = 0x0001; /* autonegotiation supported */ 1208 1209 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; 1210 } 1211 1212 static void rtl8139_reset(DeviceState *d) 1213 { 1214 RTL8139State *s = RTL8139(d); 1215 int i; 1216 1217 /* restore MAC address */ 1218 memcpy(s->phys, s->conf.macaddr.a, 6); 1219 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 1220 1221 /* reset interrupt mask */ 1222 s->IntrStatus = 0; 1223 s->IntrMask = 0; 1224 1225 rtl8139_update_irq(s); 1226 1227 /* mark all status registers as owned by host */ 1228 for (i = 0; i < 4; ++i) 1229 { 1230 s->TxStatus[i] = TxHostOwns; 1231 } 1232 1233 s->currTxDesc = 0; 1234 s->currCPlusRxDesc = 0; 1235 s->currCPlusTxDesc = 0; 1236 1237 s->RxRingAddrLO = 0; 1238 s->RxRingAddrHI = 0; 1239 1240 s->RxBuf = 0; 1241 1242 rtl8139_reset_rxring(s, 8192); 1243 1244 /* ACK the reset */ 1245 s->TxConfig = 0; 1246 1247 #if 0 1248 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk 1249 s->clock_enabled = 0; 1250 #else 1251 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake 1252 s->clock_enabled = 1; 1253 #endif 1254 1255 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; 1256 1257 /* set initial state data */ 1258 s->Config0 = 0x0; /* No boot ROM */ 1259 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ 1260 s->Config3 = 0x1; /* fast back-to-back compatible */ 1261 s->Config5 = 0x0; 1262 1263 s->CpCmd = 0x0; /* reset C+ mode */ 1264 s->cplus_enabled = 0; 1265 1266 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation 1267 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex 1268 s->BasicModeCtrl = 0x1000; // autonegotiation 1269 1270 rtl8139_reset_phy(s); 1271 1272 /* also reset timer and disable timer interrupt */ 1273 s->TCTR = 0; 1274 s->TimerInt = 0; 1275 s->TCTR_base = 0; 1276 rtl8139_set_next_tctr_time(s); 1277 1278 /* reset tally counters */ 1279 RTL8139TallyCounters_clear(&s->tally_counters); 1280 } 1281 1282 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) 1283 { 1284 counters->TxOk = 0; 1285 counters->RxOk = 0; 1286 counters->TxERR = 0; 1287 counters->RxERR = 0; 1288 counters->MissPkt = 0; 1289 counters->FAE = 0; 1290 counters->Tx1Col = 0; 1291 counters->TxMCol = 0; 1292 counters->RxOkPhy = 0; 1293 counters->RxOkBrd = 0; 1294 counters->RxOkMul = 0; 1295 counters->TxAbt = 0; 1296 counters->TxUndrn = 0; 1297 } 1298 1299 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr) 1300 { 1301 PCIDevice *d = PCI_DEVICE(s); 1302 RTL8139TallyCounters *tally_counters = &s->tally_counters; 1303 uint16_t val16; 1304 uint32_t val32; 1305 uint64_t val64; 1306 1307 val64 = cpu_to_le64(tally_counters->TxOk); 1308 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8); 1309 1310 val64 = cpu_to_le64(tally_counters->RxOk); 1311 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8); 1312 1313 val64 = cpu_to_le64(tally_counters->TxERR); 1314 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8); 1315 1316 val32 = cpu_to_le32(tally_counters->RxERR); 1317 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4); 1318 1319 val16 = cpu_to_le16(tally_counters->MissPkt); 1320 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2); 1321 1322 val16 = cpu_to_le16(tally_counters->FAE); 1323 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2); 1324 1325 val32 = cpu_to_le32(tally_counters->Tx1Col); 1326 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4); 1327 1328 val32 = cpu_to_le32(tally_counters->TxMCol); 1329 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4); 1330 1331 val64 = cpu_to_le64(tally_counters->RxOkPhy); 1332 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8); 1333 1334 val64 = cpu_to_le64(tally_counters->RxOkBrd); 1335 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8); 1336 1337 val32 = cpu_to_le32(tally_counters->RxOkMul); 1338 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4); 1339 1340 val16 = cpu_to_le16(tally_counters->TxAbt); 1341 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2); 1342 1343 val16 = cpu_to_le16(tally_counters->TxUndrn); 1344 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2); 1345 } 1346 1347 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) 1348 { 1349 DeviceState *d = DEVICE(s); 1350 1351 val &= 0xff; 1352 1353 DPRINTF("ChipCmd write val=0x%08x\n", val); 1354 1355 if (val & CmdReset) 1356 { 1357 DPRINTF("ChipCmd reset\n"); 1358 rtl8139_reset(d); 1359 } 1360 if (val & CmdRxEnb) 1361 { 1362 DPRINTF("ChipCmd enable receiver\n"); 1363 1364 s->currCPlusRxDesc = 0; 1365 } 1366 if (val & CmdTxEnb) 1367 { 1368 DPRINTF("ChipCmd enable transmitter\n"); 1369 1370 s->currCPlusTxDesc = 0; 1371 } 1372 1373 /* mask unwritable bits */ 1374 val = SET_MASKED(val, 0xe3, s->bChipCmdState); 1375 1376 /* Deassert reset pin before next read */ 1377 val &= ~CmdReset; 1378 1379 s->bChipCmdState = val; 1380 } 1381 1382 static int rtl8139_RxBufferEmpty(RTL8139State *s) 1383 { 1384 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); 1385 1386 if (unread != 0) 1387 { 1388 DPRINTF("receiver buffer data available 0x%04x\n", unread); 1389 return 0; 1390 } 1391 1392 DPRINTF("receiver buffer is empty\n"); 1393 1394 return 1; 1395 } 1396 1397 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s) 1398 { 1399 uint32_t ret = s->bChipCmdState; 1400 1401 if (rtl8139_RxBufferEmpty(s)) 1402 ret |= RxBufEmpty; 1403 1404 DPRINTF("ChipCmd read val=0x%04x\n", ret); 1405 1406 return ret; 1407 } 1408 1409 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) 1410 { 1411 val &= 0xffff; 1412 1413 DPRINTF("C+ command register write(w) val=0x%04x\n", val); 1414 1415 s->cplus_enabled = 1; 1416 1417 /* mask unwritable bits */ 1418 val = SET_MASKED(val, 0xff84, s->CpCmd); 1419 1420 s->CpCmd = val; 1421 } 1422 1423 static uint32_t rtl8139_CpCmd_read(RTL8139State *s) 1424 { 1425 uint32_t ret = s->CpCmd; 1426 1427 DPRINTF("C+ command register read(w) val=0x%04x\n", ret); 1428 1429 return ret; 1430 } 1431 1432 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) 1433 { 1434 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val); 1435 } 1436 1437 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s) 1438 { 1439 uint32_t ret = 0; 1440 1441 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret); 1442 1443 return ret; 1444 } 1445 1446 static int rtl8139_config_writable(RTL8139State *s) 1447 { 1448 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite) 1449 { 1450 return 1; 1451 } 1452 1453 DPRINTF("Configuration registers are write-protected\n"); 1454 1455 return 0; 1456 } 1457 1458 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) 1459 { 1460 val &= 0xffff; 1461 1462 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val); 1463 1464 /* mask unwritable bits */ 1465 uint32_t mask = 0xccff; 1466 1467 if (1 || !rtl8139_config_writable(s)) 1468 { 1469 /* Speed setting and autonegotiation enable bits are read-only */ 1470 mask |= 0x3000; 1471 /* Duplex mode setting is read-only */ 1472 mask |= 0x0100; 1473 } 1474 1475 if (val & 0x8000) { 1476 /* Reset PHY */ 1477 rtl8139_reset_phy(s); 1478 } 1479 1480 val = SET_MASKED(val, mask, s->BasicModeCtrl); 1481 1482 s->BasicModeCtrl = val; 1483 } 1484 1485 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s) 1486 { 1487 uint32_t ret = s->BasicModeCtrl; 1488 1489 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret); 1490 1491 return ret; 1492 } 1493 1494 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) 1495 { 1496 val &= 0xffff; 1497 1498 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val); 1499 1500 /* mask unwritable bits */ 1501 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); 1502 1503 s->BasicModeStatus = val; 1504 } 1505 1506 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s) 1507 { 1508 uint32_t ret = s->BasicModeStatus; 1509 1510 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret); 1511 1512 return ret; 1513 } 1514 1515 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) 1516 { 1517 DeviceState *d = DEVICE(s); 1518 1519 val &= 0xff; 1520 1521 DPRINTF("Cfg9346 write val=0x%02x\n", val); 1522 1523 /* mask unwritable bits */ 1524 val = SET_MASKED(val, 0x31, s->Cfg9346); 1525 1526 uint32_t opmode = val & 0xc0; 1527 uint32_t eeprom_val = val & 0xf; 1528 1529 if (opmode == 0x80) { 1530 /* eeprom access */ 1531 int eecs = (eeprom_val & 0x08)?1:0; 1532 int eesk = (eeprom_val & 0x04)?1:0; 1533 int eedi = (eeprom_val & 0x02)?1:0; 1534 prom9346_set_wire(s, eecs, eesk, eedi); 1535 } else if (opmode == 0x40) { 1536 /* Reset. */ 1537 val = 0; 1538 rtl8139_reset(d); 1539 } 1540 1541 s->Cfg9346 = val; 1542 } 1543 1544 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s) 1545 { 1546 uint32_t ret = s->Cfg9346; 1547 1548 uint32_t opmode = ret & 0xc0; 1549 1550 if (opmode == 0x80) 1551 { 1552 /* eeprom access */ 1553 int eedo = prom9346_get_wire(s); 1554 if (eedo) 1555 { 1556 ret |= 0x01; 1557 } 1558 else 1559 { 1560 ret &= ~0x01; 1561 } 1562 } 1563 1564 DPRINTF("Cfg9346 read val=0x%02x\n", ret); 1565 1566 return ret; 1567 } 1568 1569 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) 1570 { 1571 val &= 0xff; 1572 1573 DPRINTF("Config0 write val=0x%02x\n", val); 1574 1575 if (!rtl8139_config_writable(s)) { 1576 return; 1577 } 1578 1579 /* mask unwritable bits */ 1580 val = SET_MASKED(val, 0xf8, s->Config0); 1581 1582 s->Config0 = val; 1583 } 1584 1585 static uint32_t rtl8139_Config0_read(RTL8139State *s) 1586 { 1587 uint32_t ret = s->Config0; 1588 1589 DPRINTF("Config0 read val=0x%02x\n", ret); 1590 1591 return ret; 1592 } 1593 1594 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) 1595 { 1596 val &= 0xff; 1597 1598 DPRINTF("Config1 write val=0x%02x\n", val); 1599 1600 if (!rtl8139_config_writable(s)) { 1601 return; 1602 } 1603 1604 /* mask unwritable bits */ 1605 val = SET_MASKED(val, 0xC, s->Config1); 1606 1607 s->Config1 = val; 1608 } 1609 1610 static uint32_t rtl8139_Config1_read(RTL8139State *s) 1611 { 1612 uint32_t ret = s->Config1; 1613 1614 DPRINTF("Config1 read val=0x%02x\n", ret); 1615 1616 return ret; 1617 } 1618 1619 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) 1620 { 1621 val &= 0xff; 1622 1623 DPRINTF("Config3 write val=0x%02x\n", val); 1624 1625 if (!rtl8139_config_writable(s)) { 1626 return; 1627 } 1628 1629 /* mask unwritable bits */ 1630 val = SET_MASKED(val, 0x8F, s->Config3); 1631 1632 s->Config3 = val; 1633 } 1634 1635 static uint32_t rtl8139_Config3_read(RTL8139State *s) 1636 { 1637 uint32_t ret = s->Config3; 1638 1639 DPRINTF("Config3 read val=0x%02x\n", ret); 1640 1641 return ret; 1642 } 1643 1644 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) 1645 { 1646 val &= 0xff; 1647 1648 DPRINTF("Config4 write val=0x%02x\n", val); 1649 1650 if (!rtl8139_config_writable(s)) { 1651 return; 1652 } 1653 1654 /* mask unwritable bits */ 1655 val = SET_MASKED(val, 0x0a, s->Config4); 1656 1657 s->Config4 = val; 1658 } 1659 1660 static uint32_t rtl8139_Config4_read(RTL8139State *s) 1661 { 1662 uint32_t ret = s->Config4; 1663 1664 DPRINTF("Config4 read val=0x%02x\n", ret); 1665 1666 return ret; 1667 } 1668 1669 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) 1670 { 1671 val &= 0xff; 1672 1673 DPRINTF("Config5 write val=0x%02x\n", val); 1674 1675 /* mask unwritable bits */ 1676 val = SET_MASKED(val, 0x80, s->Config5); 1677 1678 s->Config5 = val; 1679 } 1680 1681 static uint32_t rtl8139_Config5_read(RTL8139State *s) 1682 { 1683 uint32_t ret = s->Config5; 1684 1685 DPRINTF("Config5 read val=0x%02x\n", ret); 1686 1687 return ret; 1688 } 1689 1690 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) 1691 { 1692 if (!rtl8139_transmitter_enabled(s)) 1693 { 1694 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val); 1695 return; 1696 } 1697 1698 DPRINTF("TxConfig write val=0x%08x\n", val); 1699 1700 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); 1701 1702 s->TxConfig = val; 1703 } 1704 1705 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) 1706 { 1707 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val); 1708 1709 uint32_t tc = s->TxConfig; 1710 tc &= 0xFFFFFF00; 1711 tc |= (val & 0x000000FF); 1712 rtl8139_TxConfig_write(s, tc); 1713 } 1714 1715 static uint32_t rtl8139_TxConfig_read(RTL8139State *s) 1716 { 1717 uint32_t ret = s->TxConfig; 1718 1719 DPRINTF("TxConfig read val=0x%04x\n", ret); 1720 1721 return ret; 1722 } 1723 1724 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) 1725 { 1726 DPRINTF("RxConfig write val=0x%08x\n", val); 1727 1728 /* mask unwritable bits */ 1729 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); 1730 1731 s->RxConfig = val; 1732 1733 /* reset buffer size and read/write pointers */ 1734 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); 1735 1736 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize); 1737 } 1738 1739 static uint32_t rtl8139_RxConfig_read(RTL8139State *s) 1740 { 1741 uint32_t ret = s->RxConfig; 1742 1743 DPRINTF("RxConfig read val=0x%08x\n", ret); 1744 1745 return ret; 1746 } 1747 1748 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, 1749 int do_interrupt, const uint8_t *dot1q_buf) 1750 { 1751 struct iovec *iov = NULL; 1752 struct iovec vlan_iov[3]; 1753 1754 if (!size) 1755 { 1756 DPRINTF("+++ empty ethernet frame\n"); 1757 return; 1758 } 1759 1760 if (dot1q_buf && size >= ETH_ALEN * 2) { 1761 iov = (struct iovec[3]) { 1762 { .iov_base = buf, .iov_len = ETH_ALEN * 2 }, 1763 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN }, 1764 { .iov_base = buf + ETH_ALEN * 2, 1765 .iov_len = size - ETH_ALEN * 2 }, 1766 }; 1767 1768 memcpy(vlan_iov, iov, sizeof(vlan_iov)); 1769 iov = vlan_iov; 1770 } 1771 1772 if (TxLoopBack == (s->TxConfig & TxLoopBack)) 1773 { 1774 size_t buf2_size; 1775 uint8_t *buf2; 1776 1777 if (iov) { 1778 buf2_size = iov_size(iov, 3); 1779 buf2 = g_malloc(buf2_size); 1780 iov_to_buf(iov, 3, 0, buf2, buf2_size); 1781 buf = buf2; 1782 } 1783 1784 DPRINTF("+++ transmit loopback mode\n"); 1785 qemu_receive_packet(qemu_get_queue(s->nic), buf, size); 1786 1787 if (iov) { 1788 g_free(buf2); 1789 } 1790 } 1791 else 1792 { 1793 if (iov) { 1794 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3); 1795 } else { 1796 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 1797 } 1798 } 1799 } 1800 1801 static int rtl8139_transmit_one(RTL8139State *s, int descriptor) 1802 { 1803 if (!rtl8139_transmitter_enabled(s)) 1804 { 1805 DPRINTF("+++ cannot transmit from descriptor %d: transmitter " 1806 "disabled\n", descriptor); 1807 return 0; 1808 } 1809 1810 if (s->TxStatus[descriptor] & TxHostOwns) 1811 { 1812 DPRINTF("+++ cannot transmit from descriptor %d: owned by host " 1813 "(%08x)\n", descriptor, s->TxStatus[descriptor]); 1814 return 0; 1815 } 1816 1817 DPRINTF("+++ transmitting from descriptor %d\n", descriptor); 1818 1819 PCIDevice *d = PCI_DEVICE(s); 1820 int txsize = s->TxStatus[descriptor] & 0x1fff; 1821 uint8_t txbuffer[0x2000]; 1822 1823 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n", 1824 txsize, s->TxAddr[descriptor]); 1825 1826 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize); 1827 1828 /* Mark descriptor as transferred */ 1829 s->TxStatus[descriptor] |= TxHostOwns; 1830 s->TxStatus[descriptor] |= TxStatOK; 1831 1832 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); 1833 1834 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize, 1835 descriptor); 1836 1837 /* update interrupt */ 1838 s->IntrStatus |= TxOK; 1839 rtl8139_update_irq(s); 1840 1841 return 1; 1842 } 1843 1844 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off))) 1845 1846 /* produces ones' complement sum of data */ 1847 static uint16_t ones_complement_sum(uint8_t *data, size_t len) 1848 { 1849 uint32_t result = 0; 1850 1851 for (; len > 1; data+=2, len-=2) 1852 { 1853 result += *(uint16_t*)data; 1854 } 1855 1856 /* add the remainder byte */ 1857 if (len) 1858 { 1859 uint8_t odd[2] = {*data, 0}; 1860 result += *(uint16_t*)odd; 1861 } 1862 1863 while (result>>16) 1864 result = (result & 0xffff) + (result >> 16); 1865 1866 return result; 1867 } 1868 1869 static uint16_t ip_checksum(void *data, size_t len) 1870 { 1871 return ~ones_complement_sum((uint8_t*)data, len); 1872 } 1873 1874 static int rtl8139_cplus_transmit_one(RTL8139State *s) 1875 { 1876 if (!rtl8139_transmitter_enabled(s)) 1877 { 1878 DPRINTF("+++ C+ mode: transmitter disabled\n"); 1879 return 0; 1880 } 1881 1882 if (!rtl8139_cp_transmitter_enabled(s)) 1883 { 1884 DPRINTF("+++ C+ mode: C+ transmitter disabled\n"); 1885 return 0 ; 1886 } 1887 1888 PCIDevice *d = PCI_DEVICE(s); 1889 int descriptor = s->currCPlusTxDesc; 1890 1891 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); 1892 1893 /* Normal priority ring */ 1894 cplus_tx_ring_desc += 16 * descriptor; 1895 1896 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at " 1897 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], 1898 s->TxAddr[0], cplus_tx_ring_desc); 1899 1900 uint32_t val, txdw0,txdw1,txbufLO,txbufHI; 1901 1902 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 1903 txdw0 = le32_to_cpu(val); 1904 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4); 1905 txdw1 = le32_to_cpu(val); 1906 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4); 1907 txbufLO = le32_to_cpu(val); 1908 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4); 1909 txbufHI = le32_to_cpu(val); 1910 1911 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor, 1912 txdw0, txdw1, txbufLO, txbufHI); 1913 1914 /* w0 ownership flag */ 1915 #define CP_TX_OWN (1<<31) 1916 /* w0 end of ring flag */ 1917 #define CP_TX_EOR (1<<30) 1918 /* first segment of received packet flag */ 1919 #define CP_TX_FS (1<<29) 1920 /* last segment of received packet flag */ 1921 #define CP_TX_LS (1<<28) 1922 /* large send packet flag */ 1923 #define CP_TX_LGSEN (1<<27) 1924 /* large send MSS mask, bits 16...26 */ 1925 #define CP_TC_LGSEN_MSS_SHIFT 16 1926 #define CP_TC_LGSEN_MSS_MASK ((1 << 11) - 1) 1927 1928 /* IP checksum offload flag */ 1929 #define CP_TX_IPCS (1<<18) 1930 /* UDP checksum offload flag */ 1931 #define CP_TX_UDPCS (1<<17) 1932 /* TCP checksum offload flag */ 1933 #define CP_TX_TCPCS (1<<16) 1934 1935 /* w0 bits 0...15 : buffer size */ 1936 #define CP_TX_BUFFER_SIZE (1<<16) 1937 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) 1938 /* w1 add tag flag */ 1939 #define CP_TX_TAGC (1<<17) 1940 /* w1 bits 0...15 : VLAN tag (big endian) */ 1941 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) 1942 /* w2 low 32bit of Rx buffer ptr */ 1943 /* w3 high 32bit of Rx buffer ptr */ 1944 1945 /* set after transmission */ 1946 /* FIFO underrun flag */ 1947 #define CP_TX_STATUS_UNF (1<<25) 1948 /* transmit error summary flag, valid if set any of three below */ 1949 #define CP_TX_STATUS_TES (1<<23) 1950 /* out-of-window collision flag */ 1951 #define CP_TX_STATUS_OWC (1<<22) 1952 /* link failure flag */ 1953 #define CP_TX_STATUS_LNKF (1<<21) 1954 /* excessive collisions flag */ 1955 #define CP_TX_STATUS_EXC (1<<20) 1956 1957 if (!(txdw0 & CP_TX_OWN)) 1958 { 1959 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor); 1960 return 0 ; 1961 } 1962 1963 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor); 1964 1965 if (txdw0 & CP_TX_FS) 1966 { 1967 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment " 1968 "descriptor\n", descriptor); 1969 1970 /* reset internal buffer offset */ 1971 s->cplus_txbuffer_offset = 0; 1972 } 1973 1974 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; 1975 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); 1976 1977 /* make sure we have enough space to assemble the packet */ 1978 if (!s->cplus_txbuffer) 1979 { 1980 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; 1981 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len); 1982 s->cplus_txbuffer_offset = 0; 1983 1984 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n", 1985 s->cplus_txbuffer_len); 1986 } 1987 1988 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) 1989 { 1990 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */ 1991 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; 1992 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor" 1993 "length to %d\n", txsize); 1994 } 1995 1996 /* append more data to the packet */ 1997 1998 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at " 1999 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr, 2000 s->cplus_txbuffer_offset); 2001 2002 pci_dma_read(d, tx_addr, 2003 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); 2004 s->cplus_txbuffer_offset += txsize; 2005 2006 /* seek to next Rx descriptor */ 2007 if (txdw0 & CP_TX_EOR) 2008 { 2009 s->currCPlusTxDesc = 0; 2010 } 2011 else 2012 { 2013 ++s->currCPlusTxDesc; 2014 if (s->currCPlusTxDesc >= 64) 2015 s->currCPlusTxDesc = 0; 2016 } 2017 2018 /* Build the Tx Status Descriptor */ 2019 uint32_t tx_status = txdw0; 2020 2021 /* transfer ownership to target */ 2022 tx_status &= ~CP_TX_OWN; 2023 2024 /* reset error indicator bits */ 2025 tx_status &= ~CP_TX_STATUS_UNF; 2026 tx_status &= ~CP_TX_STATUS_TES; 2027 tx_status &= ~CP_TX_STATUS_OWC; 2028 tx_status &= ~CP_TX_STATUS_LNKF; 2029 tx_status &= ~CP_TX_STATUS_EXC; 2030 2031 /* update ring data */ 2032 val = cpu_to_le32(tx_status); 2033 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 2034 2035 /* Now decide if descriptor being processed is holding the last segment of packet */ 2036 if (txdw0 & CP_TX_LS) 2037 { 2038 uint8_t dot1q_buffer_space[VLAN_HLEN]; 2039 uint16_t *dot1q_buffer; 2040 2041 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n", 2042 descriptor); 2043 2044 /* can transfer fully assembled packet */ 2045 2046 uint8_t *saved_buffer = s->cplus_txbuffer; 2047 int saved_size = s->cplus_txbuffer_offset; 2048 int saved_buffer_len = s->cplus_txbuffer_len; 2049 2050 /* create vlan tag */ 2051 if (txdw1 & CP_TX_TAGC) { 2052 /* the vlan tag is in BE byte order in the descriptor 2053 * BE + le_to_cpu() + ~swap()~ = cpu */ 2054 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", 2055 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); 2056 2057 dot1q_buffer = (uint16_t *) dot1q_buffer_space; 2058 dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN); 2059 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */ 2060 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK); 2061 } else { 2062 dot1q_buffer = NULL; 2063 } 2064 2065 /* reset the card space to protect from recursive call */ 2066 s->cplus_txbuffer = NULL; 2067 s->cplus_txbuffer_offset = 0; 2068 s->cplus_txbuffer_len = 0; 2069 2070 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) 2071 { 2072 DPRINTF("+++ C+ mode offloaded task checksum\n"); 2073 2074 /* Large enough for Ethernet and IP headers? */ 2075 if (saved_size < ETH_HLEN + sizeof(struct ip_header)) { 2076 goto skip_offload; 2077 } 2078 2079 /* ip packet header */ 2080 struct ip_header *ip = NULL; 2081 int hlen = 0; 2082 uint8_t ip_protocol = 0; 2083 uint16_t ip_data_len = 0; 2084 2085 uint8_t *eth_payload_data = NULL; 2086 size_t eth_payload_len = 0; 2087 2088 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); 2089 if (proto != ETH_P_IP) 2090 { 2091 goto skip_offload; 2092 } 2093 2094 DPRINTF("+++ C+ mode has IP packet\n"); 2095 2096 /* Note on memory alignment: eth_payload_data is 16-bit aligned 2097 * since saved_buffer is allocated with g_malloc() and ETH_HLEN is 2098 * even. 32-bit accesses must use ldl/stl wrappers to avoid 2099 * unaligned accesses. 2100 */ 2101 eth_payload_data = saved_buffer + ETH_HLEN; 2102 eth_payload_len = saved_size - ETH_HLEN; 2103 2104 ip = (struct ip_header*)eth_payload_data; 2105 2106 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) { 2107 DPRINTF("+++ C+ mode packet has bad IP version %d " 2108 "expected %d\n", IP_HEADER_VERSION(ip), 2109 IP_HEADER_VERSION_4); 2110 goto skip_offload; 2111 } 2112 2113 hlen = IP_HDR_GET_LEN(ip); 2114 if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) { 2115 goto skip_offload; 2116 } 2117 2118 ip_protocol = ip->ip_p; 2119 2120 ip_data_len = be16_to_cpu(ip->ip_len); 2121 if (ip_data_len < hlen || ip_data_len > eth_payload_len) { 2122 goto skip_offload; 2123 } 2124 ip_data_len -= hlen; 2125 2126 if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & CP_TX_IPCS)) 2127 { 2128 DPRINTF("+++ C+ mode need IP checksum\n"); 2129 2130 ip->ip_sum = 0; 2131 ip->ip_sum = ip_checksum(ip, hlen); 2132 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n", 2133 hlen, ip->ip_sum); 2134 } 2135 2136 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) 2137 { 2138 /* Large enough for the TCP header? */ 2139 if (ip_data_len < sizeof(tcp_header)) { 2140 goto skip_offload; 2141 } 2142 2143 int large_send_mss = (txdw0 >> CP_TC_LGSEN_MSS_SHIFT) & 2144 CP_TC_LGSEN_MSS_MASK; 2145 if (large_send_mss == 0) { 2146 goto skip_offload; 2147 } 2148 2149 DPRINTF("+++ C+ mode offloaded task TSO IP data %d " 2150 "frame data %d specified MSS=%d\n", 2151 ip_data_len, saved_size - ETH_HLEN, large_send_mss); 2152 2153 int tcp_send_offset = 0; 2154 2155 /* maximum IP header length is 60 bytes */ 2156 uint8_t saved_ip_header[60]; 2157 2158 /* save IP header template; data area is used in tcp checksum calculation */ 2159 memcpy(saved_ip_header, eth_payload_data, hlen); 2160 2161 /* a placeholder for checksum calculation routine in tcp case */ 2162 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2163 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2164 2165 /* pointer to TCP header */ 2166 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); 2167 2168 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr); 2169 2170 /* Invalid TCP data offset? */ 2171 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) { 2172 goto skip_offload; 2173 } 2174 2175 int tcp_data_len = ip_data_len - tcp_hlen; 2176 2177 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP " 2178 "data len %d\n", ip_data_len, tcp_hlen, tcp_data_len); 2179 2180 /* note the cycle below overwrites IP header data, 2181 but restores it from saved_ip_header before sending packet */ 2182 2183 int is_last_frame = 0; 2184 2185 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += large_send_mss) 2186 { 2187 uint16_t chunk_size = large_send_mss; 2188 2189 /* check if this is the last frame */ 2190 if (tcp_send_offset + large_send_mss >= tcp_data_len) 2191 { 2192 is_last_frame = 1; 2193 chunk_size = tcp_data_len - tcp_send_offset; 2194 } 2195 2196 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n", 2197 ldl_be_p(&p_tcp_hdr->th_seq)); 2198 2199 /* add 4 TCP pseudoheader fields */ 2200 /* copy IP source and destination fields */ 2201 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2202 2203 DPRINTF("+++ C+ mode TSO calculating TCP checksum for " 2204 "packet with %d bytes data\n", tcp_hlen + 2205 chunk_size); 2206 2207 if (tcp_send_offset) 2208 { 2209 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); 2210 } 2211 2212 /* keep PUSH and FIN flags only for the last frame */ 2213 if (!is_last_frame) 2214 { 2215 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN); 2216 } 2217 2218 /* recalculate TCP checksum */ 2219 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2220 p_tcpip_hdr->zeros = 0; 2221 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2222 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); 2223 2224 p_tcp_hdr->th_sum = 0; 2225 2226 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); 2227 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n", 2228 tcp_checksum); 2229 2230 p_tcp_hdr->th_sum = tcp_checksum; 2231 2232 /* restore IP header */ 2233 memcpy(eth_payload_data, saved_ip_header, hlen); 2234 2235 /* set IP data length and recalculate IP checksum */ 2236 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); 2237 2238 /* increment IP id for subsequent frames */ 2239 ip->ip_id = cpu_to_be16(tcp_send_offset/large_send_mss + be16_to_cpu(ip->ip_id)); 2240 2241 ip->ip_sum = 0; 2242 ip->ip_sum = ip_checksum(eth_payload_data, hlen); 2243 DPRINTF("+++ C+ mode TSO IP header len=%d " 2244 "checksum=%04x\n", hlen, ip->ip_sum); 2245 2246 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size; 2247 DPRINTF("+++ C+ mode TSO transferring packet size " 2248 "%d\n", tso_send_size); 2249 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 2250 0, (uint8_t *) dot1q_buffer); 2251 2252 /* add transferred count to TCP sequence number */ 2253 stl_be_p(&p_tcp_hdr->th_seq, 2254 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq)); 2255 } 2256 2257 /* Stop sending this frame */ 2258 saved_size = 0; 2259 } 2260 else if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))) 2261 { 2262 DPRINTF("+++ C+ mode need TCP or UDP checksum\n"); 2263 2264 /* maximum IP header length is 60 bytes */ 2265 uint8_t saved_ip_header[60]; 2266 memcpy(saved_ip_header, eth_payload_data, hlen); 2267 2268 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2269 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2270 2271 /* add 4 TCP pseudoheader fields */ 2272 /* copy IP source and destination fields */ 2273 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2274 2275 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) 2276 { 2277 DPRINTF("+++ C+ mode calculating TCP checksum for " 2278 "packet with %d bytes data\n", ip_data_len); 2279 2280 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2281 p_tcpip_hdr->zeros = 0; 2282 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2283 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2284 2285 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12); 2286 2287 p_tcp_hdr->th_sum = 0; 2288 2289 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2290 DPRINTF("+++ C+ mode TCP checksum %04x\n", 2291 tcp_checksum); 2292 2293 p_tcp_hdr->th_sum = tcp_checksum; 2294 } 2295 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) 2296 { 2297 DPRINTF("+++ C+ mode calculating UDP checksum for " 2298 "packet with %d bytes data\n", ip_data_len); 2299 2300 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; 2301 p_udpip_hdr->zeros = 0; 2302 p_udpip_hdr->ip_proto = IP_PROTO_UDP; 2303 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2304 2305 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12); 2306 2307 p_udp_hdr->uh_sum = 0; 2308 2309 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2310 DPRINTF("+++ C+ mode UDP checksum %04x\n", 2311 udp_checksum); 2312 2313 p_udp_hdr->uh_sum = udp_checksum; 2314 } 2315 2316 /* restore IP header */ 2317 memcpy(eth_payload_data, saved_ip_header, hlen); 2318 } 2319 } 2320 2321 skip_offload: 2322 /* update tally counter */ 2323 ++s->tally_counters.TxOk; 2324 2325 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size); 2326 2327 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1, 2328 (uint8_t *) dot1q_buffer); 2329 2330 /* restore card space if there was no recursion and reset offset */ 2331 if (!s->cplus_txbuffer) 2332 { 2333 s->cplus_txbuffer = saved_buffer; 2334 s->cplus_txbuffer_len = saved_buffer_len; 2335 s->cplus_txbuffer_offset = 0; 2336 } 2337 else 2338 { 2339 g_free(saved_buffer); 2340 } 2341 } 2342 else 2343 { 2344 DPRINTF("+++ C+ mode transmission continue to next descriptor\n"); 2345 } 2346 2347 return 1; 2348 } 2349 2350 static void rtl8139_cplus_transmit(RTL8139State *s) 2351 { 2352 int txcount = 0; 2353 2354 while (txcount < 64 && rtl8139_cplus_transmit_one(s)) 2355 { 2356 ++txcount; 2357 } 2358 2359 /* Mark transfer completed */ 2360 if (!txcount) 2361 { 2362 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n", 2363 s->currCPlusTxDesc); 2364 } 2365 else 2366 { 2367 /* update interrupt status */ 2368 s->IntrStatus |= TxOK; 2369 rtl8139_update_irq(s); 2370 } 2371 } 2372 2373 static void rtl8139_transmit(RTL8139State *s) 2374 { 2375 int descriptor = s->currTxDesc, txcount = 0; 2376 2377 /*while*/ 2378 if (rtl8139_transmit_one(s, descriptor)) 2379 { 2380 ++s->currTxDesc; 2381 s->currTxDesc %= 4; 2382 ++txcount; 2383 } 2384 2385 /* Mark transfer completed */ 2386 if (!txcount) 2387 { 2388 DPRINTF("transmitter queue stalled, current TxDesc = %d\n", 2389 s->currTxDesc); 2390 } 2391 } 2392 2393 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) 2394 { 2395 2396 int descriptor = txRegOffset/4; 2397 2398 /* handle C+ transmit mode register configuration */ 2399 2400 if (s->cplus_enabled) 2401 { 2402 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x " 2403 "descriptor=%d\n", txRegOffset, val, descriptor); 2404 2405 /* handle Dump Tally Counters command */ 2406 s->TxStatus[descriptor] = val; 2407 2408 if (descriptor == 0 && (val & 0x8)) 2409 { 2410 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); 2411 2412 /* dump tally counters to specified memory location */ 2413 RTL8139TallyCounters_dma_write(s, tc_addr); 2414 2415 /* mark dump completed */ 2416 s->TxStatus[0] &= ~0x8; 2417 } 2418 2419 return; 2420 } 2421 2422 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", 2423 txRegOffset, val, descriptor); 2424 2425 /* mask only reserved bits */ 2426 val &= ~0xff00c000; /* these bits are reset on write */ 2427 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); 2428 2429 s->TxStatus[descriptor] = val; 2430 2431 /* attempt to start transmission */ 2432 rtl8139_transmit(s); 2433 } 2434 2435 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[], 2436 uint32_t base, uint8_t addr, 2437 int size) 2438 { 2439 uint32_t reg = (addr - base) / 4; 2440 uint32_t offset = addr & 0x3; 2441 uint32_t ret = 0; 2442 2443 if (addr & (size - 1)) { 2444 DPRINTF("not implemented read for TxStatus/TxAddr " 2445 "addr=0x%x size=0x%x\n", addr, size); 2446 return ret; 2447 } 2448 2449 switch (size) { 2450 case 1: /* fall through */ 2451 case 2: /* fall through */ 2452 case 4: 2453 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1); 2454 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n", 2455 reg, addr, size, ret); 2456 break; 2457 default: 2458 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size); 2459 break; 2460 } 2461 2462 return ret; 2463 } 2464 2465 static uint16_t rtl8139_TSAD_read(RTL8139State *s) 2466 { 2467 uint16_t ret = 0; 2468 2469 /* Simulate TSAD, it is read only anyway */ 2470 2471 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) 2472 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) 2473 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) 2474 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) 2475 2476 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) 2477 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) 2478 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) 2479 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) 2480 2481 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) 2482 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) 2483 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) 2484 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) 2485 2486 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) 2487 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) 2488 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) 2489 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; 2490 2491 2492 DPRINTF("TSAD read val=0x%04x\n", ret); 2493 2494 return ret; 2495 } 2496 2497 static uint16_t rtl8139_CSCR_read(RTL8139State *s) 2498 { 2499 uint16_t ret = s->CSCR; 2500 2501 DPRINTF("CSCR read val=0x%04x\n", ret); 2502 2503 return ret; 2504 } 2505 2506 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) 2507 { 2508 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val); 2509 2510 s->TxAddr[txAddrOffset/4] = val; 2511 } 2512 2513 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) 2514 { 2515 uint32_t ret = s->TxAddr[txAddrOffset/4]; 2516 2517 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret); 2518 2519 return ret; 2520 } 2521 2522 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) 2523 { 2524 DPRINTF("RxBufPtr write val=0x%04x\n", val); 2525 2526 /* this value is off by 16 */ 2527 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); 2528 2529 /* more buffer space may be available so try to receive */ 2530 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 2531 2532 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", 2533 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 2534 } 2535 2536 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s) 2537 { 2538 /* this value is off by 16 */ 2539 uint32_t ret = s->RxBufPtr - 0x10; 2540 2541 DPRINTF("RxBufPtr read val=0x%04x\n", ret); 2542 2543 return ret; 2544 } 2545 2546 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s) 2547 { 2548 /* this value is NOT off by 16 */ 2549 uint32_t ret = s->RxBufAddr; 2550 2551 DPRINTF("RxBufAddr read val=0x%04x\n", ret); 2552 2553 return ret; 2554 } 2555 2556 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) 2557 { 2558 DPRINTF("RxBuf write val=0x%08x\n", val); 2559 2560 s->RxBuf = val; 2561 2562 /* may need to reset rxring here */ 2563 } 2564 2565 static uint32_t rtl8139_RxBuf_read(RTL8139State *s) 2566 { 2567 uint32_t ret = s->RxBuf; 2568 2569 DPRINTF("RxBuf read val=0x%08x\n", ret); 2570 2571 return ret; 2572 } 2573 2574 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) 2575 { 2576 DPRINTF("IntrMask write(w) val=0x%04x\n", val); 2577 2578 /* mask unwritable bits */ 2579 val = SET_MASKED(val, 0x1e00, s->IntrMask); 2580 2581 s->IntrMask = val; 2582 2583 rtl8139_update_irq(s); 2584 2585 } 2586 2587 static uint32_t rtl8139_IntrMask_read(RTL8139State *s) 2588 { 2589 uint32_t ret = s->IntrMask; 2590 2591 DPRINTF("IntrMask read(w) val=0x%04x\n", ret); 2592 2593 return ret; 2594 } 2595 2596 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) 2597 { 2598 DPRINTF("IntrStatus write(w) val=0x%04x\n", val); 2599 2600 #if 0 2601 2602 /* writing to ISR has no effect */ 2603 2604 return; 2605 2606 #else 2607 uint16_t newStatus = s->IntrStatus & ~val; 2608 2609 /* mask unwritable bits */ 2610 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); 2611 2612 /* writing 1 to interrupt status register bit clears it */ 2613 s->IntrStatus = 0; 2614 rtl8139_update_irq(s); 2615 2616 s->IntrStatus = newStatus; 2617 rtl8139_set_next_tctr_time(s); 2618 rtl8139_update_irq(s); 2619 2620 #endif 2621 } 2622 2623 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) 2624 { 2625 uint32_t ret = s->IntrStatus; 2626 2627 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret); 2628 2629 #if 0 2630 2631 /* reading ISR clears all interrupts */ 2632 s->IntrStatus = 0; 2633 2634 rtl8139_update_irq(s); 2635 2636 #endif 2637 2638 return ret; 2639 } 2640 2641 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) 2642 { 2643 DPRINTF("MultiIntr write(w) val=0x%04x\n", val); 2644 2645 /* mask unwritable bits */ 2646 val = SET_MASKED(val, 0xf000, s->MultiIntr); 2647 2648 s->MultiIntr = val; 2649 } 2650 2651 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s) 2652 { 2653 uint32_t ret = s->MultiIntr; 2654 2655 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret); 2656 2657 return ret; 2658 } 2659 2660 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) 2661 { 2662 RTL8139State *s = opaque; 2663 2664 switch (addr) 2665 { 2666 case MAC0 ... MAC0+4: 2667 s->phys[addr - MAC0] = val; 2668 break; 2669 case MAC0+5: 2670 s->phys[addr - MAC0] = val; 2671 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 2672 break; 2673 case MAC0+6 ... MAC0+7: 2674 /* reserved */ 2675 break; 2676 case MAR0 ... MAR0+7: 2677 s->mult[addr - MAR0] = val; 2678 break; 2679 case ChipCmd: 2680 rtl8139_ChipCmd_write(s, val); 2681 break; 2682 case Cfg9346: 2683 rtl8139_Cfg9346_write(s, val); 2684 break; 2685 case TxConfig: /* windows driver sometimes writes using byte-lenth call */ 2686 rtl8139_TxConfig_writeb(s, val); 2687 break; 2688 case Config0: 2689 rtl8139_Config0_write(s, val); 2690 break; 2691 case Config1: 2692 rtl8139_Config1_write(s, val); 2693 break; 2694 case Config3: 2695 rtl8139_Config3_write(s, val); 2696 break; 2697 case Config4: 2698 rtl8139_Config4_write(s, val); 2699 break; 2700 case Config5: 2701 rtl8139_Config5_write(s, val); 2702 break; 2703 case MediaStatus: 2704 /* ignore */ 2705 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n", 2706 val); 2707 break; 2708 2709 case HltClk: 2710 DPRINTF("HltClk write val=0x%08x\n", val); 2711 if (val == 'R') 2712 { 2713 s->clock_enabled = 1; 2714 } 2715 else if (val == 'H') 2716 { 2717 s->clock_enabled = 0; 2718 } 2719 break; 2720 2721 case TxThresh: 2722 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val); 2723 s->TxThresh = val; 2724 break; 2725 2726 case TxPoll: 2727 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val); 2728 if (val & (1 << 7)) 2729 { 2730 DPRINTF("C+ TxPoll high priority transmission (not " 2731 "implemented)\n"); 2732 //rtl8139_cplus_transmit(s); 2733 } 2734 if (val & (1 << 6)) 2735 { 2736 DPRINTF("C+ TxPoll normal priority transmission\n"); 2737 rtl8139_cplus_transmit(s); 2738 } 2739 2740 break; 2741 2742 default: 2743 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr, 2744 val); 2745 break; 2746 } 2747 } 2748 2749 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) 2750 { 2751 RTL8139State *s = opaque; 2752 2753 switch (addr) 2754 { 2755 case IntrMask: 2756 rtl8139_IntrMask_write(s, val); 2757 break; 2758 2759 case IntrStatus: 2760 rtl8139_IntrStatus_write(s, val); 2761 break; 2762 2763 case MultiIntr: 2764 rtl8139_MultiIntr_write(s, val); 2765 break; 2766 2767 case RxBufPtr: 2768 rtl8139_RxBufPtr_write(s, val); 2769 break; 2770 2771 case BasicModeCtrl: 2772 rtl8139_BasicModeCtrl_write(s, val); 2773 break; 2774 case BasicModeStatus: 2775 rtl8139_BasicModeStatus_write(s, val); 2776 break; 2777 case NWayAdvert: 2778 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val); 2779 s->NWayAdvert = val; 2780 break; 2781 case NWayLPAR: 2782 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val); 2783 break; 2784 case NWayExpansion: 2785 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val); 2786 s->NWayExpansion = val; 2787 break; 2788 2789 case CpCmd: 2790 rtl8139_CpCmd_write(s, val); 2791 break; 2792 2793 case IntrMitigate: 2794 rtl8139_IntrMitigate_write(s, val); 2795 break; 2796 2797 default: 2798 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n", 2799 addr, val); 2800 2801 rtl8139_io_writeb(opaque, addr, val & 0xff); 2802 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2803 break; 2804 } 2805 } 2806 2807 static void rtl8139_set_next_tctr_time(RTL8139State *s) 2808 { 2809 const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32; 2810 2811 DPRINTF("entered rtl8139_set_next_tctr_time\n"); 2812 2813 /* This function is called at least once per period, so it is a good 2814 * place to update the timer base. 2815 * 2816 * After one iteration of this loop the value in the Timer register does 2817 * not change, but the device model is counting up by 2^32 ticks (approx. 2818 * 130 seconds). 2819 */ 2820 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2821 s->TCTR_base += ns_per_period; 2822 } 2823 2824 if (!s->TimerInt) { 2825 timer_del(s->timer); 2826 } else { 2827 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD; 2828 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2829 delta += ns_per_period; 2830 } 2831 timer_mod(s->timer, s->TCTR_base + delta); 2832 } 2833 } 2834 2835 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) 2836 { 2837 RTL8139State *s = opaque; 2838 2839 switch (addr) 2840 { 2841 case RxMissed: 2842 DPRINTF("RxMissed clearing on write\n"); 2843 s->RxMissed = 0; 2844 break; 2845 2846 case TxConfig: 2847 rtl8139_TxConfig_write(s, val); 2848 break; 2849 2850 case RxConfig: 2851 rtl8139_RxConfig_write(s, val); 2852 break; 2853 2854 case TxStatus0 ... TxStatus0+4*4-1: 2855 rtl8139_TxStatus_write(s, addr-TxStatus0, val); 2856 break; 2857 2858 case TxAddr0 ... TxAddr0+4*4-1: 2859 rtl8139_TxAddr_write(s, addr-TxAddr0, val); 2860 break; 2861 2862 case RxBuf: 2863 rtl8139_RxBuf_write(s, val); 2864 break; 2865 2866 case RxRingAddrLO: 2867 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val); 2868 s->RxRingAddrLO = val; 2869 break; 2870 2871 case RxRingAddrHI: 2872 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val); 2873 s->RxRingAddrHI = val; 2874 break; 2875 2876 case Timer: 2877 DPRINTF("TCTR Timer reset on write\n"); 2878 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2879 rtl8139_set_next_tctr_time(s); 2880 break; 2881 2882 case FlashReg: 2883 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val); 2884 if (s->TimerInt != val) { 2885 s->TimerInt = val; 2886 rtl8139_set_next_tctr_time(s); 2887 } 2888 break; 2889 2890 default: 2891 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n", 2892 addr, val); 2893 rtl8139_io_writeb(opaque, addr, val & 0xff); 2894 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2895 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); 2896 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); 2897 break; 2898 } 2899 } 2900 2901 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) 2902 { 2903 RTL8139State *s = opaque; 2904 int ret; 2905 2906 switch (addr) 2907 { 2908 case MAC0 ... MAC0+5: 2909 ret = s->phys[addr - MAC0]; 2910 break; 2911 case MAC0+6 ... MAC0+7: 2912 ret = 0; 2913 break; 2914 case MAR0 ... MAR0+7: 2915 ret = s->mult[addr - MAR0]; 2916 break; 2917 case TxStatus0 ... TxStatus0+4*4-1: 2918 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 2919 addr, 1); 2920 break; 2921 case ChipCmd: 2922 ret = rtl8139_ChipCmd_read(s); 2923 break; 2924 case Cfg9346: 2925 ret = rtl8139_Cfg9346_read(s); 2926 break; 2927 case Config0: 2928 ret = rtl8139_Config0_read(s); 2929 break; 2930 case Config1: 2931 ret = rtl8139_Config1_read(s); 2932 break; 2933 case Config3: 2934 ret = rtl8139_Config3_read(s); 2935 break; 2936 case Config4: 2937 ret = rtl8139_Config4_read(s); 2938 break; 2939 case Config5: 2940 ret = rtl8139_Config5_read(s); 2941 break; 2942 2943 case MediaStatus: 2944 /* The LinkDown bit of MediaStatus is inverse with link status */ 2945 ret = 0xd0 | (~s->BasicModeStatus & 0x04); 2946 DPRINTF("MediaStatus read 0x%x\n", ret); 2947 break; 2948 2949 case HltClk: 2950 ret = s->clock_enabled; 2951 DPRINTF("HltClk read 0x%x\n", ret); 2952 break; 2953 2954 case PCIRevisionID: 2955 ret = RTL8139_PCI_REVID; 2956 DPRINTF("PCI Revision ID read 0x%x\n", ret); 2957 break; 2958 2959 case TxThresh: 2960 ret = s->TxThresh; 2961 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret); 2962 break; 2963 2964 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ 2965 ret = s->TxConfig >> 24; 2966 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret); 2967 break; 2968 2969 default: 2970 DPRINTF("not implemented read(b) addr=0x%x\n", addr); 2971 ret = 0; 2972 break; 2973 } 2974 2975 return ret; 2976 } 2977 2978 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) 2979 { 2980 RTL8139State *s = opaque; 2981 uint32_t ret; 2982 2983 switch (addr) 2984 { 2985 case TxAddr0 ... TxAddr0+4*4-1: 2986 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2); 2987 break; 2988 case IntrMask: 2989 ret = rtl8139_IntrMask_read(s); 2990 break; 2991 2992 case IntrStatus: 2993 ret = rtl8139_IntrStatus_read(s); 2994 break; 2995 2996 case MultiIntr: 2997 ret = rtl8139_MultiIntr_read(s); 2998 break; 2999 3000 case RxBufPtr: 3001 ret = rtl8139_RxBufPtr_read(s); 3002 break; 3003 3004 case RxBufAddr: 3005 ret = rtl8139_RxBufAddr_read(s); 3006 break; 3007 3008 case BasicModeCtrl: 3009 ret = rtl8139_BasicModeCtrl_read(s); 3010 break; 3011 case BasicModeStatus: 3012 ret = rtl8139_BasicModeStatus_read(s); 3013 break; 3014 case NWayAdvert: 3015 ret = s->NWayAdvert; 3016 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret); 3017 break; 3018 case NWayLPAR: 3019 ret = s->NWayLPAR; 3020 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret); 3021 break; 3022 case NWayExpansion: 3023 ret = s->NWayExpansion; 3024 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret); 3025 break; 3026 3027 case CpCmd: 3028 ret = rtl8139_CpCmd_read(s); 3029 break; 3030 3031 case IntrMitigate: 3032 ret = rtl8139_IntrMitigate_read(s); 3033 break; 3034 3035 case TxSummary: 3036 ret = rtl8139_TSAD_read(s); 3037 break; 3038 3039 case CSCR: 3040 ret = rtl8139_CSCR_read(s); 3041 break; 3042 3043 default: 3044 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr); 3045 3046 ret = rtl8139_io_readb(opaque, addr); 3047 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3048 3049 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret); 3050 break; 3051 } 3052 3053 return ret; 3054 } 3055 3056 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) 3057 { 3058 RTL8139State *s = opaque; 3059 uint32_t ret; 3060 3061 switch (addr) 3062 { 3063 case RxMissed: 3064 ret = s->RxMissed; 3065 3066 DPRINTF("RxMissed read val=0x%08x\n", ret); 3067 break; 3068 3069 case TxConfig: 3070 ret = rtl8139_TxConfig_read(s); 3071 break; 3072 3073 case RxConfig: 3074 ret = rtl8139_RxConfig_read(s); 3075 break; 3076 3077 case TxStatus0 ... TxStatus0+4*4-1: 3078 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 3079 addr, 4); 3080 break; 3081 3082 case TxAddr0 ... TxAddr0+4*4-1: 3083 ret = rtl8139_TxAddr_read(s, addr-TxAddr0); 3084 break; 3085 3086 case RxBuf: 3087 ret = rtl8139_RxBuf_read(s); 3088 break; 3089 3090 case RxRingAddrLO: 3091 ret = s->RxRingAddrLO; 3092 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret); 3093 break; 3094 3095 case RxRingAddrHI: 3096 ret = s->RxRingAddrHI; 3097 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret); 3098 break; 3099 3100 case Timer: 3101 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) / 3102 PCI_PERIOD; 3103 DPRINTF("TCTR Timer read val=0x%08x\n", ret); 3104 break; 3105 3106 case FlashReg: 3107 ret = s->TimerInt; 3108 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret); 3109 break; 3110 3111 default: 3112 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr); 3113 3114 ret = rtl8139_io_readb(opaque, addr); 3115 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3116 ret |= rtl8139_io_readb(opaque, addr + 2) << 16; 3117 ret |= rtl8139_io_readb(opaque, addr + 3) << 24; 3118 3119 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret); 3120 break; 3121 } 3122 3123 return ret; 3124 } 3125 3126 /* */ 3127 3128 static int rtl8139_post_load(void *opaque, int version_id) 3129 { 3130 RTL8139State* s = opaque; 3131 rtl8139_set_next_tctr_time(s); 3132 if (version_id < 4) { 3133 s->cplus_enabled = s->CpCmd != 0; 3134 } 3135 3136 /* nc.link_down can't be migrated, so infer link_down according 3137 * to link status bit in BasicModeStatus */ 3138 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0; 3139 3140 return 0; 3141 } 3142 3143 static bool rtl8139_hotplug_ready_needed(void *opaque) 3144 { 3145 return qdev_machine_modified(); 3146 } 3147 3148 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ 3149 .name = "rtl8139/hotplug_ready", 3150 .version_id = 1, 3151 .minimum_version_id = 1, 3152 .needed = rtl8139_hotplug_ready_needed, 3153 .fields = (VMStateField[]) { 3154 VMSTATE_END_OF_LIST() 3155 } 3156 }; 3157 3158 static int rtl8139_pre_save(void *opaque) 3159 { 3160 RTL8139State* s = opaque; 3161 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 3162 3163 /* for migration to older versions */ 3164 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD; 3165 s->rtl8139_mmio_io_addr_dummy = 0; 3166 3167 return 0; 3168 } 3169 3170 static const VMStateDescription vmstate_rtl8139 = { 3171 .name = "rtl8139", 3172 .version_id = 5, 3173 .minimum_version_id = 3, 3174 .post_load = rtl8139_post_load, 3175 .pre_save = rtl8139_pre_save, 3176 .fields = (VMStateField[]) { 3177 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State), 3178 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6), 3179 VMSTATE_BUFFER(mult, RTL8139State), 3180 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4), 3181 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4), 3182 3183 VMSTATE_UINT32(RxBuf, RTL8139State), 3184 VMSTATE_UINT32(RxBufferSize, RTL8139State), 3185 VMSTATE_UINT32(RxBufPtr, RTL8139State), 3186 VMSTATE_UINT32(RxBufAddr, RTL8139State), 3187 3188 VMSTATE_UINT16(IntrStatus, RTL8139State), 3189 VMSTATE_UINT16(IntrMask, RTL8139State), 3190 3191 VMSTATE_UINT32(TxConfig, RTL8139State), 3192 VMSTATE_UINT32(RxConfig, RTL8139State), 3193 VMSTATE_UINT32(RxMissed, RTL8139State), 3194 VMSTATE_UINT16(CSCR, RTL8139State), 3195 3196 VMSTATE_UINT8(Cfg9346, RTL8139State), 3197 VMSTATE_UINT8(Config0, RTL8139State), 3198 VMSTATE_UINT8(Config1, RTL8139State), 3199 VMSTATE_UINT8(Config3, RTL8139State), 3200 VMSTATE_UINT8(Config4, RTL8139State), 3201 VMSTATE_UINT8(Config5, RTL8139State), 3202 3203 VMSTATE_UINT8(clock_enabled, RTL8139State), 3204 VMSTATE_UINT8(bChipCmdState, RTL8139State), 3205 3206 VMSTATE_UINT16(MultiIntr, RTL8139State), 3207 3208 VMSTATE_UINT16(BasicModeCtrl, RTL8139State), 3209 VMSTATE_UINT16(BasicModeStatus, RTL8139State), 3210 VMSTATE_UINT16(NWayAdvert, RTL8139State), 3211 VMSTATE_UINT16(NWayLPAR, RTL8139State), 3212 VMSTATE_UINT16(NWayExpansion, RTL8139State), 3213 3214 VMSTATE_UINT16(CpCmd, RTL8139State), 3215 VMSTATE_UINT8(TxThresh, RTL8139State), 3216 3217 VMSTATE_UNUSED(4), 3218 VMSTATE_MACADDR(conf.macaddr, RTL8139State), 3219 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), 3220 3221 VMSTATE_UINT32(currTxDesc, RTL8139State), 3222 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), 3223 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), 3224 VMSTATE_UINT32(RxRingAddrLO, RTL8139State), 3225 VMSTATE_UINT32(RxRingAddrHI, RTL8139State), 3226 3227 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), 3228 VMSTATE_INT32(eeprom.mode, RTL8139State), 3229 VMSTATE_UINT32(eeprom.tick, RTL8139State), 3230 VMSTATE_UINT8(eeprom.address, RTL8139State), 3231 VMSTATE_UINT16(eeprom.input, RTL8139State), 3232 VMSTATE_UINT16(eeprom.output, RTL8139State), 3233 3234 VMSTATE_UINT8(eeprom.eecs, RTL8139State), 3235 VMSTATE_UINT8(eeprom.eesk, RTL8139State), 3236 VMSTATE_UINT8(eeprom.eedi, RTL8139State), 3237 VMSTATE_UINT8(eeprom.eedo, RTL8139State), 3238 3239 VMSTATE_UINT32(TCTR, RTL8139State), 3240 VMSTATE_UINT32(TimerInt, RTL8139State), 3241 VMSTATE_INT64(TCTR_base, RTL8139State), 3242 3243 VMSTATE_UINT64(tally_counters.TxOk, RTL8139State), 3244 VMSTATE_UINT64(tally_counters.RxOk, RTL8139State), 3245 VMSTATE_UINT64(tally_counters.TxERR, RTL8139State), 3246 VMSTATE_UINT32(tally_counters.RxERR, RTL8139State), 3247 VMSTATE_UINT16(tally_counters.MissPkt, RTL8139State), 3248 VMSTATE_UINT16(tally_counters.FAE, RTL8139State), 3249 VMSTATE_UINT32(tally_counters.Tx1Col, RTL8139State), 3250 VMSTATE_UINT32(tally_counters.TxMCol, RTL8139State), 3251 VMSTATE_UINT64(tally_counters.RxOkPhy, RTL8139State), 3252 VMSTATE_UINT64(tally_counters.RxOkBrd, RTL8139State), 3253 VMSTATE_UINT32_V(tally_counters.RxOkMul, RTL8139State, 5), 3254 VMSTATE_UINT16(tally_counters.TxAbt, RTL8139State), 3255 VMSTATE_UINT16(tally_counters.TxUndrn, RTL8139State), 3256 3257 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4), 3258 VMSTATE_END_OF_LIST() 3259 }, 3260 .subsections = (const VMStateDescription*[]) { 3261 &vmstate_rtl8139_hotplug_ready, 3262 NULL 3263 } 3264 }; 3265 3266 /***********************************************************/ 3267 /* PCI RTL8139 definitions */ 3268 3269 static void rtl8139_ioport_write(void *opaque, hwaddr addr, 3270 uint64_t val, unsigned size) 3271 { 3272 switch (size) { 3273 case 1: 3274 rtl8139_io_writeb(opaque, addr, val); 3275 break; 3276 case 2: 3277 rtl8139_io_writew(opaque, addr, val); 3278 break; 3279 case 4: 3280 rtl8139_io_writel(opaque, addr, val); 3281 break; 3282 } 3283 } 3284 3285 static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr, 3286 unsigned size) 3287 { 3288 switch (size) { 3289 case 1: 3290 return rtl8139_io_readb(opaque, addr); 3291 case 2: 3292 return rtl8139_io_readw(opaque, addr); 3293 case 4: 3294 return rtl8139_io_readl(opaque, addr); 3295 } 3296 3297 return -1; 3298 } 3299 3300 static const MemoryRegionOps rtl8139_io_ops = { 3301 .read = rtl8139_ioport_read, 3302 .write = rtl8139_ioport_write, 3303 .impl = { 3304 .min_access_size = 1, 3305 .max_access_size = 4, 3306 }, 3307 .endianness = DEVICE_LITTLE_ENDIAN, 3308 }; 3309 3310 static void rtl8139_timer(void *opaque) 3311 { 3312 RTL8139State *s = opaque; 3313 3314 if (!s->clock_enabled) 3315 { 3316 DPRINTF(">>> timer: clock is not running\n"); 3317 return; 3318 } 3319 3320 s->IntrStatus |= PCSTimeout; 3321 rtl8139_update_irq(s); 3322 rtl8139_set_next_tctr_time(s); 3323 } 3324 3325 static void pci_rtl8139_uninit(PCIDevice *dev) 3326 { 3327 RTL8139State *s = RTL8139(dev); 3328 3329 g_free(s->cplus_txbuffer); 3330 s->cplus_txbuffer = NULL; 3331 timer_free(s->timer); 3332 qemu_del_nic(s->nic); 3333 } 3334 3335 static void rtl8139_set_link_status(NetClientState *nc) 3336 { 3337 RTL8139State *s = qemu_get_nic_opaque(nc); 3338 3339 if (nc->link_down) { 3340 s->BasicModeStatus &= ~0x04; 3341 } else { 3342 s->BasicModeStatus |= 0x04; 3343 } 3344 3345 s->IntrStatus |= RxUnderrun; 3346 rtl8139_update_irq(s); 3347 } 3348 3349 static NetClientInfo net_rtl8139_info = { 3350 .type = NET_CLIENT_DRIVER_NIC, 3351 .size = sizeof(NICState), 3352 .can_receive = rtl8139_can_receive, 3353 .receive = rtl8139_receive, 3354 .link_status_changed = rtl8139_set_link_status, 3355 }; 3356 3357 static void pci_rtl8139_realize(PCIDevice *dev, Error **errp) 3358 { 3359 RTL8139State *s = RTL8139(dev); 3360 DeviceState *d = DEVICE(dev); 3361 uint8_t *pci_conf; 3362 3363 pci_conf = dev->config; 3364 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 3365 /* TODO: start of capability list, but no capability 3366 * list bit in status register, and offset 0xdc seems unused. */ 3367 pci_conf[PCI_CAPABILITY_LIST] = 0xdc; 3368 3369 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s, 3370 "rtl8139", 0x100); 3371 memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io, 3372 0, 0x100); 3373 3374 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io); 3375 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem); 3376 3377 qemu_macaddr_default_if_unset(&s->conf.macaddr); 3378 3379 /* prepare eeprom */ 3380 s->eeprom.contents[0] = 0x8129; 3381 #if 1 3382 /* PCI vendor and device ID should be mirrored here */ 3383 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK; 3384 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139; 3385 #endif 3386 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; 3387 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; 3388 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; 3389 3390 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, 3391 object_get_typename(OBJECT(dev)), d->id, 3392 &d->mem_reentrancy_guard, s); 3393 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 3394 3395 s->cplus_txbuffer = NULL; 3396 s->cplus_txbuffer_len = 0; 3397 s->cplus_txbuffer_offset = 0; 3398 3399 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s); 3400 } 3401 3402 static void rtl8139_instance_init(Object *obj) 3403 { 3404 RTL8139State *s = RTL8139(obj); 3405 3406 device_add_bootindex_property(obj, &s->conf.bootindex, 3407 "bootindex", "/ethernet-phy@0", 3408 DEVICE(obj)); 3409 } 3410 3411 static Property rtl8139_properties[] = { 3412 DEFINE_NIC_PROPERTIES(RTL8139State, conf), 3413 DEFINE_PROP_END_OF_LIST(), 3414 }; 3415 3416 static void rtl8139_class_init(ObjectClass *klass, void *data) 3417 { 3418 DeviceClass *dc = DEVICE_CLASS(klass); 3419 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3420 3421 k->realize = pci_rtl8139_realize; 3422 k->exit = pci_rtl8139_uninit; 3423 k->romfile = "efi-rtl8139.rom"; 3424 k->vendor_id = PCI_VENDOR_ID_REALTEK; 3425 k->device_id = PCI_DEVICE_ID_REALTEK_8139; 3426 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */ 3427 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 3428 dc->reset = rtl8139_reset; 3429 dc->vmsd = &vmstate_rtl8139; 3430 device_class_set_props(dc, rtl8139_properties); 3431 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 3432 } 3433 3434 static const TypeInfo rtl8139_info = { 3435 .name = TYPE_RTL8139, 3436 .parent = TYPE_PCI_DEVICE, 3437 .instance_size = sizeof(RTL8139State), 3438 .class_init = rtl8139_class_init, 3439 .instance_init = rtl8139_instance_init, 3440 .interfaces = (InterfaceInfo[]) { 3441 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 3442 { }, 3443 }, 3444 }; 3445 3446 static void rtl8139_register_types(void) 3447 { 3448 type_register_static(&rtl8139_info); 3449 } 3450 3451 type_init(rtl8139_register_types) 3452