1 /** 2 * QEMU RTL8139 emulation 3 * 4 * Copyright (c) 2006 Igor Kovalenko 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 24 * Modifications: 25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver) 26 * 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver 28 * HW revision ID changes for FreeBSD driver 29 * 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver 31 * Corrected packet transfer reassembly routine for 8139C+ mode 32 * Rearranged debugging print statements 33 * Implemented PCI timer interrupt (disabled by default) 34 * Implemented Tally Counters, increased VM load/save version 35 * Implemented IP/TCP/UDP checksum task offloading 36 * 37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading 38 * Fixed MTU=1500 for produced ethernet frames 39 * 40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing 41 * segmentation offloading 42 * Removed slirp.h dependency 43 * Added rx/tx buffer reset when enabling rx/tx operation 44 * 45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only 46 * when strictly needed (required for 47 * Darwin) 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading 49 */ 50 51 /* For crc32 */ 52 #include "qemu/osdep.h" 53 #include <zlib.h> 54 55 #include "hw/hw.h" 56 #include "hw/pci/pci.h" 57 #include "sysemu/dma.h" 58 #include "qemu/timer.h" 59 #include "net/net.h" 60 #include "net/eth.h" 61 #include "hw/loader.h" 62 #include "sysemu/sysemu.h" 63 #include "qemu/iov.h" 64 65 /* debug RTL8139 card */ 66 //#define DEBUG_RTL8139 1 67 68 #define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */ 69 70 #define SET_MASKED(input, mask, curr) \ 71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) 72 73 /* arg % size for size which is a power of 2 */ 74 #define MOD2(input, size) \ 75 ( ( input ) & ( size - 1 ) ) 76 77 #define ETHER_TYPE_LEN 2 78 #define ETH_MTU 1500 79 80 #define VLAN_TCI_LEN 2 81 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) 82 83 #if defined (DEBUG_RTL8139) 84 # define DPRINTF(fmt, ...) \ 85 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) 86 #else 87 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...) 88 { 89 return 0; 90 } 91 #endif 92 93 #define TYPE_RTL8139 "rtl8139" 94 95 #define RTL8139(obj) \ 96 OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139) 97 98 /* Symbolic offsets to registers. */ 99 enum RTL8139_registers { 100 MAC0 = 0, /* Ethernet hardware address. */ 101 MAR0 = 8, /* Multicast filter. */ 102 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ 103 /* Dump Tally Conter control register(64bit). C+ mode only */ 104 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 105 RxBuf = 0x30, 106 ChipCmd = 0x37, 107 RxBufPtr = 0x38, 108 RxBufAddr = 0x3A, 109 IntrMask = 0x3C, 110 IntrStatus = 0x3E, 111 TxConfig = 0x40, 112 RxConfig = 0x44, 113 Timer = 0x48, /* A general-purpose counter. */ 114 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 115 Cfg9346 = 0x50, 116 Config0 = 0x51, 117 Config1 = 0x52, 118 FlashReg = 0x54, 119 MediaStatus = 0x58, 120 Config3 = 0x59, 121 Config4 = 0x5A, /* absent on RTL-8139A */ 122 HltClk = 0x5B, 123 MultiIntr = 0x5C, 124 PCIRevisionID = 0x5E, 125 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ 126 BasicModeCtrl = 0x62, 127 BasicModeStatus = 0x64, 128 NWayAdvert = 0x66, 129 NWayLPAR = 0x68, 130 NWayExpansion = 0x6A, 131 /* Undocumented registers, but required for proper operation. */ 132 FIFOTMS = 0x70, /* FIFO Control and test. */ 133 CSCR = 0x74, /* Chip Status and Configuration Register. */ 134 PARA78 = 0x78, 135 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 136 Config5 = 0xD8, /* absent on RTL-8139A */ 137 /* C+ mode */ 138 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ 139 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ 140 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ 141 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ 142 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ 143 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ 144 TxThresh = 0xEC, /* Early Tx threshold */ 145 }; 146 147 enum ClearBitMasks { 148 MultiIntrClear = 0xF000, 149 ChipCmdClear = 0xE2, 150 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 151 }; 152 153 enum ChipCmdBits { 154 CmdReset = 0x10, 155 CmdRxEnb = 0x08, 156 CmdTxEnb = 0x04, 157 RxBufEmpty = 0x01, 158 }; 159 160 /* C+ mode */ 161 enum CplusCmdBits { 162 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ 163 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ 164 CPlusRxEnb = 0x0002, 165 CPlusTxEnb = 0x0001, 166 }; 167 168 /* Interrupt register bits, using my own meaningful names. */ 169 enum IntrStatusBits { 170 PCIErr = 0x8000, 171 PCSTimeout = 0x4000, 172 RxFIFOOver = 0x40, 173 RxUnderrun = 0x20, /* Packet Underrun / Link Change */ 174 RxOverflow = 0x10, 175 TxErr = 0x08, 176 TxOK = 0x04, 177 RxErr = 0x02, 178 RxOK = 0x01, 179 180 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 181 }; 182 183 enum TxStatusBits { 184 TxHostOwns = 0x2000, 185 TxUnderrun = 0x4000, 186 TxStatOK = 0x8000, 187 TxOutOfWindow = 0x20000000, 188 TxAborted = 0x40000000, 189 TxCarrierLost = 0x80000000, 190 }; 191 enum RxStatusBits { 192 RxMulticast = 0x8000, 193 RxPhysical = 0x4000, 194 RxBroadcast = 0x2000, 195 RxBadSymbol = 0x0020, 196 RxRunt = 0x0010, 197 RxTooLong = 0x0008, 198 RxCRCErr = 0x0004, 199 RxBadAlign = 0x0002, 200 RxStatusOK = 0x0001, 201 }; 202 203 /* Bits in RxConfig. */ 204 enum rx_mode_bits { 205 AcceptErr = 0x20, 206 AcceptRunt = 0x10, 207 AcceptBroadcast = 0x08, 208 AcceptMulticast = 0x04, 209 AcceptMyPhys = 0x02, 210 AcceptAllPhys = 0x01, 211 }; 212 213 /* Bits in TxConfig. */ 214 enum tx_config_bits { 215 216 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 217 TxIFGShift = 24, 218 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 219 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 220 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 221 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 222 223 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 224 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ 225 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 226 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ 227 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ 228 229 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 230 }; 231 232 233 /* Transmit Status of All Descriptors (TSAD) Register */ 234 enum TSAD_bits { 235 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 236 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 237 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 238 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 239 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 240 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 241 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 242 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 243 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 244 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 245 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 246 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 247 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 248 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 249 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 250 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 251 }; 252 253 254 /* Bits in Config1 */ 255 enum Config1Bits { 256 Cfg1_PM_Enable = 0x01, 257 Cfg1_VPD_Enable = 0x02, 258 Cfg1_PIO = 0x04, 259 Cfg1_MMIO = 0x08, 260 LWAKE = 0x10, /* not on 8139, 8139A */ 261 Cfg1_Driver_Load = 0x20, 262 Cfg1_LED0 = 0x40, 263 Cfg1_LED1 = 0x80, 264 SLEEP = (1 << 1), /* only on 8139, 8139A */ 265 PWRDN = (1 << 0), /* only on 8139, 8139A */ 266 }; 267 268 /* Bits in Config3 */ 269 enum Config3Bits { 270 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 271 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 272 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 273 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 274 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 275 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 276 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 277 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 278 }; 279 280 /* Bits in Config4 */ 281 enum Config4Bits { 282 LWPTN = (1 << 2), /* not on 8139, 8139A */ 283 }; 284 285 /* Bits in Config5 */ 286 enum Config5Bits { 287 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 288 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 289 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 290 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ 291 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 292 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 293 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 294 }; 295 296 enum RxConfigBits { 297 /* rx fifo threshold */ 298 RxCfgFIFOShift = 13, 299 RxCfgFIFONone = (7 << RxCfgFIFOShift), 300 301 /* Max DMA burst */ 302 RxCfgDMAShift = 8, 303 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 304 305 /* rx ring buffer length */ 306 RxCfgRcv8K = 0, 307 RxCfgRcv16K = (1 << 11), 308 RxCfgRcv32K = (1 << 12), 309 RxCfgRcv64K = (1 << 11) | (1 << 12), 310 311 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 312 RxNoWrap = (1 << 7), 313 }; 314 315 /* Twister tuning parameters from RealTek. 316 Completely undocumented, but required to tune bad links on some boards. */ 317 /* 318 enum CSCRBits { 319 CSCR_LinkOKBit = 0x0400, 320 CSCR_LinkChangeBit = 0x0800, 321 CSCR_LinkStatusBits = 0x0f000, 322 CSCR_LinkDownOffCmd = 0x003c0, 323 CSCR_LinkDownCmd = 0x0f3c0, 324 */ 325 enum CSCRBits { 326 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ 327 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ 328 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ 329 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ 330 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ 331 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ 332 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ 333 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ 334 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ 335 }; 336 337 enum Cfg9346Bits { 338 Cfg9346_Normal = 0x00, 339 Cfg9346_Autoload = 0x40, 340 Cfg9346_Programming = 0x80, 341 Cfg9346_ConfigWrite = 0xC0, 342 }; 343 344 typedef enum { 345 CH_8139 = 0, 346 CH_8139_K, 347 CH_8139A, 348 CH_8139A_G, 349 CH_8139B, 350 CH_8130, 351 CH_8139C, 352 CH_8100, 353 CH_8100B_8139D, 354 CH_8101, 355 } chip_t; 356 357 enum chip_flags { 358 HasHltClk = (1 << 0), 359 HasLWake = (1 << 1), 360 }; 361 362 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 363 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 364 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 365 366 #define RTL8139_PCI_REVID_8139 0x10 367 #define RTL8139_PCI_REVID_8139CPLUS 0x20 368 369 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS 370 371 /* Size is 64 * 16bit words */ 372 #define EEPROM_9346_ADDR_BITS 6 373 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) 374 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) 375 376 enum Chip9346Operation 377 { 378 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ 379 Chip9346_op_read = 0x80, /* 10 AAAAAA */ 380 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ 381 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ 382 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ 383 Chip9346_op_write_all = 0x10, /* 00 01zzzz */ 384 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ 385 }; 386 387 enum Chip9346Mode 388 { 389 Chip9346_none = 0, 390 Chip9346_enter_command_mode, 391 Chip9346_read_command, 392 Chip9346_data_read, /* from output register */ 393 Chip9346_data_write, /* to input register, then to contents at specified address */ 394 Chip9346_data_write_all, /* to input register, then filling contents */ 395 }; 396 397 typedef struct EEprom9346 398 { 399 uint16_t contents[EEPROM_9346_SIZE]; 400 int mode; 401 uint32_t tick; 402 uint8_t address; 403 uint16_t input; 404 uint16_t output; 405 406 uint8_t eecs; 407 uint8_t eesk; 408 uint8_t eedi; 409 uint8_t eedo; 410 } EEprom9346; 411 412 typedef struct RTL8139TallyCounters 413 { 414 /* Tally counters */ 415 uint64_t TxOk; 416 uint64_t RxOk; 417 uint64_t TxERR; 418 uint32_t RxERR; 419 uint16_t MissPkt; 420 uint16_t FAE; 421 uint32_t Tx1Col; 422 uint32_t TxMCol; 423 uint64_t RxOkPhy; 424 uint64_t RxOkBrd; 425 uint32_t RxOkMul; 426 uint16_t TxAbt; 427 uint16_t TxUndrn; 428 } RTL8139TallyCounters; 429 430 /* Clears all tally counters */ 431 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); 432 433 typedef struct RTL8139State { 434 /*< private >*/ 435 PCIDevice parent_obj; 436 /*< public >*/ 437 438 uint8_t phys[8]; /* mac address */ 439 uint8_t mult[8]; /* multicast mask array */ 440 441 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ 442 uint32_t TxAddr[4]; /* TxAddr0 */ 443 uint32_t RxBuf; /* Receive buffer */ 444 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */ 445 uint32_t RxBufPtr; 446 uint32_t RxBufAddr; 447 448 uint16_t IntrStatus; 449 uint16_t IntrMask; 450 451 uint32_t TxConfig; 452 uint32_t RxConfig; 453 uint32_t RxMissed; 454 455 uint16_t CSCR; 456 457 uint8_t Cfg9346; 458 uint8_t Config0; 459 uint8_t Config1; 460 uint8_t Config3; 461 uint8_t Config4; 462 uint8_t Config5; 463 464 uint8_t clock_enabled; 465 uint8_t bChipCmdState; 466 467 uint16_t MultiIntr; 468 469 uint16_t BasicModeCtrl; 470 uint16_t BasicModeStatus; 471 uint16_t NWayAdvert; 472 uint16_t NWayLPAR; 473 uint16_t NWayExpansion; 474 475 uint16_t CpCmd; 476 uint8_t TxThresh; 477 478 NICState *nic; 479 NICConf conf; 480 481 /* C ring mode */ 482 uint32_t currTxDesc; 483 484 /* C+ mode */ 485 uint32_t cplus_enabled; 486 487 uint32_t currCPlusRxDesc; 488 uint32_t currCPlusTxDesc; 489 490 uint32_t RxRingAddrLO; 491 uint32_t RxRingAddrHI; 492 493 EEprom9346 eeprom; 494 495 uint32_t TCTR; 496 uint32_t TimerInt; 497 int64_t TCTR_base; 498 499 /* Tally counters */ 500 RTL8139TallyCounters tally_counters; 501 502 /* Non-persistent data */ 503 uint8_t *cplus_txbuffer; 504 int cplus_txbuffer_len; 505 int cplus_txbuffer_offset; 506 507 /* PCI interrupt timer */ 508 QEMUTimer *timer; 509 510 MemoryRegion bar_io; 511 MemoryRegion bar_mem; 512 513 /* Support migration to/from old versions */ 514 int rtl8139_mmio_io_addr_dummy; 515 } RTL8139State; 516 517 /* Writes tally counters to memory via DMA */ 518 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr); 519 520 static void rtl8139_set_next_tctr_time(RTL8139State *s); 521 522 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) 523 { 524 DPRINTF("eeprom command 0x%02x\n", command); 525 526 switch (command & Chip9346_op_mask) 527 { 528 case Chip9346_op_read: 529 { 530 eeprom->address = command & EEPROM_9346_ADDR_MASK; 531 eeprom->output = eeprom->contents[eeprom->address]; 532 eeprom->eedo = 0; 533 eeprom->tick = 0; 534 eeprom->mode = Chip9346_data_read; 535 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", 536 eeprom->address, eeprom->output); 537 } 538 break; 539 540 case Chip9346_op_write: 541 { 542 eeprom->address = command & EEPROM_9346_ADDR_MASK; 543 eeprom->input = 0; 544 eeprom->tick = 0; 545 eeprom->mode = Chip9346_none; /* Chip9346_data_write */ 546 DPRINTF("eeprom begin write to address 0x%02x\n", 547 eeprom->address); 548 } 549 break; 550 default: 551 eeprom->mode = Chip9346_none; 552 switch (command & Chip9346_op_ext_mask) 553 { 554 case Chip9346_op_write_enable: 555 DPRINTF("eeprom write enabled\n"); 556 break; 557 case Chip9346_op_write_all: 558 DPRINTF("eeprom begin write all\n"); 559 break; 560 case Chip9346_op_write_disable: 561 DPRINTF("eeprom write disabled\n"); 562 break; 563 } 564 break; 565 } 566 } 567 568 static void prom9346_shift_clock(EEprom9346 *eeprom) 569 { 570 int bit = eeprom->eedi?1:0; 571 572 ++ eeprom->tick; 573 574 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, 575 eeprom->eedo); 576 577 switch (eeprom->mode) 578 { 579 case Chip9346_enter_command_mode: 580 if (bit) 581 { 582 eeprom->mode = Chip9346_read_command; 583 eeprom->tick = 0; 584 eeprom->input = 0; 585 DPRINTF("eeprom: +++ synchronized, begin command read\n"); 586 } 587 break; 588 589 case Chip9346_read_command: 590 eeprom->input = (eeprom->input << 1) | (bit & 1); 591 if (eeprom->tick == 8) 592 { 593 prom9346_decode_command(eeprom, eeprom->input & 0xff); 594 } 595 break; 596 597 case Chip9346_data_read: 598 eeprom->eedo = (eeprom->output & 0x8000)?1:0; 599 eeprom->output <<= 1; 600 if (eeprom->tick == 16) 601 { 602 #if 1 603 // the FreeBSD drivers (rl and re) don't explicitly toggle 604 // CS between reads (or does setting Cfg9346 to 0 count too?), 605 // so we need to enter wait-for-command state here 606 eeprom->mode = Chip9346_enter_command_mode; 607 eeprom->input = 0; 608 eeprom->tick = 0; 609 610 DPRINTF("eeprom: +++ end of read, awaiting next command\n"); 611 #else 612 // original behaviour 613 ++eeprom->address; 614 eeprom->address &= EEPROM_9346_ADDR_MASK; 615 eeprom->output = eeprom->contents[eeprom->address]; 616 eeprom->tick = 0; 617 618 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", 619 eeprom->address, eeprom->output); 620 #endif 621 } 622 break; 623 624 case Chip9346_data_write: 625 eeprom->input = (eeprom->input << 1) | (bit & 1); 626 if (eeprom->tick == 16) 627 { 628 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n", 629 eeprom->address, eeprom->input); 630 631 eeprom->contents[eeprom->address] = eeprom->input; 632 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ 633 eeprom->tick = 0; 634 eeprom->input = 0; 635 } 636 break; 637 638 case Chip9346_data_write_all: 639 eeprom->input = (eeprom->input << 1) | (bit & 1); 640 if (eeprom->tick == 16) 641 { 642 int i; 643 for (i = 0; i < EEPROM_9346_SIZE; i++) 644 { 645 eeprom->contents[i] = eeprom->input; 646 } 647 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); 648 649 eeprom->mode = Chip9346_enter_command_mode; 650 eeprom->tick = 0; 651 eeprom->input = 0; 652 } 653 break; 654 655 default: 656 break; 657 } 658 } 659 660 static int prom9346_get_wire(RTL8139State *s) 661 { 662 EEprom9346 *eeprom = &s->eeprom; 663 if (!eeprom->eecs) 664 return 0; 665 666 return eeprom->eedo; 667 } 668 669 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */ 670 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) 671 { 672 EEprom9346 *eeprom = &s->eeprom; 673 uint8_t old_eecs = eeprom->eecs; 674 uint8_t old_eesk = eeprom->eesk; 675 676 eeprom->eecs = eecs; 677 eeprom->eesk = eesk; 678 eeprom->eedi = eedi; 679 680 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, 681 eeprom->eesk, eeprom->eedi, eeprom->eedo); 682 683 if (!old_eecs && eecs) 684 { 685 /* Synchronize start */ 686 eeprom->tick = 0; 687 eeprom->input = 0; 688 eeprom->output = 0; 689 eeprom->mode = Chip9346_enter_command_mode; 690 691 DPRINTF("=== eeprom: begin access, enter command mode\n"); 692 } 693 694 if (!eecs) 695 { 696 DPRINTF("=== eeprom: end access\n"); 697 return; 698 } 699 700 if (!old_eesk && eesk) 701 { 702 /* SK front rules */ 703 prom9346_shift_clock(eeprom); 704 } 705 } 706 707 static void rtl8139_update_irq(RTL8139State *s) 708 { 709 PCIDevice *d = PCI_DEVICE(s); 710 int isr; 711 isr = (s->IntrStatus & s->IntrMask) & 0xffff; 712 713 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, 714 s->IntrMask); 715 716 pci_set_irq(d, (isr != 0)); 717 } 718 719 static int rtl8139_RxWrap(RTL8139State *s) 720 { 721 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */ 722 return (s->RxConfig & (1 << 7)); 723 } 724 725 static int rtl8139_receiver_enabled(RTL8139State *s) 726 { 727 return s->bChipCmdState & CmdRxEnb; 728 } 729 730 static int rtl8139_transmitter_enabled(RTL8139State *s) 731 { 732 return s->bChipCmdState & CmdTxEnb; 733 } 734 735 static int rtl8139_cp_receiver_enabled(RTL8139State *s) 736 { 737 return s->CpCmd & CPlusRxEnb; 738 } 739 740 static int rtl8139_cp_transmitter_enabled(RTL8139State *s) 741 { 742 return s->CpCmd & CPlusTxEnb; 743 } 744 745 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) 746 { 747 PCIDevice *d = PCI_DEVICE(s); 748 749 if (s->RxBufAddr + size > s->RxBufferSize) 750 { 751 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); 752 753 /* write packet data */ 754 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) 755 { 756 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped); 757 758 if (size > wrapped) 759 { 760 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 761 buf, size-wrapped); 762 } 763 764 /* reset buffer pointer */ 765 s->RxBufAddr = 0; 766 767 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 768 buf + (size-wrapped), wrapped); 769 770 s->RxBufAddr = wrapped; 771 772 return; 773 } 774 } 775 776 /* non-wrapping path or overwrapping enabled */ 777 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size); 778 779 s->RxBufAddr += size; 780 } 781 782 #define MIN_BUF_SIZE 60 783 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high) 784 { 785 return low | ((uint64_t)high << 32); 786 } 787 788 /* Workaround for buggy guest driver such as linux who allocates rx 789 * rings after the receiver were enabled. */ 790 static bool rtl8139_cp_rx_valid(RTL8139State *s) 791 { 792 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0); 793 } 794 795 static int rtl8139_can_receive(NetClientState *nc) 796 { 797 RTL8139State *s = qemu_get_nic_opaque(nc); 798 int avail; 799 800 /* Receive (drop) packets if card is disabled. */ 801 if (!s->clock_enabled) 802 return 1; 803 if (!rtl8139_receiver_enabled(s)) 804 return 1; 805 806 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) { 807 /* ??? Flow control not implemented in c+ mode. 808 This is a hack to work around slirp deficiencies anyway. */ 809 return 1; 810 } else { 811 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, 812 s->RxBufferSize); 813 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow)); 814 } 815 } 816 817 static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) 818 { 819 RTL8139State *s = qemu_get_nic_opaque(nc); 820 PCIDevice *d = PCI_DEVICE(s); 821 /* size is the length of the buffer passed to the driver */ 822 int size = size_; 823 const uint8_t *dot1q_buf = NULL; 824 825 uint32_t packet_header = 0; 826 827 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; 828 static const uint8_t broadcast_macaddr[6] = 829 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 830 831 DPRINTF(">>> received len=%d\n", size); 832 833 /* test if board clock is stopped */ 834 if (!s->clock_enabled) 835 { 836 DPRINTF("stopped ==========================\n"); 837 return -1; 838 } 839 840 /* first check if receiver is enabled */ 841 842 if (!rtl8139_receiver_enabled(s)) 843 { 844 DPRINTF("receiver disabled ================\n"); 845 return -1; 846 } 847 848 /* XXX: check this */ 849 if (s->RxConfig & AcceptAllPhys) { 850 /* promiscuous: receive all */ 851 DPRINTF(">>> packet received in promiscuous mode\n"); 852 853 } else { 854 if (!memcmp(buf, broadcast_macaddr, 6)) { 855 /* broadcast address */ 856 if (!(s->RxConfig & AcceptBroadcast)) 857 { 858 DPRINTF(">>> broadcast packet rejected\n"); 859 860 /* update tally counter */ 861 ++s->tally_counters.RxERR; 862 863 return size; 864 } 865 866 packet_header |= RxBroadcast; 867 868 DPRINTF(">>> broadcast packet received\n"); 869 870 /* update tally counter */ 871 ++s->tally_counters.RxOkBrd; 872 873 } else if (buf[0] & 0x01) { 874 /* multicast */ 875 if (!(s->RxConfig & AcceptMulticast)) 876 { 877 DPRINTF(">>> multicast packet rejected\n"); 878 879 /* update tally counter */ 880 ++s->tally_counters.RxERR; 881 882 return size; 883 } 884 885 int mcast_idx = compute_mcast_idx(buf); 886 887 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) 888 { 889 DPRINTF(">>> multicast address mismatch\n"); 890 891 /* update tally counter */ 892 ++s->tally_counters.RxERR; 893 894 return size; 895 } 896 897 packet_header |= RxMulticast; 898 899 DPRINTF(">>> multicast packet received\n"); 900 901 /* update tally counter */ 902 ++s->tally_counters.RxOkMul; 903 904 } else if (s->phys[0] == buf[0] && 905 s->phys[1] == buf[1] && 906 s->phys[2] == buf[2] && 907 s->phys[3] == buf[3] && 908 s->phys[4] == buf[4] && 909 s->phys[5] == buf[5]) { 910 /* match */ 911 if (!(s->RxConfig & AcceptMyPhys)) 912 { 913 DPRINTF(">>> rejecting physical address matching packet\n"); 914 915 /* update tally counter */ 916 ++s->tally_counters.RxERR; 917 918 return size; 919 } 920 921 packet_header |= RxPhysical; 922 923 DPRINTF(">>> physical address matching packet received\n"); 924 925 /* update tally counter */ 926 ++s->tally_counters.RxOkPhy; 927 928 } else { 929 930 DPRINTF(">>> unknown packet\n"); 931 932 /* update tally counter */ 933 ++s->tally_counters.RxERR; 934 935 return size; 936 } 937 } 938 939 /* if too small buffer, then expand it 940 * Include some tailroom in case a vlan tag is later removed. */ 941 if (size < MIN_BUF_SIZE + VLAN_HLEN) { 942 memcpy(buf1, buf, size); 943 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size); 944 buf = buf1; 945 if (size < MIN_BUF_SIZE) { 946 size = MIN_BUF_SIZE; 947 } 948 } 949 950 if (rtl8139_cp_receiver_enabled(s)) 951 { 952 if (!rtl8139_cp_rx_valid(s)) { 953 return size; 954 } 955 956 DPRINTF("in C+ Rx mode ================\n"); 957 958 /* begin C+ receiver mode */ 959 960 /* w0 ownership flag */ 961 #define CP_RX_OWN (1<<31) 962 /* w0 end of ring flag */ 963 #define CP_RX_EOR (1<<30) 964 /* w0 bits 0...12 : buffer size */ 965 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) 966 /* w1 tag available flag */ 967 #define CP_RX_TAVA (1<<16) 968 /* w1 bits 0...15 : VLAN tag */ 969 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) 970 /* w2 low 32bit of Rx buffer ptr */ 971 /* w3 high 32bit of Rx buffer ptr */ 972 973 int descriptor = s->currCPlusRxDesc; 974 dma_addr_t cplus_rx_ring_desc; 975 976 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); 977 cplus_rx_ring_desc += 16 * descriptor; 978 979 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at " 980 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI, 981 s->RxRingAddrLO, cplus_rx_ring_desc); 982 983 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; 984 985 pci_dma_read(d, cplus_rx_ring_desc, &val, 4); 986 rxdw0 = le32_to_cpu(val); 987 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4); 988 rxdw1 = le32_to_cpu(val); 989 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4); 990 rxbufLO = le32_to_cpu(val); 991 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4); 992 rxbufHI = le32_to_cpu(val); 993 994 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", 995 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); 996 997 if (!(rxdw0 & CP_RX_OWN)) 998 { 999 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n", 1000 descriptor); 1001 1002 s->IntrStatus |= RxOverflow; 1003 ++s->RxMissed; 1004 1005 /* update tally counter */ 1006 ++s->tally_counters.RxERR; 1007 ++s->tally_counters.MissPkt; 1008 1009 rtl8139_update_irq(s); 1010 return size_; 1011 } 1012 1013 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; 1014 1015 /* write VLAN info to descriptor variables. */ 1016 if (s->CpCmd & CPlusRxVLAN && 1017 lduw_be_p(&buf[ETH_ALEN * 2]) == ETH_P_VLAN) { 1018 dot1q_buf = &buf[ETH_ALEN * 2]; 1019 size -= VLAN_HLEN; 1020 /* if too small buffer, use the tailroom added duing expansion */ 1021 if (size < MIN_BUF_SIZE) { 1022 size = MIN_BUF_SIZE; 1023 } 1024 1025 rxdw1 &= ~CP_RX_VLAN_TAG_MASK; 1026 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */ 1027 rxdw1 |= CP_RX_TAVA | lduw_le_p(&dot1q_buf[ETHER_TYPE_LEN]); 1028 1029 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", 1030 lduw_be_p(&dot1q_buf[ETHER_TYPE_LEN])); 1031 } else { 1032 /* reset VLAN tag flag */ 1033 rxdw1 &= ~CP_RX_TAVA; 1034 } 1035 1036 /* TODO: scatter the packet over available receive ring descriptors space */ 1037 1038 if (size+4 > rx_space) 1039 { 1040 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n", 1041 descriptor, rx_space, size); 1042 1043 s->IntrStatus |= RxOverflow; 1044 ++s->RxMissed; 1045 1046 /* update tally counter */ 1047 ++s->tally_counters.RxERR; 1048 ++s->tally_counters.MissPkt; 1049 1050 rtl8139_update_irq(s); 1051 return size_; 1052 } 1053 1054 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); 1055 1056 /* receive/copy to target memory */ 1057 if (dot1q_buf) { 1058 pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN); 1059 pci_dma_write(d, rx_addr + 2 * ETH_ALEN, 1060 buf + 2 * ETH_ALEN + VLAN_HLEN, 1061 size - 2 * ETH_ALEN); 1062 } else { 1063 pci_dma_write(d, rx_addr, buf, size); 1064 } 1065 1066 if (s->CpCmd & CPlusRxChkSum) 1067 { 1068 /* do some packet checksumming */ 1069 } 1070 1071 /* write checksum */ 1072 val = cpu_to_le32(crc32(0, buf, size_)); 1073 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4); 1074 1075 /* first segment of received packet flag */ 1076 #define CP_RX_STATUS_FS (1<<29) 1077 /* last segment of received packet flag */ 1078 #define CP_RX_STATUS_LS (1<<28) 1079 /* multicast packet flag */ 1080 #define CP_RX_STATUS_MAR (1<<26) 1081 /* physical-matching packet flag */ 1082 #define CP_RX_STATUS_PAM (1<<25) 1083 /* broadcast packet flag */ 1084 #define CP_RX_STATUS_BAR (1<<24) 1085 /* runt packet flag */ 1086 #define CP_RX_STATUS_RUNT (1<<19) 1087 /* crc error flag */ 1088 #define CP_RX_STATUS_CRC (1<<18) 1089 /* IP checksum error flag */ 1090 #define CP_RX_STATUS_IPF (1<<15) 1091 /* UDP checksum error flag */ 1092 #define CP_RX_STATUS_UDPF (1<<14) 1093 /* TCP checksum error flag */ 1094 #define CP_RX_STATUS_TCPF (1<<13) 1095 1096 /* transfer ownership to target */ 1097 rxdw0 &= ~CP_RX_OWN; 1098 1099 /* set first segment bit */ 1100 rxdw0 |= CP_RX_STATUS_FS; 1101 1102 /* set last segment bit */ 1103 rxdw0 |= CP_RX_STATUS_LS; 1104 1105 /* set received packet type flags */ 1106 if (packet_header & RxBroadcast) 1107 rxdw0 |= CP_RX_STATUS_BAR; 1108 if (packet_header & RxMulticast) 1109 rxdw0 |= CP_RX_STATUS_MAR; 1110 if (packet_header & RxPhysical) 1111 rxdw0 |= CP_RX_STATUS_PAM; 1112 1113 /* set received size */ 1114 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; 1115 rxdw0 |= (size+4); 1116 1117 /* update ring data */ 1118 val = cpu_to_le32(rxdw0); 1119 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4); 1120 val = cpu_to_le32(rxdw1); 1121 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4); 1122 1123 /* update tally counter */ 1124 ++s->tally_counters.RxOk; 1125 1126 /* seek to next Rx descriptor */ 1127 if (rxdw0 & CP_RX_EOR) 1128 { 1129 s->currCPlusRxDesc = 0; 1130 } 1131 else 1132 { 1133 ++s->currCPlusRxDesc; 1134 } 1135 1136 DPRINTF("done C+ Rx mode ----------------\n"); 1137 1138 } 1139 else 1140 { 1141 DPRINTF("in ring Rx mode ================\n"); 1142 1143 /* begin ring receiver mode */ 1144 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); 1145 1146 /* if receiver buffer is empty then avail == 0 */ 1147 1148 #define RX_ALIGN(x) (((x) + 3) & ~0x3) 1149 1150 if (avail != 0 && RX_ALIGN(size + 8) >= avail) 1151 { 1152 DPRINTF("rx overflow: rx buffer length %d head 0x%04x " 1153 "read 0x%04x === available 0x%04x need 0x%04x\n", 1154 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); 1155 1156 s->IntrStatus |= RxOverflow; 1157 ++s->RxMissed; 1158 rtl8139_update_irq(s); 1159 return 0; 1160 } 1161 1162 packet_header |= RxStatusOK; 1163 1164 packet_header |= (((size+4) << 16) & 0xffff0000); 1165 1166 /* write header */ 1167 uint32_t val = cpu_to_le32(packet_header); 1168 1169 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1170 1171 rtl8139_write_buffer(s, buf, size); 1172 1173 /* write checksum */ 1174 val = cpu_to_le32(crc32(0, buf, size)); 1175 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1176 1177 /* correct buffer write pointer */ 1178 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize); 1179 1180 /* now we can signal we have received something */ 1181 1182 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n", 1183 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 1184 } 1185 1186 s->IntrStatus |= RxOK; 1187 1188 if (do_interrupt) 1189 { 1190 rtl8139_update_irq(s); 1191 } 1192 1193 return size_; 1194 } 1195 1196 static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1197 { 1198 return rtl8139_do_receive(nc, buf, size, 1); 1199 } 1200 1201 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) 1202 { 1203 s->RxBufferSize = bufferSize; 1204 s->RxBufPtr = 0; 1205 s->RxBufAddr = 0; 1206 } 1207 1208 static void rtl8139_reset_phy(RTL8139State *s) 1209 { 1210 s->BasicModeStatus = 0x7809; 1211 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ 1212 /* preserve link state */ 1213 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04; 1214 1215 s->NWayAdvert = 0x05e1; /* all modes, full duplex */ 1216 s->NWayLPAR = 0x05e1; /* all modes, full duplex */ 1217 s->NWayExpansion = 0x0001; /* autonegotiation supported */ 1218 1219 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; 1220 } 1221 1222 static void rtl8139_reset(DeviceState *d) 1223 { 1224 RTL8139State *s = RTL8139(d); 1225 int i; 1226 1227 /* restore MAC address */ 1228 memcpy(s->phys, s->conf.macaddr.a, 6); 1229 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 1230 1231 /* reset interrupt mask */ 1232 s->IntrStatus = 0; 1233 s->IntrMask = 0; 1234 1235 rtl8139_update_irq(s); 1236 1237 /* mark all status registers as owned by host */ 1238 for (i = 0; i < 4; ++i) 1239 { 1240 s->TxStatus[i] = TxHostOwns; 1241 } 1242 1243 s->currTxDesc = 0; 1244 s->currCPlusRxDesc = 0; 1245 s->currCPlusTxDesc = 0; 1246 1247 s->RxRingAddrLO = 0; 1248 s->RxRingAddrHI = 0; 1249 1250 s->RxBuf = 0; 1251 1252 rtl8139_reset_rxring(s, 8192); 1253 1254 /* ACK the reset */ 1255 s->TxConfig = 0; 1256 1257 #if 0 1258 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk 1259 s->clock_enabled = 0; 1260 #else 1261 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake 1262 s->clock_enabled = 1; 1263 #endif 1264 1265 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; 1266 1267 /* set initial state data */ 1268 s->Config0 = 0x0; /* No boot ROM */ 1269 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ 1270 s->Config3 = 0x1; /* fast back-to-back compatible */ 1271 s->Config5 = 0x0; 1272 1273 s->CpCmd = 0x0; /* reset C+ mode */ 1274 s->cplus_enabled = 0; 1275 1276 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation 1277 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex 1278 s->BasicModeCtrl = 0x1000; // autonegotiation 1279 1280 rtl8139_reset_phy(s); 1281 1282 /* also reset timer and disable timer interrupt */ 1283 s->TCTR = 0; 1284 s->TimerInt = 0; 1285 s->TCTR_base = 0; 1286 rtl8139_set_next_tctr_time(s); 1287 1288 /* reset tally counters */ 1289 RTL8139TallyCounters_clear(&s->tally_counters); 1290 } 1291 1292 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) 1293 { 1294 counters->TxOk = 0; 1295 counters->RxOk = 0; 1296 counters->TxERR = 0; 1297 counters->RxERR = 0; 1298 counters->MissPkt = 0; 1299 counters->FAE = 0; 1300 counters->Tx1Col = 0; 1301 counters->TxMCol = 0; 1302 counters->RxOkPhy = 0; 1303 counters->RxOkBrd = 0; 1304 counters->RxOkMul = 0; 1305 counters->TxAbt = 0; 1306 counters->TxUndrn = 0; 1307 } 1308 1309 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr) 1310 { 1311 PCIDevice *d = PCI_DEVICE(s); 1312 RTL8139TallyCounters *tally_counters = &s->tally_counters; 1313 uint16_t val16; 1314 uint32_t val32; 1315 uint64_t val64; 1316 1317 val64 = cpu_to_le64(tally_counters->TxOk); 1318 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8); 1319 1320 val64 = cpu_to_le64(tally_counters->RxOk); 1321 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8); 1322 1323 val64 = cpu_to_le64(tally_counters->TxERR); 1324 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8); 1325 1326 val32 = cpu_to_le32(tally_counters->RxERR); 1327 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4); 1328 1329 val16 = cpu_to_le16(tally_counters->MissPkt); 1330 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2); 1331 1332 val16 = cpu_to_le16(tally_counters->FAE); 1333 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2); 1334 1335 val32 = cpu_to_le32(tally_counters->Tx1Col); 1336 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4); 1337 1338 val32 = cpu_to_le32(tally_counters->TxMCol); 1339 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4); 1340 1341 val64 = cpu_to_le64(tally_counters->RxOkPhy); 1342 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8); 1343 1344 val64 = cpu_to_le64(tally_counters->RxOkBrd); 1345 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8); 1346 1347 val32 = cpu_to_le32(tally_counters->RxOkMul); 1348 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4); 1349 1350 val16 = cpu_to_le16(tally_counters->TxAbt); 1351 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2); 1352 1353 val16 = cpu_to_le16(tally_counters->TxUndrn); 1354 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2); 1355 } 1356 1357 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) 1358 { 1359 DeviceState *d = DEVICE(s); 1360 1361 val &= 0xff; 1362 1363 DPRINTF("ChipCmd write val=0x%08x\n", val); 1364 1365 if (val & CmdReset) 1366 { 1367 DPRINTF("ChipCmd reset\n"); 1368 rtl8139_reset(d); 1369 } 1370 if (val & CmdRxEnb) 1371 { 1372 DPRINTF("ChipCmd enable receiver\n"); 1373 1374 s->currCPlusRxDesc = 0; 1375 } 1376 if (val & CmdTxEnb) 1377 { 1378 DPRINTF("ChipCmd enable transmitter\n"); 1379 1380 s->currCPlusTxDesc = 0; 1381 } 1382 1383 /* mask unwritable bits */ 1384 val = SET_MASKED(val, 0xe3, s->bChipCmdState); 1385 1386 /* Deassert reset pin before next read */ 1387 val &= ~CmdReset; 1388 1389 s->bChipCmdState = val; 1390 } 1391 1392 static int rtl8139_RxBufferEmpty(RTL8139State *s) 1393 { 1394 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); 1395 1396 if (unread != 0) 1397 { 1398 DPRINTF("receiver buffer data available 0x%04x\n", unread); 1399 return 0; 1400 } 1401 1402 DPRINTF("receiver buffer is empty\n"); 1403 1404 return 1; 1405 } 1406 1407 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s) 1408 { 1409 uint32_t ret = s->bChipCmdState; 1410 1411 if (rtl8139_RxBufferEmpty(s)) 1412 ret |= RxBufEmpty; 1413 1414 DPRINTF("ChipCmd read val=0x%04x\n", ret); 1415 1416 return ret; 1417 } 1418 1419 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) 1420 { 1421 val &= 0xffff; 1422 1423 DPRINTF("C+ command register write(w) val=0x%04x\n", val); 1424 1425 s->cplus_enabled = 1; 1426 1427 /* mask unwritable bits */ 1428 val = SET_MASKED(val, 0xff84, s->CpCmd); 1429 1430 s->CpCmd = val; 1431 } 1432 1433 static uint32_t rtl8139_CpCmd_read(RTL8139State *s) 1434 { 1435 uint32_t ret = s->CpCmd; 1436 1437 DPRINTF("C+ command register read(w) val=0x%04x\n", ret); 1438 1439 return ret; 1440 } 1441 1442 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) 1443 { 1444 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val); 1445 } 1446 1447 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s) 1448 { 1449 uint32_t ret = 0; 1450 1451 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret); 1452 1453 return ret; 1454 } 1455 1456 static int rtl8139_config_writable(RTL8139State *s) 1457 { 1458 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite) 1459 { 1460 return 1; 1461 } 1462 1463 DPRINTF("Configuration registers are write-protected\n"); 1464 1465 return 0; 1466 } 1467 1468 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) 1469 { 1470 val &= 0xffff; 1471 1472 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val); 1473 1474 /* mask unwritable bits */ 1475 uint32_t mask = 0xccff; 1476 1477 if (1 || !rtl8139_config_writable(s)) 1478 { 1479 /* Speed setting and autonegotiation enable bits are read-only */ 1480 mask |= 0x3000; 1481 /* Duplex mode setting is read-only */ 1482 mask |= 0x0100; 1483 } 1484 1485 if (val & 0x8000) { 1486 /* Reset PHY */ 1487 rtl8139_reset_phy(s); 1488 } 1489 1490 val = SET_MASKED(val, mask, s->BasicModeCtrl); 1491 1492 s->BasicModeCtrl = val; 1493 } 1494 1495 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s) 1496 { 1497 uint32_t ret = s->BasicModeCtrl; 1498 1499 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret); 1500 1501 return ret; 1502 } 1503 1504 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) 1505 { 1506 val &= 0xffff; 1507 1508 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val); 1509 1510 /* mask unwritable bits */ 1511 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); 1512 1513 s->BasicModeStatus = val; 1514 } 1515 1516 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s) 1517 { 1518 uint32_t ret = s->BasicModeStatus; 1519 1520 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret); 1521 1522 return ret; 1523 } 1524 1525 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) 1526 { 1527 DeviceState *d = DEVICE(s); 1528 1529 val &= 0xff; 1530 1531 DPRINTF("Cfg9346 write val=0x%02x\n", val); 1532 1533 /* mask unwritable bits */ 1534 val = SET_MASKED(val, 0x31, s->Cfg9346); 1535 1536 uint32_t opmode = val & 0xc0; 1537 uint32_t eeprom_val = val & 0xf; 1538 1539 if (opmode == 0x80) { 1540 /* eeprom access */ 1541 int eecs = (eeprom_val & 0x08)?1:0; 1542 int eesk = (eeprom_val & 0x04)?1:0; 1543 int eedi = (eeprom_val & 0x02)?1:0; 1544 prom9346_set_wire(s, eecs, eesk, eedi); 1545 } else if (opmode == 0x40) { 1546 /* Reset. */ 1547 val = 0; 1548 rtl8139_reset(d); 1549 } 1550 1551 s->Cfg9346 = val; 1552 } 1553 1554 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s) 1555 { 1556 uint32_t ret = s->Cfg9346; 1557 1558 uint32_t opmode = ret & 0xc0; 1559 1560 if (opmode == 0x80) 1561 { 1562 /* eeprom access */ 1563 int eedo = prom9346_get_wire(s); 1564 if (eedo) 1565 { 1566 ret |= 0x01; 1567 } 1568 else 1569 { 1570 ret &= ~0x01; 1571 } 1572 } 1573 1574 DPRINTF("Cfg9346 read val=0x%02x\n", ret); 1575 1576 return ret; 1577 } 1578 1579 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) 1580 { 1581 val &= 0xff; 1582 1583 DPRINTF("Config0 write val=0x%02x\n", val); 1584 1585 if (!rtl8139_config_writable(s)) { 1586 return; 1587 } 1588 1589 /* mask unwritable bits */ 1590 val = SET_MASKED(val, 0xf8, s->Config0); 1591 1592 s->Config0 = val; 1593 } 1594 1595 static uint32_t rtl8139_Config0_read(RTL8139State *s) 1596 { 1597 uint32_t ret = s->Config0; 1598 1599 DPRINTF("Config0 read val=0x%02x\n", ret); 1600 1601 return ret; 1602 } 1603 1604 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) 1605 { 1606 val &= 0xff; 1607 1608 DPRINTF("Config1 write val=0x%02x\n", val); 1609 1610 if (!rtl8139_config_writable(s)) { 1611 return; 1612 } 1613 1614 /* mask unwritable bits */ 1615 val = SET_MASKED(val, 0xC, s->Config1); 1616 1617 s->Config1 = val; 1618 } 1619 1620 static uint32_t rtl8139_Config1_read(RTL8139State *s) 1621 { 1622 uint32_t ret = s->Config1; 1623 1624 DPRINTF("Config1 read val=0x%02x\n", ret); 1625 1626 return ret; 1627 } 1628 1629 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) 1630 { 1631 val &= 0xff; 1632 1633 DPRINTF("Config3 write val=0x%02x\n", val); 1634 1635 if (!rtl8139_config_writable(s)) { 1636 return; 1637 } 1638 1639 /* mask unwritable bits */ 1640 val = SET_MASKED(val, 0x8F, s->Config3); 1641 1642 s->Config3 = val; 1643 } 1644 1645 static uint32_t rtl8139_Config3_read(RTL8139State *s) 1646 { 1647 uint32_t ret = s->Config3; 1648 1649 DPRINTF("Config3 read val=0x%02x\n", ret); 1650 1651 return ret; 1652 } 1653 1654 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) 1655 { 1656 val &= 0xff; 1657 1658 DPRINTF("Config4 write val=0x%02x\n", val); 1659 1660 if (!rtl8139_config_writable(s)) { 1661 return; 1662 } 1663 1664 /* mask unwritable bits */ 1665 val = SET_MASKED(val, 0x0a, s->Config4); 1666 1667 s->Config4 = val; 1668 } 1669 1670 static uint32_t rtl8139_Config4_read(RTL8139State *s) 1671 { 1672 uint32_t ret = s->Config4; 1673 1674 DPRINTF("Config4 read val=0x%02x\n", ret); 1675 1676 return ret; 1677 } 1678 1679 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) 1680 { 1681 val &= 0xff; 1682 1683 DPRINTF("Config5 write val=0x%02x\n", val); 1684 1685 /* mask unwritable bits */ 1686 val = SET_MASKED(val, 0x80, s->Config5); 1687 1688 s->Config5 = val; 1689 } 1690 1691 static uint32_t rtl8139_Config5_read(RTL8139State *s) 1692 { 1693 uint32_t ret = s->Config5; 1694 1695 DPRINTF("Config5 read val=0x%02x\n", ret); 1696 1697 return ret; 1698 } 1699 1700 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) 1701 { 1702 if (!rtl8139_transmitter_enabled(s)) 1703 { 1704 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val); 1705 return; 1706 } 1707 1708 DPRINTF("TxConfig write val=0x%08x\n", val); 1709 1710 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); 1711 1712 s->TxConfig = val; 1713 } 1714 1715 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) 1716 { 1717 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val); 1718 1719 uint32_t tc = s->TxConfig; 1720 tc &= 0xFFFFFF00; 1721 tc |= (val & 0x000000FF); 1722 rtl8139_TxConfig_write(s, tc); 1723 } 1724 1725 static uint32_t rtl8139_TxConfig_read(RTL8139State *s) 1726 { 1727 uint32_t ret = s->TxConfig; 1728 1729 DPRINTF("TxConfig read val=0x%04x\n", ret); 1730 1731 return ret; 1732 } 1733 1734 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) 1735 { 1736 DPRINTF("RxConfig write val=0x%08x\n", val); 1737 1738 /* mask unwritable bits */ 1739 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); 1740 1741 s->RxConfig = val; 1742 1743 /* reset buffer size and read/write pointers */ 1744 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); 1745 1746 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize); 1747 } 1748 1749 static uint32_t rtl8139_RxConfig_read(RTL8139State *s) 1750 { 1751 uint32_t ret = s->RxConfig; 1752 1753 DPRINTF("RxConfig read val=0x%08x\n", ret); 1754 1755 return ret; 1756 } 1757 1758 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, 1759 int do_interrupt, const uint8_t *dot1q_buf) 1760 { 1761 struct iovec *iov = NULL; 1762 struct iovec vlan_iov[3]; 1763 1764 if (!size) 1765 { 1766 DPRINTF("+++ empty ethernet frame\n"); 1767 return; 1768 } 1769 1770 if (dot1q_buf && size >= ETH_ALEN * 2) { 1771 iov = (struct iovec[3]) { 1772 { .iov_base = buf, .iov_len = ETH_ALEN * 2 }, 1773 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN }, 1774 { .iov_base = buf + ETH_ALEN * 2, 1775 .iov_len = size - ETH_ALEN * 2 }, 1776 }; 1777 1778 memcpy(vlan_iov, iov, sizeof(vlan_iov)); 1779 iov = vlan_iov; 1780 } 1781 1782 if (TxLoopBack == (s->TxConfig & TxLoopBack)) 1783 { 1784 size_t buf2_size; 1785 uint8_t *buf2; 1786 1787 if (iov) { 1788 buf2_size = iov_size(iov, 3); 1789 buf2 = g_malloc(buf2_size); 1790 iov_to_buf(iov, 3, 0, buf2, buf2_size); 1791 buf = buf2; 1792 } 1793 1794 DPRINTF("+++ transmit loopback mode\n"); 1795 rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt); 1796 1797 if (iov) { 1798 g_free(buf2); 1799 } 1800 } 1801 else 1802 { 1803 if (iov) { 1804 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3); 1805 } else { 1806 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 1807 } 1808 } 1809 } 1810 1811 static int rtl8139_transmit_one(RTL8139State *s, int descriptor) 1812 { 1813 if (!rtl8139_transmitter_enabled(s)) 1814 { 1815 DPRINTF("+++ cannot transmit from descriptor %d: transmitter " 1816 "disabled\n", descriptor); 1817 return 0; 1818 } 1819 1820 if (s->TxStatus[descriptor] & TxHostOwns) 1821 { 1822 DPRINTF("+++ cannot transmit from descriptor %d: owned by host " 1823 "(%08x)\n", descriptor, s->TxStatus[descriptor]); 1824 return 0; 1825 } 1826 1827 DPRINTF("+++ transmitting from descriptor %d\n", descriptor); 1828 1829 PCIDevice *d = PCI_DEVICE(s); 1830 int txsize = s->TxStatus[descriptor] & 0x1fff; 1831 uint8_t txbuffer[0x2000]; 1832 1833 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n", 1834 txsize, s->TxAddr[descriptor]); 1835 1836 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize); 1837 1838 /* Mark descriptor as transferred */ 1839 s->TxStatus[descriptor] |= TxHostOwns; 1840 s->TxStatus[descriptor] |= TxStatOK; 1841 1842 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); 1843 1844 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize, 1845 descriptor); 1846 1847 /* update interrupt */ 1848 s->IntrStatus |= TxOK; 1849 rtl8139_update_irq(s); 1850 1851 return 1; 1852 } 1853 1854 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off))) 1855 1856 /* produces ones' complement sum of data */ 1857 static uint16_t ones_complement_sum(uint8_t *data, size_t len) 1858 { 1859 uint32_t result = 0; 1860 1861 for (; len > 1; data+=2, len-=2) 1862 { 1863 result += *(uint16_t*)data; 1864 } 1865 1866 /* add the remainder byte */ 1867 if (len) 1868 { 1869 uint8_t odd[2] = {*data, 0}; 1870 result += *(uint16_t*)odd; 1871 } 1872 1873 while (result>>16) 1874 result = (result & 0xffff) + (result >> 16); 1875 1876 return result; 1877 } 1878 1879 static uint16_t ip_checksum(void *data, size_t len) 1880 { 1881 return ~ones_complement_sum((uint8_t*)data, len); 1882 } 1883 1884 static int rtl8139_cplus_transmit_one(RTL8139State *s) 1885 { 1886 if (!rtl8139_transmitter_enabled(s)) 1887 { 1888 DPRINTF("+++ C+ mode: transmitter disabled\n"); 1889 return 0; 1890 } 1891 1892 if (!rtl8139_cp_transmitter_enabled(s)) 1893 { 1894 DPRINTF("+++ C+ mode: C+ transmitter disabled\n"); 1895 return 0 ; 1896 } 1897 1898 PCIDevice *d = PCI_DEVICE(s); 1899 int descriptor = s->currCPlusTxDesc; 1900 1901 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); 1902 1903 /* Normal priority ring */ 1904 cplus_tx_ring_desc += 16 * descriptor; 1905 1906 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at " 1907 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], 1908 s->TxAddr[0], cplus_tx_ring_desc); 1909 1910 uint32_t val, txdw0,txdw1,txbufLO,txbufHI; 1911 1912 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 1913 txdw0 = le32_to_cpu(val); 1914 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4); 1915 txdw1 = le32_to_cpu(val); 1916 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4); 1917 txbufLO = le32_to_cpu(val); 1918 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4); 1919 txbufHI = le32_to_cpu(val); 1920 1921 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor, 1922 txdw0, txdw1, txbufLO, txbufHI); 1923 1924 /* w0 ownership flag */ 1925 #define CP_TX_OWN (1<<31) 1926 /* w0 end of ring flag */ 1927 #define CP_TX_EOR (1<<30) 1928 /* first segment of received packet flag */ 1929 #define CP_TX_FS (1<<29) 1930 /* last segment of received packet flag */ 1931 #define CP_TX_LS (1<<28) 1932 /* large send packet flag */ 1933 #define CP_TX_LGSEN (1<<27) 1934 /* large send MSS mask, bits 16...25 */ 1935 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) 1936 1937 /* IP checksum offload flag */ 1938 #define CP_TX_IPCS (1<<18) 1939 /* UDP checksum offload flag */ 1940 #define CP_TX_UDPCS (1<<17) 1941 /* TCP checksum offload flag */ 1942 #define CP_TX_TCPCS (1<<16) 1943 1944 /* w0 bits 0...15 : buffer size */ 1945 #define CP_TX_BUFFER_SIZE (1<<16) 1946 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) 1947 /* w1 add tag flag */ 1948 #define CP_TX_TAGC (1<<17) 1949 /* w1 bits 0...15 : VLAN tag (big endian) */ 1950 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) 1951 /* w2 low 32bit of Rx buffer ptr */ 1952 /* w3 high 32bit of Rx buffer ptr */ 1953 1954 /* set after transmission */ 1955 /* FIFO underrun flag */ 1956 #define CP_TX_STATUS_UNF (1<<25) 1957 /* transmit error summary flag, valid if set any of three below */ 1958 #define CP_TX_STATUS_TES (1<<23) 1959 /* out-of-window collision flag */ 1960 #define CP_TX_STATUS_OWC (1<<22) 1961 /* link failure flag */ 1962 #define CP_TX_STATUS_LNKF (1<<21) 1963 /* excessive collisions flag */ 1964 #define CP_TX_STATUS_EXC (1<<20) 1965 1966 if (!(txdw0 & CP_TX_OWN)) 1967 { 1968 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor); 1969 return 0 ; 1970 } 1971 1972 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor); 1973 1974 if (txdw0 & CP_TX_FS) 1975 { 1976 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment " 1977 "descriptor\n", descriptor); 1978 1979 /* reset internal buffer offset */ 1980 s->cplus_txbuffer_offset = 0; 1981 } 1982 1983 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; 1984 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); 1985 1986 /* make sure we have enough space to assemble the packet */ 1987 if (!s->cplus_txbuffer) 1988 { 1989 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; 1990 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len); 1991 s->cplus_txbuffer_offset = 0; 1992 1993 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n", 1994 s->cplus_txbuffer_len); 1995 } 1996 1997 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) 1998 { 1999 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */ 2000 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; 2001 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor" 2002 "length to %d\n", txsize); 2003 } 2004 2005 /* append more data to the packet */ 2006 2007 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at " 2008 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr, 2009 s->cplus_txbuffer_offset); 2010 2011 pci_dma_read(d, tx_addr, 2012 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); 2013 s->cplus_txbuffer_offset += txsize; 2014 2015 /* seek to next Rx descriptor */ 2016 if (txdw0 & CP_TX_EOR) 2017 { 2018 s->currCPlusTxDesc = 0; 2019 } 2020 else 2021 { 2022 ++s->currCPlusTxDesc; 2023 if (s->currCPlusTxDesc >= 64) 2024 s->currCPlusTxDesc = 0; 2025 } 2026 2027 /* transfer ownership to target */ 2028 txdw0 &= ~CP_TX_OWN; 2029 2030 /* reset error indicator bits */ 2031 txdw0 &= ~CP_TX_STATUS_UNF; 2032 txdw0 &= ~CP_TX_STATUS_TES; 2033 txdw0 &= ~CP_TX_STATUS_OWC; 2034 txdw0 &= ~CP_TX_STATUS_LNKF; 2035 txdw0 &= ~CP_TX_STATUS_EXC; 2036 2037 /* update ring data */ 2038 val = cpu_to_le32(txdw0); 2039 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 2040 2041 /* Now decide if descriptor being processed is holding the last segment of packet */ 2042 if (txdw0 & CP_TX_LS) 2043 { 2044 uint8_t dot1q_buffer_space[VLAN_HLEN]; 2045 uint16_t *dot1q_buffer; 2046 2047 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n", 2048 descriptor); 2049 2050 /* can transfer fully assembled packet */ 2051 2052 uint8_t *saved_buffer = s->cplus_txbuffer; 2053 int saved_size = s->cplus_txbuffer_offset; 2054 int saved_buffer_len = s->cplus_txbuffer_len; 2055 2056 /* create vlan tag */ 2057 if (txdw1 & CP_TX_TAGC) { 2058 /* the vlan tag is in BE byte order in the descriptor 2059 * BE + le_to_cpu() + ~swap()~ = cpu */ 2060 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", 2061 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); 2062 2063 dot1q_buffer = (uint16_t *) dot1q_buffer_space; 2064 dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN); 2065 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */ 2066 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK); 2067 } else { 2068 dot1q_buffer = NULL; 2069 } 2070 2071 /* reset the card space to protect from recursive call */ 2072 s->cplus_txbuffer = NULL; 2073 s->cplus_txbuffer_offset = 0; 2074 s->cplus_txbuffer_len = 0; 2075 2076 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) 2077 { 2078 DPRINTF("+++ C+ mode offloaded task checksum\n"); 2079 2080 /* Large enough for Ethernet and IP headers? */ 2081 if (saved_size < ETH_HLEN + sizeof(struct ip_header)) { 2082 goto skip_offload; 2083 } 2084 2085 /* ip packet header */ 2086 struct ip_header *ip = NULL; 2087 int hlen = 0; 2088 uint8_t ip_protocol = 0; 2089 uint16_t ip_data_len = 0; 2090 2091 uint8_t *eth_payload_data = NULL; 2092 size_t eth_payload_len = 0; 2093 2094 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); 2095 if (proto != ETH_P_IP) 2096 { 2097 goto skip_offload; 2098 } 2099 2100 DPRINTF("+++ C+ mode has IP packet\n"); 2101 2102 /* Note on memory alignment: eth_payload_data is 16-bit aligned 2103 * since saved_buffer is allocated with g_malloc() and ETH_HLEN is 2104 * even. 32-bit accesses must use ldl/stl wrappers to avoid 2105 * unaligned accesses. 2106 */ 2107 eth_payload_data = saved_buffer + ETH_HLEN; 2108 eth_payload_len = saved_size - ETH_HLEN; 2109 2110 ip = (struct ip_header*)eth_payload_data; 2111 2112 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) { 2113 DPRINTF("+++ C+ mode packet has bad IP version %d " 2114 "expected %d\n", IP_HEADER_VERSION(ip), 2115 IP_HEADER_VERSION_4); 2116 goto skip_offload; 2117 } 2118 2119 hlen = IP_HDR_GET_LEN(ip); 2120 if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) { 2121 goto skip_offload; 2122 } 2123 2124 ip_protocol = ip->ip_p; 2125 2126 ip_data_len = be16_to_cpu(ip->ip_len); 2127 if (ip_data_len < hlen || ip_data_len > eth_payload_len) { 2128 goto skip_offload; 2129 } 2130 ip_data_len -= hlen; 2131 2132 if (txdw0 & CP_TX_IPCS) 2133 { 2134 DPRINTF("+++ C+ mode need IP checksum\n"); 2135 2136 ip->ip_sum = 0; 2137 ip->ip_sum = ip_checksum(ip, hlen); 2138 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n", 2139 hlen, ip->ip_sum); 2140 } 2141 2142 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) 2143 { 2144 /* Large enough for the TCP header? */ 2145 if (ip_data_len < sizeof(tcp_header)) { 2146 goto skip_offload; 2147 } 2148 2149 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; 2150 2151 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d " 2152 "frame data %d specified MSS=%d\n", ETH_MTU, 2153 ip_data_len, saved_size - ETH_HLEN, large_send_mss); 2154 2155 int tcp_send_offset = 0; 2156 int send_count = 0; 2157 2158 /* maximum IP header length is 60 bytes */ 2159 uint8_t saved_ip_header[60]; 2160 2161 /* save IP header template; data area is used in tcp checksum calculation */ 2162 memcpy(saved_ip_header, eth_payload_data, hlen); 2163 2164 /* a placeholder for checksum calculation routine in tcp case */ 2165 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2166 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2167 2168 /* pointer to TCP header */ 2169 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); 2170 2171 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr); 2172 2173 /* Invalid TCP data offset? */ 2174 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) { 2175 goto skip_offload; 2176 } 2177 2178 /* ETH_MTU = ip header len + tcp header len + payload */ 2179 int tcp_data_len = ip_data_len - tcp_hlen; 2180 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen; 2181 2182 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP " 2183 "data len %d TCP chunk size %d\n", ip_data_len, 2184 tcp_hlen, tcp_data_len, tcp_chunk_size); 2185 2186 /* note the cycle below overwrites IP header data, 2187 but restores it from saved_ip_header before sending packet */ 2188 2189 int is_last_frame = 0; 2190 2191 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) 2192 { 2193 uint16_t chunk_size = tcp_chunk_size; 2194 2195 /* check if this is the last frame */ 2196 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len) 2197 { 2198 is_last_frame = 1; 2199 chunk_size = tcp_data_len - tcp_send_offset; 2200 } 2201 2202 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n", 2203 ldl_be_p(&p_tcp_hdr->th_seq)); 2204 2205 /* add 4 TCP pseudoheader fields */ 2206 /* copy IP source and destination fields */ 2207 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2208 2209 DPRINTF("+++ C+ mode TSO calculating TCP checksum for " 2210 "packet with %d bytes data\n", tcp_hlen + 2211 chunk_size); 2212 2213 if (tcp_send_offset) 2214 { 2215 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); 2216 } 2217 2218 /* keep PUSH and FIN flags only for the last frame */ 2219 if (!is_last_frame) 2220 { 2221 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN); 2222 } 2223 2224 /* recalculate TCP checksum */ 2225 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2226 p_tcpip_hdr->zeros = 0; 2227 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2228 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); 2229 2230 p_tcp_hdr->th_sum = 0; 2231 2232 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); 2233 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n", 2234 tcp_checksum); 2235 2236 p_tcp_hdr->th_sum = tcp_checksum; 2237 2238 /* restore IP header */ 2239 memcpy(eth_payload_data, saved_ip_header, hlen); 2240 2241 /* set IP data length and recalculate IP checksum */ 2242 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); 2243 2244 /* increment IP id for subsequent frames */ 2245 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); 2246 2247 ip->ip_sum = 0; 2248 ip->ip_sum = ip_checksum(eth_payload_data, hlen); 2249 DPRINTF("+++ C+ mode TSO IP header len=%d " 2250 "checksum=%04x\n", hlen, ip->ip_sum); 2251 2252 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size; 2253 DPRINTF("+++ C+ mode TSO transferring packet size " 2254 "%d\n", tso_send_size); 2255 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 2256 0, (uint8_t *) dot1q_buffer); 2257 2258 /* add transferred count to TCP sequence number */ 2259 stl_be_p(&p_tcp_hdr->th_seq, 2260 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq)); 2261 ++send_count; 2262 } 2263 2264 /* Stop sending this frame */ 2265 saved_size = 0; 2266 } 2267 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) 2268 { 2269 DPRINTF("+++ C+ mode need TCP or UDP checksum\n"); 2270 2271 /* maximum IP header length is 60 bytes */ 2272 uint8_t saved_ip_header[60]; 2273 memcpy(saved_ip_header, eth_payload_data, hlen); 2274 2275 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2276 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2277 2278 /* add 4 TCP pseudoheader fields */ 2279 /* copy IP source and destination fields */ 2280 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2281 2282 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) 2283 { 2284 DPRINTF("+++ C+ mode calculating TCP checksum for " 2285 "packet with %d bytes data\n", ip_data_len); 2286 2287 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2288 p_tcpip_hdr->zeros = 0; 2289 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2290 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2291 2292 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12); 2293 2294 p_tcp_hdr->th_sum = 0; 2295 2296 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2297 DPRINTF("+++ C+ mode TCP checksum %04x\n", 2298 tcp_checksum); 2299 2300 p_tcp_hdr->th_sum = tcp_checksum; 2301 } 2302 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) 2303 { 2304 DPRINTF("+++ C+ mode calculating UDP checksum for " 2305 "packet with %d bytes data\n", ip_data_len); 2306 2307 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; 2308 p_udpip_hdr->zeros = 0; 2309 p_udpip_hdr->ip_proto = IP_PROTO_UDP; 2310 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2311 2312 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12); 2313 2314 p_udp_hdr->uh_sum = 0; 2315 2316 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2317 DPRINTF("+++ C+ mode UDP checksum %04x\n", 2318 udp_checksum); 2319 2320 p_udp_hdr->uh_sum = udp_checksum; 2321 } 2322 2323 /* restore IP header */ 2324 memcpy(eth_payload_data, saved_ip_header, hlen); 2325 } 2326 } 2327 2328 skip_offload: 2329 /* update tally counter */ 2330 ++s->tally_counters.TxOk; 2331 2332 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size); 2333 2334 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1, 2335 (uint8_t *) dot1q_buffer); 2336 2337 /* restore card space if there was no recursion and reset offset */ 2338 if (!s->cplus_txbuffer) 2339 { 2340 s->cplus_txbuffer = saved_buffer; 2341 s->cplus_txbuffer_len = saved_buffer_len; 2342 s->cplus_txbuffer_offset = 0; 2343 } 2344 else 2345 { 2346 g_free(saved_buffer); 2347 } 2348 } 2349 else 2350 { 2351 DPRINTF("+++ C+ mode transmission continue to next descriptor\n"); 2352 } 2353 2354 return 1; 2355 } 2356 2357 static void rtl8139_cplus_transmit(RTL8139State *s) 2358 { 2359 int txcount = 0; 2360 2361 while (txcount < 64 && rtl8139_cplus_transmit_one(s)) 2362 { 2363 ++txcount; 2364 } 2365 2366 /* Mark transfer completed */ 2367 if (!txcount) 2368 { 2369 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n", 2370 s->currCPlusTxDesc); 2371 } 2372 else 2373 { 2374 /* update interrupt status */ 2375 s->IntrStatus |= TxOK; 2376 rtl8139_update_irq(s); 2377 } 2378 } 2379 2380 static void rtl8139_transmit(RTL8139State *s) 2381 { 2382 int descriptor = s->currTxDesc, txcount = 0; 2383 2384 /*while*/ 2385 if (rtl8139_transmit_one(s, descriptor)) 2386 { 2387 ++s->currTxDesc; 2388 s->currTxDesc %= 4; 2389 ++txcount; 2390 } 2391 2392 /* Mark transfer completed */ 2393 if (!txcount) 2394 { 2395 DPRINTF("transmitter queue stalled, current TxDesc = %d\n", 2396 s->currTxDesc); 2397 } 2398 } 2399 2400 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) 2401 { 2402 2403 int descriptor = txRegOffset/4; 2404 2405 /* handle C+ transmit mode register configuration */ 2406 2407 if (s->cplus_enabled) 2408 { 2409 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x " 2410 "descriptor=%d\n", txRegOffset, val, descriptor); 2411 2412 /* handle Dump Tally Counters command */ 2413 s->TxStatus[descriptor] = val; 2414 2415 if (descriptor == 0 && (val & 0x8)) 2416 { 2417 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); 2418 2419 /* dump tally counters to specified memory location */ 2420 RTL8139TallyCounters_dma_write(s, tc_addr); 2421 2422 /* mark dump completed */ 2423 s->TxStatus[0] &= ~0x8; 2424 } 2425 2426 return; 2427 } 2428 2429 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", 2430 txRegOffset, val, descriptor); 2431 2432 /* mask only reserved bits */ 2433 val &= ~0xff00c000; /* these bits are reset on write */ 2434 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); 2435 2436 s->TxStatus[descriptor] = val; 2437 2438 /* attempt to start transmission */ 2439 rtl8139_transmit(s); 2440 } 2441 2442 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[], 2443 uint32_t base, uint8_t addr, 2444 int size) 2445 { 2446 uint32_t reg = (addr - base) / 4; 2447 uint32_t offset = addr & 0x3; 2448 uint32_t ret = 0; 2449 2450 if (addr & (size - 1)) { 2451 DPRINTF("not implemented read for TxStatus/TxAddr " 2452 "addr=0x%x size=0x%x\n", addr, size); 2453 return ret; 2454 } 2455 2456 switch (size) { 2457 case 1: /* fall through */ 2458 case 2: /* fall through */ 2459 case 4: 2460 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1); 2461 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n", 2462 reg, addr, size, ret); 2463 break; 2464 default: 2465 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size); 2466 break; 2467 } 2468 2469 return ret; 2470 } 2471 2472 static uint16_t rtl8139_TSAD_read(RTL8139State *s) 2473 { 2474 uint16_t ret = 0; 2475 2476 /* Simulate TSAD, it is read only anyway */ 2477 2478 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) 2479 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) 2480 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) 2481 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) 2482 2483 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) 2484 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) 2485 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) 2486 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) 2487 2488 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) 2489 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) 2490 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) 2491 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) 2492 2493 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) 2494 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) 2495 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) 2496 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; 2497 2498 2499 DPRINTF("TSAD read val=0x%04x\n", ret); 2500 2501 return ret; 2502 } 2503 2504 static uint16_t rtl8139_CSCR_read(RTL8139State *s) 2505 { 2506 uint16_t ret = s->CSCR; 2507 2508 DPRINTF("CSCR read val=0x%04x\n", ret); 2509 2510 return ret; 2511 } 2512 2513 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) 2514 { 2515 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val); 2516 2517 s->TxAddr[txAddrOffset/4] = val; 2518 } 2519 2520 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) 2521 { 2522 uint32_t ret = s->TxAddr[txAddrOffset/4]; 2523 2524 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret); 2525 2526 return ret; 2527 } 2528 2529 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) 2530 { 2531 DPRINTF("RxBufPtr write val=0x%04x\n", val); 2532 2533 /* this value is off by 16 */ 2534 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); 2535 2536 /* more buffer space may be available so try to receive */ 2537 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 2538 2539 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", 2540 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 2541 } 2542 2543 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s) 2544 { 2545 /* this value is off by 16 */ 2546 uint32_t ret = s->RxBufPtr - 0x10; 2547 2548 DPRINTF("RxBufPtr read val=0x%04x\n", ret); 2549 2550 return ret; 2551 } 2552 2553 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s) 2554 { 2555 /* this value is NOT off by 16 */ 2556 uint32_t ret = s->RxBufAddr; 2557 2558 DPRINTF("RxBufAddr read val=0x%04x\n", ret); 2559 2560 return ret; 2561 } 2562 2563 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) 2564 { 2565 DPRINTF("RxBuf write val=0x%08x\n", val); 2566 2567 s->RxBuf = val; 2568 2569 /* may need to reset rxring here */ 2570 } 2571 2572 static uint32_t rtl8139_RxBuf_read(RTL8139State *s) 2573 { 2574 uint32_t ret = s->RxBuf; 2575 2576 DPRINTF("RxBuf read val=0x%08x\n", ret); 2577 2578 return ret; 2579 } 2580 2581 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) 2582 { 2583 DPRINTF("IntrMask write(w) val=0x%04x\n", val); 2584 2585 /* mask unwritable bits */ 2586 val = SET_MASKED(val, 0x1e00, s->IntrMask); 2587 2588 s->IntrMask = val; 2589 2590 rtl8139_update_irq(s); 2591 2592 } 2593 2594 static uint32_t rtl8139_IntrMask_read(RTL8139State *s) 2595 { 2596 uint32_t ret = s->IntrMask; 2597 2598 DPRINTF("IntrMask read(w) val=0x%04x\n", ret); 2599 2600 return ret; 2601 } 2602 2603 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) 2604 { 2605 DPRINTF("IntrStatus write(w) val=0x%04x\n", val); 2606 2607 #if 0 2608 2609 /* writing to ISR has no effect */ 2610 2611 return; 2612 2613 #else 2614 uint16_t newStatus = s->IntrStatus & ~val; 2615 2616 /* mask unwritable bits */ 2617 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); 2618 2619 /* writing 1 to interrupt status register bit clears it */ 2620 s->IntrStatus = 0; 2621 rtl8139_update_irq(s); 2622 2623 s->IntrStatus = newStatus; 2624 rtl8139_set_next_tctr_time(s); 2625 rtl8139_update_irq(s); 2626 2627 #endif 2628 } 2629 2630 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) 2631 { 2632 uint32_t ret = s->IntrStatus; 2633 2634 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret); 2635 2636 #if 0 2637 2638 /* reading ISR clears all interrupts */ 2639 s->IntrStatus = 0; 2640 2641 rtl8139_update_irq(s); 2642 2643 #endif 2644 2645 return ret; 2646 } 2647 2648 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) 2649 { 2650 DPRINTF("MultiIntr write(w) val=0x%04x\n", val); 2651 2652 /* mask unwritable bits */ 2653 val = SET_MASKED(val, 0xf000, s->MultiIntr); 2654 2655 s->MultiIntr = val; 2656 } 2657 2658 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s) 2659 { 2660 uint32_t ret = s->MultiIntr; 2661 2662 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret); 2663 2664 return ret; 2665 } 2666 2667 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) 2668 { 2669 RTL8139State *s = opaque; 2670 2671 switch (addr) 2672 { 2673 case MAC0 ... MAC0+4: 2674 s->phys[addr - MAC0] = val; 2675 break; 2676 case MAC0+5: 2677 s->phys[addr - MAC0] = val; 2678 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 2679 break; 2680 case MAC0+6 ... MAC0+7: 2681 /* reserved */ 2682 break; 2683 case MAR0 ... MAR0+7: 2684 s->mult[addr - MAR0] = val; 2685 break; 2686 case ChipCmd: 2687 rtl8139_ChipCmd_write(s, val); 2688 break; 2689 case Cfg9346: 2690 rtl8139_Cfg9346_write(s, val); 2691 break; 2692 case TxConfig: /* windows driver sometimes writes using byte-lenth call */ 2693 rtl8139_TxConfig_writeb(s, val); 2694 break; 2695 case Config0: 2696 rtl8139_Config0_write(s, val); 2697 break; 2698 case Config1: 2699 rtl8139_Config1_write(s, val); 2700 break; 2701 case Config3: 2702 rtl8139_Config3_write(s, val); 2703 break; 2704 case Config4: 2705 rtl8139_Config4_write(s, val); 2706 break; 2707 case Config5: 2708 rtl8139_Config5_write(s, val); 2709 break; 2710 case MediaStatus: 2711 /* ignore */ 2712 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n", 2713 val); 2714 break; 2715 2716 case HltClk: 2717 DPRINTF("HltClk write val=0x%08x\n", val); 2718 if (val == 'R') 2719 { 2720 s->clock_enabled = 1; 2721 } 2722 else if (val == 'H') 2723 { 2724 s->clock_enabled = 0; 2725 } 2726 break; 2727 2728 case TxThresh: 2729 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val); 2730 s->TxThresh = val; 2731 break; 2732 2733 case TxPoll: 2734 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val); 2735 if (val & (1 << 7)) 2736 { 2737 DPRINTF("C+ TxPoll high priority transmission (not " 2738 "implemented)\n"); 2739 //rtl8139_cplus_transmit(s); 2740 } 2741 if (val & (1 << 6)) 2742 { 2743 DPRINTF("C+ TxPoll normal priority transmission\n"); 2744 rtl8139_cplus_transmit(s); 2745 } 2746 2747 break; 2748 2749 default: 2750 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr, 2751 val); 2752 break; 2753 } 2754 } 2755 2756 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) 2757 { 2758 RTL8139State *s = opaque; 2759 2760 switch (addr) 2761 { 2762 case IntrMask: 2763 rtl8139_IntrMask_write(s, val); 2764 break; 2765 2766 case IntrStatus: 2767 rtl8139_IntrStatus_write(s, val); 2768 break; 2769 2770 case MultiIntr: 2771 rtl8139_MultiIntr_write(s, val); 2772 break; 2773 2774 case RxBufPtr: 2775 rtl8139_RxBufPtr_write(s, val); 2776 break; 2777 2778 case BasicModeCtrl: 2779 rtl8139_BasicModeCtrl_write(s, val); 2780 break; 2781 case BasicModeStatus: 2782 rtl8139_BasicModeStatus_write(s, val); 2783 break; 2784 case NWayAdvert: 2785 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val); 2786 s->NWayAdvert = val; 2787 break; 2788 case NWayLPAR: 2789 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val); 2790 break; 2791 case NWayExpansion: 2792 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val); 2793 s->NWayExpansion = val; 2794 break; 2795 2796 case CpCmd: 2797 rtl8139_CpCmd_write(s, val); 2798 break; 2799 2800 case IntrMitigate: 2801 rtl8139_IntrMitigate_write(s, val); 2802 break; 2803 2804 default: 2805 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n", 2806 addr, val); 2807 2808 rtl8139_io_writeb(opaque, addr, val & 0xff); 2809 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2810 break; 2811 } 2812 } 2813 2814 static void rtl8139_set_next_tctr_time(RTL8139State *s) 2815 { 2816 const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32; 2817 2818 DPRINTF("entered rtl8139_set_next_tctr_time\n"); 2819 2820 /* This function is called at least once per period, so it is a good 2821 * place to update the timer base. 2822 * 2823 * After one iteration of this loop the value in the Timer register does 2824 * not change, but the device model is counting up by 2^32 ticks (approx. 2825 * 130 seconds). 2826 */ 2827 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2828 s->TCTR_base += ns_per_period; 2829 } 2830 2831 if (!s->TimerInt) { 2832 timer_del(s->timer); 2833 } else { 2834 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD; 2835 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2836 delta += ns_per_period; 2837 } 2838 timer_mod(s->timer, s->TCTR_base + delta); 2839 } 2840 } 2841 2842 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) 2843 { 2844 RTL8139State *s = opaque; 2845 2846 switch (addr) 2847 { 2848 case RxMissed: 2849 DPRINTF("RxMissed clearing on write\n"); 2850 s->RxMissed = 0; 2851 break; 2852 2853 case TxConfig: 2854 rtl8139_TxConfig_write(s, val); 2855 break; 2856 2857 case RxConfig: 2858 rtl8139_RxConfig_write(s, val); 2859 break; 2860 2861 case TxStatus0 ... TxStatus0+4*4-1: 2862 rtl8139_TxStatus_write(s, addr-TxStatus0, val); 2863 break; 2864 2865 case TxAddr0 ... TxAddr0+4*4-1: 2866 rtl8139_TxAddr_write(s, addr-TxAddr0, val); 2867 break; 2868 2869 case RxBuf: 2870 rtl8139_RxBuf_write(s, val); 2871 break; 2872 2873 case RxRingAddrLO: 2874 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val); 2875 s->RxRingAddrLO = val; 2876 break; 2877 2878 case RxRingAddrHI: 2879 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val); 2880 s->RxRingAddrHI = val; 2881 break; 2882 2883 case Timer: 2884 DPRINTF("TCTR Timer reset on write\n"); 2885 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2886 rtl8139_set_next_tctr_time(s); 2887 break; 2888 2889 case FlashReg: 2890 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val); 2891 if (s->TimerInt != val) { 2892 s->TimerInt = val; 2893 rtl8139_set_next_tctr_time(s); 2894 } 2895 break; 2896 2897 default: 2898 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n", 2899 addr, val); 2900 rtl8139_io_writeb(opaque, addr, val & 0xff); 2901 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2902 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); 2903 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); 2904 break; 2905 } 2906 } 2907 2908 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) 2909 { 2910 RTL8139State *s = opaque; 2911 int ret; 2912 2913 switch (addr) 2914 { 2915 case MAC0 ... MAC0+5: 2916 ret = s->phys[addr - MAC0]; 2917 break; 2918 case MAC0+6 ... MAC0+7: 2919 ret = 0; 2920 break; 2921 case MAR0 ... MAR0+7: 2922 ret = s->mult[addr - MAR0]; 2923 break; 2924 case TxStatus0 ... TxStatus0+4*4-1: 2925 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 2926 addr, 1); 2927 break; 2928 case ChipCmd: 2929 ret = rtl8139_ChipCmd_read(s); 2930 break; 2931 case Cfg9346: 2932 ret = rtl8139_Cfg9346_read(s); 2933 break; 2934 case Config0: 2935 ret = rtl8139_Config0_read(s); 2936 break; 2937 case Config1: 2938 ret = rtl8139_Config1_read(s); 2939 break; 2940 case Config3: 2941 ret = rtl8139_Config3_read(s); 2942 break; 2943 case Config4: 2944 ret = rtl8139_Config4_read(s); 2945 break; 2946 case Config5: 2947 ret = rtl8139_Config5_read(s); 2948 break; 2949 2950 case MediaStatus: 2951 /* The LinkDown bit of MediaStatus is inverse with link status */ 2952 ret = 0xd0 | (~s->BasicModeStatus & 0x04); 2953 DPRINTF("MediaStatus read 0x%x\n", ret); 2954 break; 2955 2956 case HltClk: 2957 ret = s->clock_enabled; 2958 DPRINTF("HltClk read 0x%x\n", ret); 2959 break; 2960 2961 case PCIRevisionID: 2962 ret = RTL8139_PCI_REVID; 2963 DPRINTF("PCI Revision ID read 0x%x\n", ret); 2964 break; 2965 2966 case TxThresh: 2967 ret = s->TxThresh; 2968 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret); 2969 break; 2970 2971 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ 2972 ret = s->TxConfig >> 24; 2973 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret); 2974 break; 2975 2976 default: 2977 DPRINTF("not implemented read(b) addr=0x%x\n", addr); 2978 ret = 0; 2979 break; 2980 } 2981 2982 return ret; 2983 } 2984 2985 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) 2986 { 2987 RTL8139State *s = opaque; 2988 uint32_t ret; 2989 2990 switch (addr) 2991 { 2992 case TxAddr0 ... TxAddr0+4*4-1: 2993 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2); 2994 break; 2995 case IntrMask: 2996 ret = rtl8139_IntrMask_read(s); 2997 break; 2998 2999 case IntrStatus: 3000 ret = rtl8139_IntrStatus_read(s); 3001 break; 3002 3003 case MultiIntr: 3004 ret = rtl8139_MultiIntr_read(s); 3005 break; 3006 3007 case RxBufPtr: 3008 ret = rtl8139_RxBufPtr_read(s); 3009 break; 3010 3011 case RxBufAddr: 3012 ret = rtl8139_RxBufAddr_read(s); 3013 break; 3014 3015 case BasicModeCtrl: 3016 ret = rtl8139_BasicModeCtrl_read(s); 3017 break; 3018 case BasicModeStatus: 3019 ret = rtl8139_BasicModeStatus_read(s); 3020 break; 3021 case NWayAdvert: 3022 ret = s->NWayAdvert; 3023 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret); 3024 break; 3025 case NWayLPAR: 3026 ret = s->NWayLPAR; 3027 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret); 3028 break; 3029 case NWayExpansion: 3030 ret = s->NWayExpansion; 3031 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret); 3032 break; 3033 3034 case CpCmd: 3035 ret = rtl8139_CpCmd_read(s); 3036 break; 3037 3038 case IntrMitigate: 3039 ret = rtl8139_IntrMitigate_read(s); 3040 break; 3041 3042 case TxSummary: 3043 ret = rtl8139_TSAD_read(s); 3044 break; 3045 3046 case CSCR: 3047 ret = rtl8139_CSCR_read(s); 3048 break; 3049 3050 default: 3051 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr); 3052 3053 ret = rtl8139_io_readb(opaque, addr); 3054 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3055 3056 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret); 3057 break; 3058 } 3059 3060 return ret; 3061 } 3062 3063 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) 3064 { 3065 RTL8139State *s = opaque; 3066 uint32_t ret; 3067 3068 switch (addr) 3069 { 3070 case RxMissed: 3071 ret = s->RxMissed; 3072 3073 DPRINTF("RxMissed read val=0x%08x\n", ret); 3074 break; 3075 3076 case TxConfig: 3077 ret = rtl8139_TxConfig_read(s); 3078 break; 3079 3080 case RxConfig: 3081 ret = rtl8139_RxConfig_read(s); 3082 break; 3083 3084 case TxStatus0 ... TxStatus0+4*4-1: 3085 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 3086 addr, 4); 3087 break; 3088 3089 case TxAddr0 ... TxAddr0+4*4-1: 3090 ret = rtl8139_TxAddr_read(s, addr-TxAddr0); 3091 break; 3092 3093 case RxBuf: 3094 ret = rtl8139_RxBuf_read(s); 3095 break; 3096 3097 case RxRingAddrLO: 3098 ret = s->RxRingAddrLO; 3099 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret); 3100 break; 3101 3102 case RxRingAddrHI: 3103 ret = s->RxRingAddrHI; 3104 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret); 3105 break; 3106 3107 case Timer: 3108 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) / 3109 PCI_PERIOD; 3110 DPRINTF("TCTR Timer read val=0x%08x\n", ret); 3111 break; 3112 3113 case FlashReg: 3114 ret = s->TimerInt; 3115 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret); 3116 break; 3117 3118 default: 3119 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr); 3120 3121 ret = rtl8139_io_readb(opaque, addr); 3122 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3123 ret |= rtl8139_io_readb(opaque, addr + 2) << 16; 3124 ret |= rtl8139_io_readb(opaque, addr + 3) << 24; 3125 3126 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret); 3127 break; 3128 } 3129 3130 return ret; 3131 } 3132 3133 /* */ 3134 3135 static int rtl8139_post_load(void *opaque, int version_id) 3136 { 3137 RTL8139State* s = opaque; 3138 rtl8139_set_next_tctr_time(s); 3139 if (version_id < 4) { 3140 s->cplus_enabled = s->CpCmd != 0; 3141 } 3142 3143 /* nc.link_down can't be migrated, so infer link_down according 3144 * to link status bit in BasicModeStatus */ 3145 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0; 3146 3147 return 0; 3148 } 3149 3150 static bool rtl8139_hotplug_ready_needed(void *opaque) 3151 { 3152 return qdev_machine_modified(); 3153 } 3154 3155 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ 3156 .name = "rtl8139/hotplug_ready", 3157 .version_id = 1, 3158 .minimum_version_id = 1, 3159 .needed = rtl8139_hotplug_ready_needed, 3160 .fields = (VMStateField[]) { 3161 VMSTATE_END_OF_LIST() 3162 } 3163 }; 3164 3165 static void rtl8139_pre_save(void *opaque) 3166 { 3167 RTL8139State* s = opaque; 3168 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 3169 3170 /* for migration to older versions */ 3171 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD; 3172 s->rtl8139_mmio_io_addr_dummy = 0; 3173 } 3174 3175 static const VMStateDescription vmstate_rtl8139 = { 3176 .name = "rtl8139", 3177 .version_id = 5, 3178 .minimum_version_id = 3, 3179 .post_load = rtl8139_post_load, 3180 .pre_save = rtl8139_pre_save, 3181 .fields = (VMStateField[]) { 3182 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State), 3183 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6), 3184 VMSTATE_BUFFER(mult, RTL8139State), 3185 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4), 3186 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4), 3187 3188 VMSTATE_UINT32(RxBuf, RTL8139State), 3189 VMSTATE_UINT32(RxBufferSize, RTL8139State), 3190 VMSTATE_UINT32(RxBufPtr, RTL8139State), 3191 VMSTATE_UINT32(RxBufAddr, RTL8139State), 3192 3193 VMSTATE_UINT16(IntrStatus, RTL8139State), 3194 VMSTATE_UINT16(IntrMask, RTL8139State), 3195 3196 VMSTATE_UINT32(TxConfig, RTL8139State), 3197 VMSTATE_UINT32(RxConfig, RTL8139State), 3198 VMSTATE_UINT32(RxMissed, RTL8139State), 3199 VMSTATE_UINT16(CSCR, RTL8139State), 3200 3201 VMSTATE_UINT8(Cfg9346, RTL8139State), 3202 VMSTATE_UINT8(Config0, RTL8139State), 3203 VMSTATE_UINT8(Config1, RTL8139State), 3204 VMSTATE_UINT8(Config3, RTL8139State), 3205 VMSTATE_UINT8(Config4, RTL8139State), 3206 VMSTATE_UINT8(Config5, RTL8139State), 3207 3208 VMSTATE_UINT8(clock_enabled, RTL8139State), 3209 VMSTATE_UINT8(bChipCmdState, RTL8139State), 3210 3211 VMSTATE_UINT16(MultiIntr, RTL8139State), 3212 3213 VMSTATE_UINT16(BasicModeCtrl, RTL8139State), 3214 VMSTATE_UINT16(BasicModeStatus, RTL8139State), 3215 VMSTATE_UINT16(NWayAdvert, RTL8139State), 3216 VMSTATE_UINT16(NWayLPAR, RTL8139State), 3217 VMSTATE_UINT16(NWayExpansion, RTL8139State), 3218 3219 VMSTATE_UINT16(CpCmd, RTL8139State), 3220 VMSTATE_UINT8(TxThresh, RTL8139State), 3221 3222 VMSTATE_UNUSED(4), 3223 VMSTATE_MACADDR(conf.macaddr, RTL8139State), 3224 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), 3225 3226 VMSTATE_UINT32(currTxDesc, RTL8139State), 3227 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), 3228 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), 3229 VMSTATE_UINT32(RxRingAddrLO, RTL8139State), 3230 VMSTATE_UINT32(RxRingAddrHI, RTL8139State), 3231 3232 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), 3233 VMSTATE_INT32(eeprom.mode, RTL8139State), 3234 VMSTATE_UINT32(eeprom.tick, RTL8139State), 3235 VMSTATE_UINT8(eeprom.address, RTL8139State), 3236 VMSTATE_UINT16(eeprom.input, RTL8139State), 3237 VMSTATE_UINT16(eeprom.output, RTL8139State), 3238 3239 VMSTATE_UINT8(eeprom.eecs, RTL8139State), 3240 VMSTATE_UINT8(eeprom.eesk, RTL8139State), 3241 VMSTATE_UINT8(eeprom.eedi, RTL8139State), 3242 VMSTATE_UINT8(eeprom.eedo, RTL8139State), 3243 3244 VMSTATE_UINT32(TCTR, RTL8139State), 3245 VMSTATE_UINT32(TimerInt, RTL8139State), 3246 VMSTATE_INT64(TCTR_base, RTL8139State), 3247 3248 VMSTATE_UINT64(tally_counters.TxOk, RTL8139State), 3249 VMSTATE_UINT64(tally_counters.RxOk, RTL8139State), 3250 VMSTATE_UINT64(tally_counters.TxERR, RTL8139State), 3251 VMSTATE_UINT32(tally_counters.RxERR, RTL8139State), 3252 VMSTATE_UINT16(tally_counters.MissPkt, RTL8139State), 3253 VMSTATE_UINT16(tally_counters.FAE, RTL8139State), 3254 VMSTATE_UINT32(tally_counters.Tx1Col, RTL8139State), 3255 VMSTATE_UINT32(tally_counters.TxMCol, RTL8139State), 3256 VMSTATE_UINT64(tally_counters.RxOkPhy, RTL8139State), 3257 VMSTATE_UINT64(tally_counters.RxOkBrd, RTL8139State), 3258 VMSTATE_UINT32_V(tally_counters.RxOkMul, RTL8139State, 5), 3259 VMSTATE_UINT16(tally_counters.TxAbt, RTL8139State), 3260 VMSTATE_UINT16(tally_counters.TxUndrn, RTL8139State), 3261 3262 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4), 3263 VMSTATE_END_OF_LIST() 3264 }, 3265 .subsections = (const VMStateDescription*[]) { 3266 &vmstate_rtl8139_hotplug_ready, 3267 NULL 3268 } 3269 }; 3270 3271 /***********************************************************/ 3272 /* PCI RTL8139 definitions */ 3273 3274 static void rtl8139_ioport_write(void *opaque, hwaddr addr, 3275 uint64_t val, unsigned size) 3276 { 3277 switch (size) { 3278 case 1: 3279 rtl8139_io_writeb(opaque, addr, val); 3280 break; 3281 case 2: 3282 rtl8139_io_writew(opaque, addr, val); 3283 break; 3284 case 4: 3285 rtl8139_io_writel(opaque, addr, val); 3286 break; 3287 } 3288 } 3289 3290 static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr, 3291 unsigned size) 3292 { 3293 switch (size) { 3294 case 1: 3295 return rtl8139_io_readb(opaque, addr); 3296 case 2: 3297 return rtl8139_io_readw(opaque, addr); 3298 case 4: 3299 return rtl8139_io_readl(opaque, addr); 3300 } 3301 3302 return -1; 3303 } 3304 3305 static const MemoryRegionOps rtl8139_io_ops = { 3306 .read = rtl8139_ioport_read, 3307 .write = rtl8139_ioport_write, 3308 .impl = { 3309 .min_access_size = 1, 3310 .max_access_size = 4, 3311 }, 3312 .endianness = DEVICE_LITTLE_ENDIAN, 3313 }; 3314 3315 static void rtl8139_timer(void *opaque) 3316 { 3317 RTL8139State *s = opaque; 3318 3319 if (!s->clock_enabled) 3320 { 3321 DPRINTF(">>> timer: clock is not running\n"); 3322 return; 3323 } 3324 3325 s->IntrStatus |= PCSTimeout; 3326 rtl8139_update_irq(s); 3327 rtl8139_set_next_tctr_time(s); 3328 } 3329 3330 static void pci_rtl8139_uninit(PCIDevice *dev) 3331 { 3332 RTL8139State *s = RTL8139(dev); 3333 3334 g_free(s->cplus_txbuffer); 3335 s->cplus_txbuffer = NULL; 3336 timer_del(s->timer); 3337 timer_free(s->timer); 3338 qemu_del_nic(s->nic); 3339 } 3340 3341 static void rtl8139_set_link_status(NetClientState *nc) 3342 { 3343 RTL8139State *s = qemu_get_nic_opaque(nc); 3344 3345 if (nc->link_down) { 3346 s->BasicModeStatus &= ~0x04; 3347 } else { 3348 s->BasicModeStatus |= 0x04; 3349 } 3350 3351 s->IntrStatus |= RxUnderrun; 3352 rtl8139_update_irq(s); 3353 } 3354 3355 static NetClientInfo net_rtl8139_info = { 3356 .type = NET_CLIENT_DRIVER_NIC, 3357 .size = sizeof(NICState), 3358 .can_receive = rtl8139_can_receive, 3359 .receive = rtl8139_receive, 3360 .link_status_changed = rtl8139_set_link_status, 3361 }; 3362 3363 static void pci_rtl8139_realize(PCIDevice *dev, Error **errp) 3364 { 3365 RTL8139State *s = RTL8139(dev); 3366 DeviceState *d = DEVICE(dev); 3367 uint8_t *pci_conf; 3368 3369 pci_conf = dev->config; 3370 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 3371 /* TODO: start of capability list, but no capability 3372 * list bit in status register, and offset 0xdc seems unused. */ 3373 pci_conf[PCI_CAPABILITY_LIST] = 0xdc; 3374 3375 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s, 3376 "rtl8139", 0x100); 3377 memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io, 3378 0, 0x100); 3379 3380 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io); 3381 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem); 3382 3383 qemu_macaddr_default_if_unset(&s->conf.macaddr); 3384 3385 /* prepare eeprom */ 3386 s->eeprom.contents[0] = 0x8129; 3387 #if 1 3388 /* PCI vendor and device ID should be mirrored here */ 3389 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK; 3390 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139; 3391 #endif 3392 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; 3393 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; 3394 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; 3395 3396 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, 3397 object_get_typename(OBJECT(dev)), d->id, s); 3398 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 3399 3400 s->cplus_txbuffer = NULL; 3401 s->cplus_txbuffer_len = 0; 3402 s->cplus_txbuffer_offset = 0; 3403 3404 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s); 3405 } 3406 3407 static void rtl8139_instance_init(Object *obj) 3408 { 3409 RTL8139State *s = RTL8139(obj); 3410 3411 device_add_bootindex_property(obj, &s->conf.bootindex, 3412 "bootindex", "/ethernet-phy@0", 3413 DEVICE(obj), NULL); 3414 } 3415 3416 static Property rtl8139_properties[] = { 3417 DEFINE_NIC_PROPERTIES(RTL8139State, conf), 3418 DEFINE_PROP_END_OF_LIST(), 3419 }; 3420 3421 static void rtl8139_class_init(ObjectClass *klass, void *data) 3422 { 3423 DeviceClass *dc = DEVICE_CLASS(klass); 3424 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3425 3426 k->realize = pci_rtl8139_realize; 3427 k->exit = pci_rtl8139_uninit; 3428 k->romfile = "efi-rtl8139.rom"; 3429 k->vendor_id = PCI_VENDOR_ID_REALTEK; 3430 k->device_id = PCI_DEVICE_ID_REALTEK_8139; 3431 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */ 3432 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 3433 dc->reset = rtl8139_reset; 3434 dc->vmsd = &vmstate_rtl8139; 3435 dc->props = rtl8139_properties; 3436 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 3437 } 3438 3439 static const TypeInfo rtl8139_info = { 3440 .name = TYPE_RTL8139, 3441 .parent = TYPE_PCI_DEVICE, 3442 .instance_size = sizeof(RTL8139State), 3443 .class_init = rtl8139_class_init, 3444 .instance_init = rtl8139_instance_init, 3445 }; 3446 3447 static void rtl8139_register_types(void) 3448 { 3449 type_register_static(&rtl8139_info); 3450 } 3451 3452 type_init(rtl8139_register_types) 3453