1 /** 2 * QEMU RTL8139 emulation 3 * 4 * Copyright (c) 2006 Igor Kovalenko 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 24 * Modifications: 25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver) 26 * 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver 28 * HW revision ID changes for FreeBSD driver 29 * 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver 31 * Corrected packet transfer reassembly routine for 8139C+ mode 32 * Rearranged debugging print statements 33 * Implemented PCI timer interrupt (disabled by default) 34 * Implemented Tally Counters, increased VM load/save version 35 * Implemented IP/TCP/UDP checksum task offloading 36 * 37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading 38 * Fixed MTU=1500 for produced ethernet frames 39 * 40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing 41 * segmentation offloading 42 * Removed slirp.h dependency 43 * Added rx/tx buffer reset when enabling rx/tx operation 44 * 45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only 46 * when strictly needed (required for 47 * Darwin) 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading 49 */ 50 51 /* For crc32 */ 52 #include "qemu/osdep.h" 53 #include <zlib.h> 54 55 #include "hw/hw.h" 56 #include "hw/pci/pci.h" 57 #include "sysemu/dma.h" 58 #include "qemu/timer.h" 59 #include "net/net.h" 60 #include "net/eth.h" 61 #include "sysemu/sysemu.h" 62 63 /* debug RTL8139 card */ 64 //#define DEBUG_RTL8139 1 65 66 #define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */ 67 68 #define SET_MASKED(input, mask, curr) \ 69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) 70 71 /* arg % size for size which is a power of 2 */ 72 #define MOD2(input, size) \ 73 ( ( input ) & ( size - 1 ) ) 74 75 #define ETHER_TYPE_LEN 2 76 #define ETH_MTU 1500 77 78 #define VLAN_TCI_LEN 2 79 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) 80 81 #if defined (DEBUG_RTL8139) 82 # define DPRINTF(fmt, ...) \ 83 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) 84 #else 85 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...) 86 { 87 return 0; 88 } 89 #endif 90 91 #define TYPE_RTL8139 "rtl8139" 92 93 #define RTL8139(obj) \ 94 OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139) 95 96 /* Symbolic offsets to registers. */ 97 enum RTL8139_registers { 98 MAC0 = 0, /* Ethernet hardware address. */ 99 MAR0 = 8, /* Multicast filter. */ 100 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ 101 /* Dump Tally Conter control register(64bit). C+ mode only */ 102 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 103 RxBuf = 0x30, 104 ChipCmd = 0x37, 105 RxBufPtr = 0x38, 106 RxBufAddr = 0x3A, 107 IntrMask = 0x3C, 108 IntrStatus = 0x3E, 109 TxConfig = 0x40, 110 RxConfig = 0x44, 111 Timer = 0x48, /* A general-purpose counter. */ 112 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 113 Cfg9346 = 0x50, 114 Config0 = 0x51, 115 Config1 = 0x52, 116 FlashReg = 0x54, 117 MediaStatus = 0x58, 118 Config3 = 0x59, 119 Config4 = 0x5A, /* absent on RTL-8139A */ 120 HltClk = 0x5B, 121 MultiIntr = 0x5C, 122 PCIRevisionID = 0x5E, 123 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ 124 BasicModeCtrl = 0x62, 125 BasicModeStatus = 0x64, 126 NWayAdvert = 0x66, 127 NWayLPAR = 0x68, 128 NWayExpansion = 0x6A, 129 /* Undocumented registers, but required for proper operation. */ 130 FIFOTMS = 0x70, /* FIFO Control and test. */ 131 CSCR = 0x74, /* Chip Status and Configuration Register. */ 132 PARA78 = 0x78, 133 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 134 Config5 = 0xD8, /* absent on RTL-8139A */ 135 /* C+ mode */ 136 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ 137 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ 138 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ 139 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ 140 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ 141 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ 142 TxThresh = 0xEC, /* Early Tx threshold */ 143 }; 144 145 enum ClearBitMasks { 146 MultiIntrClear = 0xF000, 147 ChipCmdClear = 0xE2, 148 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 149 }; 150 151 enum ChipCmdBits { 152 CmdReset = 0x10, 153 CmdRxEnb = 0x08, 154 CmdTxEnb = 0x04, 155 RxBufEmpty = 0x01, 156 }; 157 158 /* C+ mode */ 159 enum CplusCmdBits { 160 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ 161 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ 162 CPlusRxEnb = 0x0002, 163 CPlusTxEnb = 0x0001, 164 }; 165 166 /* Interrupt register bits, using my own meaningful names. */ 167 enum IntrStatusBits { 168 PCIErr = 0x8000, 169 PCSTimeout = 0x4000, 170 RxFIFOOver = 0x40, 171 RxUnderrun = 0x20, /* Packet Underrun / Link Change */ 172 RxOverflow = 0x10, 173 TxErr = 0x08, 174 TxOK = 0x04, 175 RxErr = 0x02, 176 RxOK = 0x01, 177 178 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 179 }; 180 181 enum TxStatusBits { 182 TxHostOwns = 0x2000, 183 TxUnderrun = 0x4000, 184 TxStatOK = 0x8000, 185 TxOutOfWindow = 0x20000000, 186 TxAborted = 0x40000000, 187 TxCarrierLost = 0x80000000, 188 }; 189 enum RxStatusBits { 190 RxMulticast = 0x8000, 191 RxPhysical = 0x4000, 192 RxBroadcast = 0x2000, 193 RxBadSymbol = 0x0020, 194 RxRunt = 0x0010, 195 RxTooLong = 0x0008, 196 RxCRCErr = 0x0004, 197 RxBadAlign = 0x0002, 198 RxStatusOK = 0x0001, 199 }; 200 201 /* Bits in RxConfig. */ 202 enum rx_mode_bits { 203 AcceptErr = 0x20, 204 AcceptRunt = 0x10, 205 AcceptBroadcast = 0x08, 206 AcceptMulticast = 0x04, 207 AcceptMyPhys = 0x02, 208 AcceptAllPhys = 0x01, 209 }; 210 211 /* Bits in TxConfig. */ 212 enum tx_config_bits { 213 214 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 215 TxIFGShift = 24, 216 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 217 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 218 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 219 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 220 221 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 222 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ 223 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 224 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ 225 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ 226 227 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 228 }; 229 230 231 /* Transmit Status of All Descriptors (TSAD) Register */ 232 enum TSAD_bits { 233 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 234 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 235 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 236 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 237 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 238 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 239 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 240 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 241 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 242 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 243 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 244 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 245 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 246 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 247 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 248 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 249 }; 250 251 252 /* Bits in Config1 */ 253 enum Config1Bits { 254 Cfg1_PM_Enable = 0x01, 255 Cfg1_VPD_Enable = 0x02, 256 Cfg1_PIO = 0x04, 257 Cfg1_MMIO = 0x08, 258 LWAKE = 0x10, /* not on 8139, 8139A */ 259 Cfg1_Driver_Load = 0x20, 260 Cfg1_LED0 = 0x40, 261 Cfg1_LED1 = 0x80, 262 SLEEP = (1 << 1), /* only on 8139, 8139A */ 263 PWRDN = (1 << 0), /* only on 8139, 8139A */ 264 }; 265 266 /* Bits in Config3 */ 267 enum Config3Bits { 268 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 269 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 270 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 271 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 272 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 273 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 274 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 275 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 276 }; 277 278 /* Bits in Config4 */ 279 enum Config4Bits { 280 LWPTN = (1 << 2), /* not on 8139, 8139A */ 281 }; 282 283 /* Bits in Config5 */ 284 enum Config5Bits { 285 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 286 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 287 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 288 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ 289 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 290 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 291 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 292 }; 293 294 enum RxConfigBits { 295 /* rx fifo threshold */ 296 RxCfgFIFOShift = 13, 297 RxCfgFIFONone = (7 << RxCfgFIFOShift), 298 299 /* Max DMA burst */ 300 RxCfgDMAShift = 8, 301 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 302 303 /* rx ring buffer length */ 304 RxCfgRcv8K = 0, 305 RxCfgRcv16K = (1 << 11), 306 RxCfgRcv32K = (1 << 12), 307 RxCfgRcv64K = (1 << 11) | (1 << 12), 308 309 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 310 RxNoWrap = (1 << 7), 311 }; 312 313 /* Twister tuning parameters from RealTek. 314 Completely undocumented, but required to tune bad links on some boards. */ 315 /* 316 enum CSCRBits { 317 CSCR_LinkOKBit = 0x0400, 318 CSCR_LinkChangeBit = 0x0800, 319 CSCR_LinkStatusBits = 0x0f000, 320 CSCR_LinkDownOffCmd = 0x003c0, 321 CSCR_LinkDownCmd = 0x0f3c0, 322 */ 323 enum CSCRBits { 324 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ 325 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ 326 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ 327 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ 328 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ 329 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ 330 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ 331 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ 332 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ 333 }; 334 335 enum Cfg9346Bits { 336 Cfg9346_Normal = 0x00, 337 Cfg9346_Autoload = 0x40, 338 Cfg9346_Programming = 0x80, 339 Cfg9346_ConfigWrite = 0xC0, 340 }; 341 342 typedef enum { 343 CH_8139 = 0, 344 CH_8139_K, 345 CH_8139A, 346 CH_8139A_G, 347 CH_8139B, 348 CH_8130, 349 CH_8139C, 350 CH_8100, 351 CH_8100B_8139D, 352 CH_8101, 353 } chip_t; 354 355 enum chip_flags { 356 HasHltClk = (1 << 0), 357 HasLWake = (1 << 1), 358 }; 359 360 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 361 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 362 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 363 364 #define RTL8139_PCI_REVID_8139 0x10 365 #define RTL8139_PCI_REVID_8139CPLUS 0x20 366 367 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS 368 369 /* Size is 64 * 16bit words */ 370 #define EEPROM_9346_ADDR_BITS 6 371 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) 372 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) 373 374 enum Chip9346Operation 375 { 376 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ 377 Chip9346_op_read = 0x80, /* 10 AAAAAA */ 378 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ 379 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ 380 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ 381 Chip9346_op_write_all = 0x10, /* 00 01zzzz */ 382 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ 383 }; 384 385 enum Chip9346Mode 386 { 387 Chip9346_none = 0, 388 Chip9346_enter_command_mode, 389 Chip9346_read_command, 390 Chip9346_data_read, /* from output register */ 391 Chip9346_data_write, /* to input register, then to contents at specified address */ 392 Chip9346_data_write_all, /* to input register, then filling contents */ 393 }; 394 395 typedef struct EEprom9346 396 { 397 uint16_t contents[EEPROM_9346_SIZE]; 398 int mode; 399 uint32_t tick; 400 uint8_t address; 401 uint16_t input; 402 uint16_t output; 403 404 uint8_t eecs; 405 uint8_t eesk; 406 uint8_t eedi; 407 uint8_t eedo; 408 } EEprom9346; 409 410 typedef struct RTL8139TallyCounters 411 { 412 /* Tally counters */ 413 uint64_t TxOk; 414 uint64_t RxOk; 415 uint64_t TxERR; 416 uint32_t RxERR; 417 uint16_t MissPkt; 418 uint16_t FAE; 419 uint32_t Tx1Col; 420 uint32_t TxMCol; 421 uint64_t RxOkPhy; 422 uint64_t RxOkBrd; 423 uint32_t RxOkMul; 424 uint16_t TxAbt; 425 uint16_t TxUndrn; 426 } RTL8139TallyCounters; 427 428 /* Clears all tally counters */ 429 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); 430 431 typedef struct RTL8139State { 432 /*< private >*/ 433 PCIDevice parent_obj; 434 /*< public >*/ 435 436 uint8_t phys[8]; /* mac address */ 437 uint8_t mult[8]; /* multicast mask array */ 438 439 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ 440 uint32_t TxAddr[4]; /* TxAddr0 */ 441 uint32_t RxBuf; /* Receive buffer */ 442 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */ 443 uint32_t RxBufPtr; 444 uint32_t RxBufAddr; 445 446 uint16_t IntrStatus; 447 uint16_t IntrMask; 448 449 uint32_t TxConfig; 450 uint32_t RxConfig; 451 uint32_t RxMissed; 452 453 uint16_t CSCR; 454 455 uint8_t Cfg9346; 456 uint8_t Config0; 457 uint8_t Config1; 458 uint8_t Config3; 459 uint8_t Config4; 460 uint8_t Config5; 461 462 uint8_t clock_enabled; 463 uint8_t bChipCmdState; 464 465 uint16_t MultiIntr; 466 467 uint16_t BasicModeCtrl; 468 uint16_t BasicModeStatus; 469 uint16_t NWayAdvert; 470 uint16_t NWayLPAR; 471 uint16_t NWayExpansion; 472 473 uint16_t CpCmd; 474 uint8_t TxThresh; 475 476 NICState *nic; 477 NICConf conf; 478 479 /* C ring mode */ 480 uint32_t currTxDesc; 481 482 /* C+ mode */ 483 uint32_t cplus_enabled; 484 485 uint32_t currCPlusRxDesc; 486 uint32_t currCPlusTxDesc; 487 488 uint32_t RxRingAddrLO; 489 uint32_t RxRingAddrHI; 490 491 EEprom9346 eeprom; 492 493 uint32_t TCTR; 494 uint32_t TimerInt; 495 int64_t TCTR_base; 496 497 /* Tally counters */ 498 RTL8139TallyCounters tally_counters; 499 500 /* Non-persistent data */ 501 uint8_t *cplus_txbuffer; 502 int cplus_txbuffer_len; 503 int cplus_txbuffer_offset; 504 505 /* PCI interrupt timer */ 506 QEMUTimer *timer; 507 508 MemoryRegion bar_io; 509 MemoryRegion bar_mem; 510 511 /* Support migration to/from old versions */ 512 int rtl8139_mmio_io_addr_dummy; 513 } RTL8139State; 514 515 /* Writes tally counters to memory via DMA */ 516 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr); 517 518 static void rtl8139_set_next_tctr_time(RTL8139State *s); 519 520 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) 521 { 522 DPRINTF("eeprom command 0x%02x\n", command); 523 524 switch (command & Chip9346_op_mask) 525 { 526 case Chip9346_op_read: 527 { 528 eeprom->address = command & EEPROM_9346_ADDR_MASK; 529 eeprom->output = eeprom->contents[eeprom->address]; 530 eeprom->eedo = 0; 531 eeprom->tick = 0; 532 eeprom->mode = Chip9346_data_read; 533 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", 534 eeprom->address, eeprom->output); 535 } 536 break; 537 538 case Chip9346_op_write: 539 { 540 eeprom->address = command & EEPROM_9346_ADDR_MASK; 541 eeprom->input = 0; 542 eeprom->tick = 0; 543 eeprom->mode = Chip9346_none; /* Chip9346_data_write */ 544 DPRINTF("eeprom begin write to address 0x%02x\n", 545 eeprom->address); 546 } 547 break; 548 default: 549 eeprom->mode = Chip9346_none; 550 switch (command & Chip9346_op_ext_mask) 551 { 552 case Chip9346_op_write_enable: 553 DPRINTF("eeprom write enabled\n"); 554 break; 555 case Chip9346_op_write_all: 556 DPRINTF("eeprom begin write all\n"); 557 break; 558 case Chip9346_op_write_disable: 559 DPRINTF("eeprom write disabled\n"); 560 break; 561 } 562 break; 563 } 564 } 565 566 static void prom9346_shift_clock(EEprom9346 *eeprom) 567 { 568 int bit = eeprom->eedi?1:0; 569 570 ++ eeprom->tick; 571 572 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, 573 eeprom->eedo); 574 575 switch (eeprom->mode) 576 { 577 case Chip9346_enter_command_mode: 578 if (bit) 579 { 580 eeprom->mode = Chip9346_read_command; 581 eeprom->tick = 0; 582 eeprom->input = 0; 583 DPRINTF("eeprom: +++ synchronized, begin command read\n"); 584 } 585 break; 586 587 case Chip9346_read_command: 588 eeprom->input = (eeprom->input << 1) | (bit & 1); 589 if (eeprom->tick == 8) 590 { 591 prom9346_decode_command(eeprom, eeprom->input & 0xff); 592 } 593 break; 594 595 case Chip9346_data_read: 596 eeprom->eedo = (eeprom->output & 0x8000)?1:0; 597 eeprom->output <<= 1; 598 if (eeprom->tick == 16) 599 { 600 #if 1 601 // the FreeBSD drivers (rl and re) don't explicitly toggle 602 // CS between reads (or does setting Cfg9346 to 0 count too?), 603 // so we need to enter wait-for-command state here 604 eeprom->mode = Chip9346_enter_command_mode; 605 eeprom->input = 0; 606 eeprom->tick = 0; 607 608 DPRINTF("eeprom: +++ end of read, awaiting next command\n"); 609 #else 610 // original behaviour 611 ++eeprom->address; 612 eeprom->address &= EEPROM_9346_ADDR_MASK; 613 eeprom->output = eeprom->contents[eeprom->address]; 614 eeprom->tick = 0; 615 616 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", 617 eeprom->address, eeprom->output); 618 #endif 619 } 620 break; 621 622 case Chip9346_data_write: 623 eeprom->input = (eeprom->input << 1) | (bit & 1); 624 if (eeprom->tick == 16) 625 { 626 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n", 627 eeprom->address, eeprom->input); 628 629 eeprom->contents[eeprom->address] = eeprom->input; 630 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ 631 eeprom->tick = 0; 632 eeprom->input = 0; 633 } 634 break; 635 636 case Chip9346_data_write_all: 637 eeprom->input = (eeprom->input << 1) | (bit & 1); 638 if (eeprom->tick == 16) 639 { 640 int i; 641 for (i = 0; i < EEPROM_9346_SIZE; i++) 642 { 643 eeprom->contents[i] = eeprom->input; 644 } 645 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); 646 647 eeprom->mode = Chip9346_enter_command_mode; 648 eeprom->tick = 0; 649 eeprom->input = 0; 650 } 651 break; 652 653 default: 654 break; 655 } 656 } 657 658 static int prom9346_get_wire(RTL8139State *s) 659 { 660 EEprom9346 *eeprom = &s->eeprom; 661 if (!eeprom->eecs) 662 return 0; 663 664 return eeprom->eedo; 665 } 666 667 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */ 668 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) 669 { 670 EEprom9346 *eeprom = &s->eeprom; 671 uint8_t old_eecs = eeprom->eecs; 672 uint8_t old_eesk = eeprom->eesk; 673 674 eeprom->eecs = eecs; 675 eeprom->eesk = eesk; 676 eeprom->eedi = eedi; 677 678 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, 679 eeprom->eesk, eeprom->eedi, eeprom->eedo); 680 681 if (!old_eecs && eecs) 682 { 683 /* Synchronize start */ 684 eeprom->tick = 0; 685 eeprom->input = 0; 686 eeprom->output = 0; 687 eeprom->mode = Chip9346_enter_command_mode; 688 689 DPRINTF("=== eeprom: begin access, enter command mode\n"); 690 } 691 692 if (!eecs) 693 { 694 DPRINTF("=== eeprom: end access\n"); 695 return; 696 } 697 698 if (!old_eesk && eesk) 699 { 700 /* SK front rules */ 701 prom9346_shift_clock(eeprom); 702 } 703 } 704 705 static void rtl8139_update_irq(RTL8139State *s) 706 { 707 PCIDevice *d = PCI_DEVICE(s); 708 int isr; 709 isr = (s->IntrStatus & s->IntrMask) & 0xffff; 710 711 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, 712 s->IntrMask); 713 714 pci_set_irq(d, (isr != 0)); 715 } 716 717 static int rtl8139_RxWrap(RTL8139State *s) 718 { 719 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */ 720 return (s->RxConfig & (1 << 7)); 721 } 722 723 static int rtl8139_receiver_enabled(RTL8139State *s) 724 { 725 return s->bChipCmdState & CmdRxEnb; 726 } 727 728 static int rtl8139_transmitter_enabled(RTL8139State *s) 729 { 730 return s->bChipCmdState & CmdTxEnb; 731 } 732 733 static int rtl8139_cp_receiver_enabled(RTL8139State *s) 734 { 735 return s->CpCmd & CPlusRxEnb; 736 } 737 738 static int rtl8139_cp_transmitter_enabled(RTL8139State *s) 739 { 740 return s->CpCmd & CPlusTxEnb; 741 } 742 743 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) 744 { 745 PCIDevice *d = PCI_DEVICE(s); 746 747 if (s->RxBufAddr + size > s->RxBufferSize) 748 { 749 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); 750 751 /* write packet data */ 752 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) 753 { 754 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped); 755 756 if (size > wrapped) 757 { 758 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 759 buf, size-wrapped); 760 } 761 762 /* reset buffer pointer */ 763 s->RxBufAddr = 0; 764 765 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 766 buf + (size-wrapped), wrapped); 767 768 s->RxBufAddr = wrapped; 769 770 return; 771 } 772 } 773 774 /* non-wrapping path or overwrapping enabled */ 775 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size); 776 777 s->RxBufAddr += size; 778 } 779 780 #define MIN_BUF_SIZE 60 781 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high) 782 { 783 return low | ((uint64_t)high << 32); 784 } 785 786 /* Workaround for buggy guest driver such as linux who allocates rx 787 * rings after the receiver were enabled. */ 788 static bool rtl8139_cp_rx_valid(RTL8139State *s) 789 { 790 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0); 791 } 792 793 static int rtl8139_can_receive(NetClientState *nc) 794 { 795 RTL8139State *s = qemu_get_nic_opaque(nc); 796 int avail; 797 798 /* Receive (drop) packets if card is disabled. */ 799 if (!s->clock_enabled) 800 return 1; 801 if (!rtl8139_receiver_enabled(s)) 802 return 1; 803 804 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) { 805 /* ??? Flow control not implemented in c+ mode. 806 This is a hack to work around slirp deficiencies anyway. */ 807 return 1; 808 } else { 809 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, 810 s->RxBufferSize); 811 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow)); 812 } 813 } 814 815 static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) 816 { 817 RTL8139State *s = qemu_get_nic_opaque(nc); 818 PCIDevice *d = PCI_DEVICE(s); 819 /* size is the length of the buffer passed to the driver */ 820 int size = size_; 821 const uint8_t *dot1q_buf = NULL; 822 823 uint32_t packet_header = 0; 824 825 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; 826 static const uint8_t broadcast_macaddr[6] = 827 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 828 829 DPRINTF(">>> received len=%d\n", size); 830 831 /* test if board clock is stopped */ 832 if (!s->clock_enabled) 833 { 834 DPRINTF("stopped ==========================\n"); 835 return -1; 836 } 837 838 /* first check if receiver is enabled */ 839 840 if (!rtl8139_receiver_enabled(s)) 841 { 842 DPRINTF("receiver disabled ================\n"); 843 return -1; 844 } 845 846 /* XXX: check this */ 847 if (s->RxConfig & AcceptAllPhys) { 848 /* promiscuous: receive all */ 849 DPRINTF(">>> packet received in promiscuous mode\n"); 850 851 } else { 852 if (!memcmp(buf, broadcast_macaddr, 6)) { 853 /* broadcast address */ 854 if (!(s->RxConfig & AcceptBroadcast)) 855 { 856 DPRINTF(">>> broadcast packet rejected\n"); 857 858 /* update tally counter */ 859 ++s->tally_counters.RxERR; 860 861 return size; 862 } 863 864 packet_header |= RxBroadcast; 865 866 DPRINTF(">>> broadcast packet received\n"); 867 868 /* update tally counter */ 869 ++s->tally_counters.RxOkBrd; 870 871 } else if (buf[0] & 0x01) { 872 /* multicast */ 873 if (!(s->RxConfig & AcceptMulticast)) 874 { 875 DPRINTF(">>> multicast packet rejected\n"); 876 877 /* update tally counter */ 878 ++s->tally_counters.RxERR; 879 880 return size; 881 } 882 883 int mcast_idx = net_crc32(buf, ETH_ALEN) >> 26; 884 885 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) 886 { 887 DPRINTF(">>> multicast address mismatch\n"); 888 889 /* update tally counter */ 890 ++s->tally_counters.RxERR; 891 892 return size; 893 } 894 895 packet_header |= RxMulticast; 896 897 DPRINTF(">>> multicast packet received\n"); 898 899 /* update tally counter */ 900 ++s->tally_counters.RxOkMul; 901 902 } else if (s->phys[0] == buf[0] && 903 s->phys[1] == buf[1] && 904 s->phys[2] == buf[2] && 905 s->phys[3] == buf[3] && 906 s->phys[4] == buf[4] && 907 s->phys[5] == buf[5]) { 908 /* match */ 909 if (!(s->RxConfig & AcceptMyPhys)) 910 { 911 DPRINTF(">>> rejecting physical address matching packet\n"); 912 913 /* update tally counter */ 914 ++s->tally_counters.RxERR; 915 916 return size; 917 } 918 919 packet_header |= RxPhysical; 920 921 DPRINTF(">>> physical address matching packet received\n"); 922 923 /* update tally counter */ 924 ++s->tally_counters.RxOkPhy; 925 926 } else { 927 928 DPRINTF(">>> unknown packet\n"); 929 930 /* update tally counter */ 931 ++s->tally_counters.RxERR; 932 933 return size; 934 } 935 } 936 937 /* if too small buffer, then expand it 938 * Include some tailroom in case a vlan tag is later removed. */ 939 if (size < MIN_BUF_SIZE + VLAN_HLEN) { 940 memcpy(buf1, buf, size); 941 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size); 942 buf = buf1; 943 if (size < MIN_BUF_SIZE) { 944 size = MIN_BUF_SIZE; 945 } 946 } 947 948 if (rtl8139_cp_receiver_enabled(s)) 949 { 950 if (!rtl8139_cp_rx_valid(s)) { 951 return size; 952 } 953 954 DPRINTF("in C+ Rx mode ================\n"); 955 956 /* begin C+ receiver mode */ 957 958 /* w0 ownership flag */ 959 #define CP_RX_OWN (1<<31) 960 /* w0 end of ring flag */ 961 #define CP_RX_EOR (1<<30) 962 /* w0 bits 0...12 : buffer size */ 963 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) 964 /* w1 tag available flag */ 965 #define CP_RX_TAVA (1<<16) 966 /* w1 bits 0...15 : VLAN tag */ 967 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) 968 /* w2 low 32bit of Rx buffer ptr */ 969 /* w3 high 32bit of Rx buffer ptr */ 970 971 int descriptor = s->currCPlusRxDesc; 972 dma_addr_t cplus_rx_ring_desc; 973 974 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); 975 cplus_rx_ring_desc += 16 * descriptor; 976 977 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at " 978 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI, 979 s->RxRingAddrLO, cplus_rx_ring_desc); 980 981 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; 982 983 pci_dma_read(d, cplus_rx_ring_desc, &val, 4); 984 rxdw0 = le32_to_cpu(val); 985 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4); 986 rxdw1 = le32_to_cpu(val); 987 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4); 988 rxbufLO = le32_to_cpu(val); 989 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4); 990 rxbufHI = le32_to_cpu(val); 991 992 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", 993 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); 994 995 if (!(rxdw0 & CP_RX_OWN)) 996 { 997 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n", 998 descriptor); 999 1000 s->IntrStatus |= RxOverflow; 1001 ++s->RxMissed; 1002 1003 /* update tally counter */ 1004 ++s->tally_counters.RxERR; 1005 ++s->tally_counters.MissPkt; 1006 1007 rtl8139_update_irq(s); 1008 return size_; 1009 } 1010 1011 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; 1012 1013 /* write VLAN info to descriptor variables. */ 1014 if (s->CpCmd & CPlusRxVLAN && 1015 lduw_be_p(&buf[ETH_ALEN * 2]) == ETH_P_VLAN) { 1016 dot1q_buf = &buf[ETH_ALEN * 2]; 1017 size -= VLAN_HLEN; 1018 /* if too small buffer, use the tailroom added duing expansion */ 1019 if (size < MIN_BUF_SIZE) { 1020 size = MIN_BUF_SIZE; 1021 } 1022 1023 rxdw1 &= ~CP_RX_VLAN_TAG_MASK; 1024 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */ 1025 rxdw1 |= CP_RX_TAVA | lduw_le_p(&dot1q_buf[ETHER_TYPE_LEN]); 1026 1027 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", 1028 lduw_be_p(&dot1q_buf[ETHER_TYPE_LEN])); 1029 } else { 1030 /* reset VLAN tag flag */ 1031 rxdw1 &= ~CP_RX_TAVA; 1032 } 1033 1034 /* TODO: scatter the packet over available receive ring descriptors space */ 1035 1036 if (size+4 > rx_space) 1037 { 1038 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n", 1039 descriptor, rx_space, size); 1040 1041 s->IntrStatus |= RxOverflow; 1042 ++s->RxMissed; 1043 1044 /* update tally counter */ 1045 ++s->tally_counters.RxERR; 1046 ++s->tally_counters.MissPkt; 1047 1048 rtl8139_update_irq(s); 1049 return size_; 1050 } 1051 1052 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); 1053 1054 /* receive/copy to target memory */ 1055 if (dot1q_buf) { 1056 pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN); 1057 pci_dma_write(d, rx_addr + 2 * ETH_ALEN, 1058 buf + 2 * ETH_ALEN + VLAN_HLEN, 1059 size - 2 * ETH_ALEN); 1060 } else { 1061 pci_dma_write(d, rx_addr, buf, size); 1062 } 1063 1064 if (s->CpCmd & CPlusRxChkSum) 1065 { 1066 /* do some packet checksumming */ 1067 } 1068 1069 /* write checksum */ 1070 val = cpu_to_le32(crc32(0, buf, size_)); 1071 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4); 1072 1073 /* first segment of received packet flag */ 1074 #define CP_RX_STATUS_FS (1<<29) 1075 /* last segment of received packet flag */ 1076 #define CP_RX_STATUS_LS (1<<28) 1077 /* multicast packet flag */ 1078 #define CP_RX_STATUS_MAR (1<<26) 1079 /* physical-matching packet flag */ 1080 #define CP_RX_STATUS_PAM (1<<25) 1081 /* broadcast packet flag */ 1082 #define CP_RX_STATUS_BAR (1<<24) 1083 /* runt packet flag */ 1084 #define CP_RX_STATUS_RUNT (1<<19) 1085 /* crc error flag */ 1086 #define CP_RX_STATUS_CRC (1<<18) 1087 /* IP checksum error flag */ 1088 #define CP_RX_STATUS_IPF (1<<15) 1089 /* UDP checksum error flag */ 1090 #define CP_RX_STATUS_UDPF (1<<14) 1091 /* TCP checksum error flag */ 1092 #define CP_RX_STATUS_TCPF (1<<13) 1093 1094 /* transfer ownership to target */ 1095 rxdw0 &= ~CP_RX_OWN; 1096 1097 /* set first segment bit */ 1098 rxdw0 |= CP_RX_STATUS_FS; 1099 1100 /* set last segment bit */ 1101 rxdw0 |= CP_RX_STATUS_LS; 1102 1103 /* set received packet type flags */ 1104 if (packet_header & RxBroadcast) 1105 rxdw0 |= CP_RX_STATUS_BAR; 1106 if (packet_header & RxMulticast) 1107 rxdw0 |= CP_RX_STATUS_MAR; 1108 if (packet_header & RxPhysical) 1109 rxdw0 |= CP_RX_STATUS_PAM; 1110 1111 /* set received size */ 1112 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; 1113 rxdw0 |= (size+4); 1114 1115 /* update ring data */ 1116 val = cpu_to_le32(rxdw0); 1117 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4); 1118 val = cpu_to_le32(rxdw1); 1119 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4); 1120 1121 /* update tally counter */ 1122 ++s->tally_counters.RxOk; 1123 1124 /* seek to next Rx descriptor */ 1125 if (rxdw0 & CP_RX_EOR) 1126 { 1127 s->currCPlusRxDesc = 0; 1128 } 1129 else 1130 { 1131 ++s->currCPlusRxDesc; 1132 } 1133 1134 DPRINTF("done C+ Rx mode ----------------\n"); 1135 1136 } 1137 else 1138 { 1139 DPRINTF("in ring Rx mode ================\n"); 1140 1141 /* begin ring receiver mode */ 1142 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); 1143 1144 /* if receiver buffer is empty then avail == 0 */ 1145 1146 #define RX_ALIGN(x) (((x) + 3) & ~0x3) 1147 1148 if (avail != 0 && RX_ALIGN(size + 8) >= avail) 1149 { 1150 DPRINTF("rx overflow: rx buffer length %d head 0x%04x " 1151 "read 0x%04x === available 0x%04x need 0x%04x\n", 1152 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); 1153 1154 s->IntrStatus |= RxOverflow; 1155 ++s->RxMissed; 1156 rtl8139_update_irq(s); 1157 return 0; 1158 } 1159 1160 packet_header |= RxStatusOK; 1161 1162 packet_header |= (((size+4) << 16) & 0xffff0000); 1163 1164 /* write header */ 1165 uint32_t val = cpu_to_le32(packet_header); 1166 1167 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1168 1169 rtl8139_write_buffer(s, buf, size); 1170 1171 /* write checksum */ 1172 val = cpu_to_le32(crc32(0, buf, size)); 1173 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1174 1175 /* correct buffer write pointer */ 1176 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize); 1177 1178 /* now we can signal we have received something */ 1179 1180 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n", 1181 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 1182 } 1183 1184 s->IntrStatus |= RxOK; 1185 1186 if (do_interrupt) 1187 { 1188 rtl8139_update_irq(s); 1189 } 1190 1191 return size_; 1192 } 1193 1194 static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1195 { 1196 return rtl8139_do_receive(nc, buf, size, 1); 1197 } 1198 1199 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) 1200 { 1201 s->RxBufferSize = bufferSize; 1202 s->RxBufPtr = 0; 1203 s->RxBufAddr = 0; 1204 } 1205 1206 static void rtl8139_reset_phy(RTL8139State *s) 1207 { 1208 s->BasicModeStatus = 0x7809; 1209 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ 1210 /* preserve link state */ 1211 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04; 1212 1213 s->NWayAdvert = 0x05e1; /* all modes, full duplex */ 1214 s->NWayLPAR = 0x05e1; /* all modes, full duplex */ 1215 s->NWayExpansion = 0x0001; /* autonegotiation supported */ 1216 1217 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; 1218 } 1219 1220 static void rtl8139_reset(DeviceState *d) 1221 { 1222 RTL8139State *s = RTL8139(d); 1223 int i; 1224 1225 /* restore MAC address */ 1226 memcpy(s->phys, s->conf.macaddr.a, 6); 1227 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 1228 1229 /* reset interrupt mask */ 1230 s->IntrStatus = 0; 1231 s->IntrMask = 0; 1232 1233 rtl8139_update_irq(s); 1234 1235 /* mark all status registers as owned by host */ 1236 for (i = 0; i < 4; ++i) 1237 { 1238 s->TxStatus[i] = TxHostOwns; 1239 } 1240 1241 s->currTxDesc = 0; 1242 s->currCPlusRxDesc = 0; 1243 s->currCPlusTxDesc = 0; 1244 1245 s->RxRingAddrLO = 0; 1246 s->RxRingAddrHI = 0; 1247 1248 s->RxBuf = 0; 1249 1250 rtl8139_reset_rxring(s, 8192); 1251 1252 /* ACK the reset */ 1253 s->TxConfig = 0; 1254 1255 #if 0 1256 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk 1257 s->clock_enabled = 0; 1258 #else 1259 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake 1260 s->clock_enabled = 1; 1261 #endif 1262 1263 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; 1264 1265 /* set initial state data */ 1266 s->Config0 = 0x0; /* No boot ROM */ 1267 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ 1268 s->Config3 = 0x1; /* fast back-to-back compatible */ 1269 s->Config5 = 0x0; 1270 1271 s->CpCmd = 0x0; /* reset C+ mode */ 1272 s->cplus_enabled = 0; 1273 1274 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation 1275 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex 1276 s->BasicModeCtrl = 0x1000; // autonegotiation 1277 1278 rtl8139_reset_phy(s); 1279 1280 /* also reset timer and disable timer interrupt */ 1281 s->TCTR = 0; 1282 s->TimerInt = 0; 1283 s->TCTR_base = 0; 1284 rtl8139_set_next_tctr_time(s); 1285 1286 /* reset tally counters */ 1287 RTL8139TallyCounters_clear(&s->tally_counters); 1288 } 1289 1290 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) 1291 { 1292 counters->TxOk = 0; 1293 counters->RxOk = 0; 1294 counters->TxERR = 0; 1295 counters->RxERR = 0; 1296 counters->MissPkt = 0; 1297 counters->FAE = 0; 1298 counters->Tx1Col = 0; 1299 counters->TxMCol = 0; 1300 counters->RxOkPhy = 0; 1301 counters->RxOkBrd = 0; 1302 counters->RxOkMul = 0; 1303 counters->TxAbt = 0; 1304 counters->TxUndrn = 0; 1305 } 1306 1307 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr) 1308 { 1309 PCIDevice *d = PCI_DEVICE(s); 1310 RTL8139TallyCounters *tally_counters = &s->tally_counters; 1311 uint16_t val16; 1312 uint32_t val32; 1313 uint64_t val64; 1314 1315 val64 = cpu_to_le64(tally_counters->TxOk); 1316 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8); 1317 1318 val64 = cpu_to_le64(tally_counters->RxOk); 1319 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8); 1320 1321 val64 = cpu_to_le64(tally_counters->TxERR); 1322 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8); 1323 1324 val32 = cpu_to_le32(tally_counters->RxERR); 1325 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4); 1326 1327 val16 = cpu_to_le16(tally_counters->MissPkt); 1328 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2); 1329 1330 val16 = cpu_to_le16(tally_counters->FAE); 1331 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2); 1332 1333 val32 = cpu_to_le32(tally_counters->Tx1Col); 1334 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4); 1335 1336 val32 = cpu_to_le32(tally_counters->TxMCol); 1337 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4); 1338 1339 val64 = cpu_to_le64(tally_counters->RxOkPhy); 1340 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8); 1341 1342 val64 = cpu_to_le64(tally_counters->RxOkBrd); 1343 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8); 1344 1345 val32 = cpu_to_le32(tally_counters->RxOkMul); 1346 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4); 1347 1348 val16 = cpu_to_le16(tally_counters->TxAbt); 1349 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2); 1350 1351 val16 = cpu_to_le16(tally_counters->TxUndrn); 1352 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2); 1353 } 1354 1355 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) 1356 { 1357 DeviceState *d = DEVICE(s); 1358 1359 val &= 0xff; 1360 1361 DPRINTF("ChipCmd write val=0x%08x\n", val); 1362 1363 if (val & CmdReset) 1364 { 1365 DPRINTF("ChipCmd reset\n"); 1366 rtl8139_reset(d); 1367 } 1368 if (val & CmdRxEnb) 1369 { 1370 DPRINTF("ChipCmd enable receiver\n"); 1371 1372 s->currCPlusRxDesc = 0; 1373 } 1374 if (val & CmdTxEnb) 1375 { 1376 DPRINTF("ChipCmd enable transmitter\n"); 1377 1378 s->currCPlusTxDesc = 0; 1379 } 1380 1381 /* mask unwritable bits */ 1382 val = SET_MASKED(val, 0xe3, s->bChipCmdState); 1383 1384 /* Deassert reset pin before next read */ 1385 val &= ~CmdReset; 1386 1387 s->bChipCmdState = val; 1388 } 1389 1390 static int rtl8139_RxBufferEmpty(RTL8139State *s) 1391 { 1392 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); 1393 1394 if (unread != 0) 1395 { 1396 DPRINTF("receiver buffer data available 0x%04x\n", unread); 1397 return 0; 1398 } 1399 1400 DPRINTF("receiver buffer is empty\n"); 1401 1402 return 1; 1403 } 1404 1405 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s) 1406 { 1407 uint32_t ret = s->bChipCmdState; 1408 1409 if (rtl8139_RxBufferEmpty(s)) 1410 ret |= RxBufEmpty; 1411 1412 DPRINTF("ChipCmd read val=0x%04x\n", ret); 1413 1414 return ret; 1415 } 1416 1417 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) 1418 { 1419 val &= 0xffff; 1420 1421 DPRINTF("C+ command register write(w) val=0x%04x\n", val); 1422 1423 s->cplus_enabled = 1; 1424 1425 /* mask unwritable bits */ 1426 val = SET_MASKED(val, 0xff84, s->CpCmd); 1427 1428 s->CpCmd = val; 1429 } 1430 1431 static uint32_t rtl8139_CpCmd_read(RTL8139State *s) 1432 { 1433 uint32_t ret = s->CpCmd; 1434 1435 DPRINTF("C+ command register read(w) val=0x%04x\n", ret); 1436 1437 return ret; 1438 } 1439 1440 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) 1441 { 1442 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val); 1443 } 1444 1445 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s) 1446 { 1447 uint32_t ret = 0; 1448 1449 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret); 1450 1451 return ret; 1452 } 1453 1454 static int rtl8139_config_writable(RTL8139State *s) 1455 { 1456 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite) 1457 { 1458 return 1; 1459 } 1460 1461 DPRINTF("Configuration registers are write-protected\n"); 1462 1463 return 0; 1464 } 1465 1466 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) 1467 { 1468 val &= 0xffff; 1469 1470 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val); 1471 1472 /* mask unwritable bits */ 1473 uint32_t mask = 0xccff; 1474 1475 if (1 || !rtl8139_config_writable(s)) 1476 { 1477 /* Speed setting and autonegotiation enable bits are read-only */ 1478 mask |= 0x3000; 1479 /* Duplex mode setting is read-only */ 1480 mask |= 0x0100; 1481 } 1482 1483 if (val & 0x8000) { 1484 /* Reset PHY */ 1485 rtl8139_reset_phy(s); 1486 } 1487 1488 val = SET_MASKED(val, mask, s->BasicModeCtrl); 1489 1490 s->BasicModeCtrl = val; 1491 } 1492 1493 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s) 1494 { 1495 uint32_t ret = s->BasicModeCtrl; 1496 1497 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret); 1498 1499 return ret; 1500 } 1501 1502 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) 1503 { 1504 val &= 0xffff; 1505 1506 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val); 1507 1508 /* mask unwritable bits */ 1509 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); 1510 1511 s->BasicModeStatus = val; 1512 } 1513 1514 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s) 1515 { 1516 uint32_t ret = s->BasicModeStatus; 1517 1518 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret); 1519 1520 return ret; 1521 } 1522 1523 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) 1524 { 1525 DeviceState *d = DEVICE(s); 1526 1527 val &= 0xff; 1528 1529 DPRINTF("Cfg9346 write val=0x%02x\n", val); 1530 1531 /* mask unwritable bits */ 1532 val = SET_MASKED(val, 0x31, s->Cfg9346); 1533 1534 uint32_t opmode = val & 0xc0; 1535 uint32_t eeprom_val = val & 0xf; 1536 1537 if (opmode == 0x80) { 1538 /* eeprom access */ 1539 int eecs = (eeprom_val & 0x08)?1:0; 1540 int eesk = (eeprom_val & 0x04)?1:0; 1541 int eedi = (eeprom_val & 0x02)?1:0; 1542 prom9346_set_wire(s, eecs, eesk, eedi); 1543 } else if (opmode == 0x40) { 1544 /* Reset. */ 1545 val = 0; 1546 rtl8139_reset(d); 1547 } 1548 1549 s->Cfg9346 = val; 1550 } 1551 1552 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s) 1553 { 1554 uint32_t ret = s->Cfg9346; 1555 1556 uint32_t opmode = ret & 0xc0; 1557 1558 if (opmode == 0x80) 1559 { 1560 /* eeprom access */ 1561 int eedo = prom9346_get_wire(s); 1562 if (eedo) 1563 { 1564 ret |= 0x01; 1565 } 1566 else 1567 { 1568 ret &= ~0x01; 1569 } 1570 } 1571 1572 DPRINTF("Cfg9346 read val=0x%02x\n", ret); 1573 1574 return ret; 1575 } 1576 1577 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) 1578 { 1579 val &= 0xff; 1580 1581 DPRINTF("Config0 write val=0x%02x\n", val); 1582 1583 if (!rtl8139_config_writable(s)) { 1584 return; 1585 } 1586 1587 /* mask unwritable bits */ 1588 val = SET_MASKED(val, 0xf8, s->Config0); 1589 1590 s->Config0 = val; 1591 } 1592 1593 static uint32_t rtl8139_Config0_read(RTL8139State *s) 1594 { 1595 uint32_t ret = s->Config0; 1596 1597 DPRINTF("Config0 read val=0x%02x\n", ret); 1598 1599 return ret; 1600 } 1601 1602 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) 1603 { 1604 val &= 0xff; 1605 1606 DPRINTF("Config1 write val=0x%02x\n", val); 1607 1608 if (!rtl8139_config_writable(s)) { 1609 return; 1610 } 1611 1612 /* mask unwritable bits */ 1613 val = SET_MASKED(val, 0xC, s->Config1); 1614 1615 s->Config1 = val; 1616 } 1617 1618 static uint32_t rtl8139_Config1_read(RTL8139State *s) 1619 { 1620 uint32_t ret = s->Config1; 1621 1622 DPRINTF("Config1 read val=0x%02x\n", ret); 1623 1624 return ret; 1625 } 1626 1627 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) 1628 { 1629 val &= 0xff; 1630 1631 DPRINTF("Config3 write val=0x%02x\n", val); 1632 1633 if (!rtl8139_config_writable(s)) { 1634 return; 1635 } 1636 1637 /* mask unwritable bits */ 1638 val = SET_MASKED(val, 0x8F, s->Config3); 1639 1640 s->Config3 = val; 1641 } 1642 1643 static uint32_t rtl8139_Config3_read(RTL8139State *s) 1644 { 1645 uint32_t ret = s->Config3; 1646 1647 DPRINTF("Config3 read val=0x%02x\n", ret); 1648 1649 return ret; 1650 } 1651 1652 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) 1653 { 1654 val &= 0xff; 1655 1656 DPRINTF("Config4 write val=0x%02x\n", val); 1657 1658 if (!rtl8139_config_writable(s)) { 1659 return; 1660 } 1661 1662 /* mask unwritable bits */ 1663 val = SET_MASKED(val, 0x0a, s->Config4); 1664 1665 s->Config4 = val; 1666 } 1667 1668 static uint32_t rtl8139_Config4_read(RTL8139State *s) 1669 { 1670 uint32_t ret = s->Config4; 1671 1672 DPRINTF("Config4 read val=0x%02x\n", ret); 1673 1674 return ret; 1675 } 1676 1677 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) 1678 { 1679 val &= 0xff; 1680 1681 DPRINTF("Config5 write val=0x%02x\n", val); 1682 1683 /* mask unwritable bits */ 1684 val = SET_MASKED(val, 0x80, s->Config5); 1685 1686 s->Config5 = val; 1687 } 1688 1689 static uint32_t rtl8139_Config5_read(RTL8139State *s) 1690 { 1691 uint32_t ret = s->Config5; 1692 1693 DPRINTF("Config5 read val=0x%02x\n", ret); 1694 1695 return ret; 1696 } 1697 1698 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) 1699 { 1700 if (!rtl8139_transmitter_enabled(s)) 1701 { 1702 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val); 1703 return; 1704 } 1705 1706 DPRINTF("TxConfig write val=0x%08x\n", val); 1707 1708 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); 1709 1710 s->TxConfig = val; 1711 } 1712 1713 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) 1714 { 1715 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val); 1716 1717 uint32_t tc = s->TxConfig; 1718 tc &= 0xFFFFFF00; 1719 tc |= (val & 0x000000FF); 1720 rtl8139_TxConfig_write(s, tc); 1721 } 1722 1723 static uint32_t rtl8139_TxConfig_read(RTL8139State *s) 1724 { 1725 uint32_t ret = s->TxConfig; 1726 1727 DPRINTF("TxConfig read val=0x%04x\n", ret); 1728 1729 return ret; 1730 } 1731 1732 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) 1733 { 1734 DPRINTF("RxConfig write val=0x%08x\n", val); 1735 1736 /* mask unwritable bits */ 1737 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); 1738 1739 s->RxConfig = val; 1740 1741 /* reset buffer size and read/write pointers */ 1742 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); 1743 1744 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize); 1745 } 1746 1747 static uint32_t rtl8139_RxConfig_read(RTL8139State *s) 1748 { 1749 uint32_t ret = s->RxConfig; 1750 1751 DPRINTF("RxConfig read val=0x%08x\n", ret); 1752 1753 return ret; 1754 } 1755 1756 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, 1757 int do_interrupt, const uint8_t *dot1q_buf) 1758 { 1759 struct iovec *iov = NULL; 1760 struct iovec vlan_iov[3]; 1761 1762 if (!size) 1763 { 1764 DPRINTF("+++ empty ethernet frame\n"); 1765 return; 1766 } 1767 1768 if (dot1q_buf && size >= ETH_ALEN * 2) { 1769 iov = (struct iovec[3]) { 1770 { .iov_base = buf, .iov_len = ETH_ALEN * 2 }, 1771 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN }, 1772 { .iov_base = buf + ETH_ALEN * 2, 1773 .iov_len = size - ETH_ALEN * 2 }, 1774 }; 1775 1776 memcpy(vlan_iov, iov, sizeof(vlan_iov)); 1777 iov = vlan_iov; 1778 } 1779 1780 if (TxLoopBack == (s->TxConfig & TxLoopBack)) 1781 { 1782 size_t buf2_size; 1783 uint8_t *buf2; 1784 1785 if (iov) { 1786 buf2_size = iov_size(iov, 3); 1787 buf2 = g_malloc(buf2_size); 1788 iov_to_buf(iov, 3, 0, buf2, buf2_size); 1789 buf = buf2; 1790 } 1791 1792 DPRINTF("+++ transmit loopback mode\n"); 1793 rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt); 1794 1795 if (iov) { 1796 g_free(buf2); 1797 } 1798 } 1799 else 1800 { 1801 if (iov) { 1802 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3); 1803 } else { 1804 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 1805 } 1806 } 1807 } 1808 1809 static int rtl8139_transmit_one(RTL8139State *s, int descriptor) 1810 { 1811 if (!rtl8139_transmitter_enabled(s)) 1812 { 1813 DPRINTF("+++ cannot transmit from descriptor %d: transmitter " 1814 "disabled\n", descriptor); 1815 return 0; 1816 } 1817 1818 if (s->TxStatus[descriptor] & TxHostOwns) 1819 { 1820 DPRINTF("+++ cannot transmit from descriptor %d: owned by host " 1821 "(%08x)\n", descriptor, s->TxStatus[descriptor]); 1822 return 0; 1823 } 1824 1825 DPRINTF("+++ transmitting from descriptor %d\n", descriptor); 1826 1827 PCIDevice *d = PCI_DEVICE(s); 1828 int txsize = s->TxStatus[descriptor] & 0x1fff; 1829 uint8_t txbuffer[0x2000]; 1830 1831 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n", 1832 txsize, s->TxAddr[descriptor]); 1833 1834 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize); 1835 1836 /* Mark descriptor as transferred */ 1837 s->TxStatus[descriptor] |= TxHostOwns; 1838 s->TxStatus[descriptor] |= TxStatOK; 1839 1840 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); 1841 1842 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize, 1843 descriptor); 1844 1845 /* update interrupt */ 1846 s->IntrStatus |= TxOK; 1847 rtl8139_update_irq(s); 1848 1849 return 1; 1850 } 1851 1852 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off))) 1853 1854 /* produces ones' complement sum of data */ 1855 static uint16_t ones_complement_sum(uint8_t *data, size_t len) 1856 { 1857 uint32_t result = 0; 1858 1859 for (; len > 1; data+=2, len-=2) 1860 { 1861 result += *(uint16_t*)data; 1862 } 1863 1864 /* add the remainder byte */ 1865 if (len) 1866 { 1867 uint8_t odd[2] = {*data, 0}; 1868 result += *(uint16_t*)odd; 1869 } 1870 1871 while (result>>16) 1872 result = (result & 0xffff) + (result >> 16); 1873 1874 return result; 1875 } 1876 1877 static uint16_t ip_checksum(void *data, size_t len) 1878 { 1879 return ~ones_complement_sum((uint8_t*)data, len); 1880 } 1881 1882 static int rtl8139_cplus_transmit_one(RTL8139State *s) 1883 { 1884 if (!rtl8139_transmitter_enabled(s)) 1885 { 1886 DPRINTF("+++ C+ mode: transmitter disabled\n"); 1887 return 0; 1888 } 1889 1890 if (!rtl8139_cp_transmitter_enabled(s)) 1891 { 1892 DPRINTF("+++ C+ mode: C+ transmitter disabled\n"); 1893 return 0 ; 1894 } 1895 1896 PCIDevice *d = PCI_DEVICE(s); 1897 int descriptor = s->currCPlusTxDesc; 1898 1899 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); 1900 1901 /* Normal priority ring */ 1902 cplus_tx_ring_desc += 16 * descriptor; 1903 1904 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at " 1905 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], 1906 s->TxAddr[0], cplus_tx_ring_desc); 1907 1908 uint32_t val, txdw0,txdw1,txbufLO,txbufHI; 1909 1910 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 1911 txdw0 = le32_to_cpu(val); 1912 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4); 1913 txdw1 = le32_to_cpu(val); 1914 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4); 1915 txbufLO = le32_to_cpu(val); 1916 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4); 1917 txbufHI = le32_to_cpu(val); 1918 1919 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor, 1920 txdw0, txdw1, txbufLO, txbufHI); 1921 1922 /* w0 ownership flag */ 1923 #define CP_TX_OWN (1<<31) 1924 /* w0 end of ring flag */ 1925 #define CP_TX_EOR (1<<30) 1926 /* first segment of received packet flag */ 1927 #define CP_TX_FS (1<<29) 1928 /* last segment of received packet flag */ 1929 #define CP_TX_LS (1<<28) 1930 /* large send packet flag */ 1931 #define CP_TX_LGSEN (1<<27) 1932 /* large send MSS mask, bits 16...25 */ 1933 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) 1934 1935 /* IP checksum offload flag */ 1936 #define CP_TX_IPCS (1<<18) 1937 /* UDP checksum offload flag */ 1938 #define CP_TX_UDPCS (1<<17) 1939 /* TCP checksum offload flag */ 1940 #define CP_TX_TCPCS (1<<16) 1941 1942 /* w0 bits 0...15 : buffer size */ 1943 #define CP_TX_BUFFER_SIZE (1<<16) 1944 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) 1945 /* w1 add tag flag */ 1946 #define CP_TX_TAGC (1<<17) 1947 /* w1 bits 0...15 : VLAN tag (big endian) */ 1948 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) 1949 /* w2 low 32bit of Rx buffer ptr */ 1950 /* w3 high 32bit of Rx buffer ptr */ 1951 1952 /* set after transmission */ 1953 /* FIFO underrun flag */ 1954 #define CP_TX_STATUS_UNF (1<<25) 1955 /* transmit error summary flag, valid if set any of three below */ 1956 #define CP_TX_STATUS_TES (1<<23) 1957 /* out-of-window collision flag */ 1958 #define CP_TX_STATUS_OWC (1<<22) 1959 /* link failure flag */ 1960 #define CP_TX_STATUS_LNKF (1<<21) 1961 /* excessive collisions flag */ 1962 #define CP_TX_STATUS_EXC (1<<20) 1963 1964 if (!(txdw0 & CP_TX_OWN)) 1965 { 1966 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor); 1967 return 0 ; 1968 } 1969 1970 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor); 1971 1972 if (txdw0 & CP_TX_FS) 1973 { 1974 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment " 1975 "descriptor\n", descriptor); 1976 1977 /* reset internal buffer offset */ 1978 s->cplus_txbuffer_offset = 0; 1979 } 1980 1981 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; 1982 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); 1983 1984 /* make sure we have enough space to assemble the packet */ 1985 if (!s->cplus_txbuffer) 1986 { 1987 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; 1988 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len); 1989 s->cplus_txbuffer_offset = 0; 1990 1991 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n", 1992 s->cplus_txbuffer_len); 1993 } 1994 1995 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) 1996 { 1997 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */ 1998 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; 1999 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor" 2000 "length to %d\n", txsize); 2001 } 2002 2003 /* append more data to the packet */ 2004 2005 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at " 2006 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr, 2007 s->cplus_txbuffer_offset); 2008 2009 pci_dma_read(d, tx_addr, 2010 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); 2011 s->cplus_txbuffer_offset += txsize; 2012 2013 /* seek to next Rx descriptor */ 2014 if (txdw0 & CP_TX_EOR) 2015 { 2016 s->currCPlusTxDesc = 0; 2017 } 2018 else 2019 { 2020 ++s->currCPlusTxDesc; 2021 if (s->currCPlusTxDesc >= 64) 2022 s->currCPlusTxDesc = 0; 2023 } 2024 2025 /* transfer ownership to target */ 2026 txdw0 &= ~CP_TX_OWN; 2027 2028 /* reset error indicator bits */ 2029 txdw0 &= ~CP_TX_STATUS_UNF; 2030 txdw0 &= ~CP_TX_STATUS_TES; 2031 txdw0 &= ~CP_TX_STATUS_OWC; 2032 txdw0 &= ~CP_TX_STATUS_LNKF; 2033 txdw0 &= ~CP_TX_STATUS_EXC; 2034 2035 /* update ring data */ 2036 val = cpu_to_le32(txdw0); 2037 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 2038 2039 /* Now decide if descriptor being processed is holding the last segment of packet */ 2040 if (txdw0 & CP_TX_LS) 2041 { 2042 uint8_t dot1q_buffer_space[VLAN_HLEN]; 2043 uint16_t *dot1q_buffer; 2044 2045 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n", 2046 descriptor); 2047 2048 /* can transfer fully assembled packet */ 2049 2050 uint8_t *saved_buffer = s->cplus_txbuffer; 2051 int saved_size = s->cplus_txbuffer_offset; 2052 int saved_buffer_len = s->cplus_txbuffer_len; 2053 2054 /* create vlan tag */ 2055 if (txdw1 & CP_TX_TAGC) { 2056 /* the vlan tag is in BE byte order in the descriptor 2057 * BE + le_to_cpu() + ~swap()~ = cpu */ 2058 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", 2059 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); 2060 2061 dot1q_buffer = (uint16_t *) dot1q_buffer_space; 2062 dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN); 2063 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */ 2064 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK); 2065 } else { 2066 dot1q_buffer = NULL; 2067 } 2068 2069 /* reset the card space to protect from recursive call */ 2070 s->cplus_txbuffer = NULL; 2071 s->cplus_txbuffer_offset = 0; 2072 s->cplus_txbuffer_len = 0; 2073 2074 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) 2075 { 2076 DPRINTF("+++ C+ mode offloaded task checksum\n"); 2077 2078 /* Large enough for Ethernet and IP headers? */ 2079 if (saved_size < ETH_HLEN + sizeof(struct ip_header)) { 2080 goto skip_offload; 2081 } 2082 2083 /* ip packet header */ 2084 struct ip_header *ip = NULL; 2085 int hlen = 0; 2086 uint8_t ip_protocol = 0; 2087 uint16_t ip_data_len = 0; 2088 2089 uint8_t *eth_payload_data = NULL; 2090 size_t eth_payload_len = 0; 2091 2092 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); 2093 if (proto != ETH_P_IP) 2094 { 2095 goto skip_offload; 2096 } 2097 2098 DPRINTF("+++ C+ mode has IP packet\n"); 2099 2100 /* Note on memory alignment: eth_payload_data is 16-bit aligned 2101 * since saved_buffer is allocated with g_malloc() and ETH_HLEN is 2102 * even. 32-bit accesses must use ldl/stl wrappers to avoid 2103 * unaligned accesses. 2104 */ 2105 eth_payload_data = saved_buffer + ETH_HLEN; 2106 eth_payload_len = saved_size - ETH_HLEN; 2107 2108 ip = (struct ip_header*)eth_payload_data; 2109 2110 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) { 2111 DPRINTF("+++ C+ mode packet has bad IP version %d " 2112 "expected %d\n", IP_HEADER_VERSION(ip), 2113 IP_HEADER_VERSION_4); 2114 goto skip_offload; 2115 } 2116 2117 hlen = IP_HDR_GET_LEN(ip); 2118 if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) { 2119 goto skip_offload; 2120 } 2121 2122 ip_protocol = ip->ip_p; 2123 2124 ip_data_len = be16_to_cpu(ip->ip_len); 2125 if (ip_data_len < hlen || ip_data_len > eth_payload_len) { 2126 goto skip_offload; 2127 } 2128 ip_data_len -= hlen; 2129 2130 if (txdw0 & CP_TX_IPCS) 2131 { 2132 DPRINTF("+++ C+ mode need IP checksum\n"); 2133 2134 ip->ip_sum = 0; 2135 ip->ip_sum = ip_checksum(ip, hlen); 2136 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n", 2137 hlen, ip->ip_sum); 2138 } 2139 2140 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) 2141 { 2142 /* Large enough for the TCP header? */ 2143 if (ip_data_len < sizeof(tcp_header)) { 2144 goto skip_offload; 2145 } 2146 2147 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; 2148 2149 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d " 2150 "frame data %d specified MSS=%d\n", ETH_MTU, 2151 ip_data_len, saved_size - ETH_HLEN, large_send_mss); 2152 2153 int tcp_send_offset = 0; 2154 int send_count = 0; 2155 2156 /* maximum IP header length is 60 bytes */ 2157 uint8_t saved_ip_header[60]; 2158 2159 /* save IP header template; data area is used in tcp checksum calculation */ 2160 memcpy(saved_ip_header, eth_payload_data, hlen); 2161 2162 /* a placeholder for checksum calculation routine in tcp case */ 2163 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2164 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2165 2166 /* pointer to TCP header */ 2167 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); 2168 2169 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr); 2170 2171 /* Invalid TCP data offset? */ 2172 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) { 2173 goto skip_offload; 2174 } 2175 2176 /* ETH_MTU = ip header len + tcp header len + payload */ 2177 int tcp_data_len = ip_data_len - tcp_hlen; 2178 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen; 2179 2180 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP " 2181 "data len %d TCP chunk size %d\n", ip_data_len, 2182 tcp_hlen, tcp_data_len, tcp_chunk_size); 2183 2184 /* note the cycle below overwrites IP header data, 2185 but restores it from saved_ip_header before sending packet */ 2186 2187 int is_last_frame = 0; 2188 2189 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) 2190 { 2191 uint16_t chunk_size = tcp_chunk_size; 2192 2193 /* check if this is the last frame */ 2194 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len) 2195 { 2196 is_last_frame = 1; 2197 chunk_size = tcp_data_len - tcp_send_offset; 2198 } 2199 2200 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n", 2201 ldl_be_p(&p_tcp_hdr->th_seq)); 2202 2203 /* add 4 TCP pseudoheader fields */ 2204 /* copy IP source and destination fields */ 2205 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2206 2207 DPRINTF("+++ C+ mode TSO calculating TCP checksum for " 2208 "packet with %d bytes data\n", tcp_hlen + 2209 chunk_size); 2210 2211 if (tcp_send_offset) 2212 { 2213 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); 2214 } 2215 2216 /* keep PUSH and FIN flags only for the last frame */ 2217 if (!is_last_frame) 2218 { 2219 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN); 2220 } 2221 2222 /* recalculate TCP checksum */ 2223 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2224 p_tcpip_hdr->zeros = 0; 2225 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2226 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); 2227 2228 p_tcp_hdr->th_sum = 0; 2229 2230 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); 2231 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n", 2232 tcp_checksum); 2233 2234 p_tcp_hdr->th_sum = tcp_checksum; 2235 2236 /* restore IP header */ 2237 memcpy(eth_payload_data, saved_ip_header, hlen); 2238 2239 /* set IP data length and recalculate IP checksum */ 2240 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); 2241 2242 /* increment IP id for subsequent frames */ 2243 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); 2244 2245 ip->ip_sum = 0; 2246 ip->ip_sum = ip_checksum(eth_payload_data, hlen); 2247 DPRINTF("+++ C+ mode TSO IP header len=%d " 2248 "checksum=%04x\n", hlen, ip->ip_sum); 2249 2250 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size; 2251 DPRINTF("+++ C+ mode TSO transferring packet size " 2252 "%d\n", tso_send_size); 2253 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 2254 0, (uint8_t *) dot1q_buffer); 2255 2256 /* add transferred count to TCP sequence number */ 2257 stl_be_p(&p_tcp_hdr->th_seq, 2258 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq)); 2259 ++send_count; 2260 } 2261 2262 /* Stop sending this frame */ 2263 saved_size = 0; 2264 } 2265 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) 2266 { 2267 DPRINTF("+++ C+ mode need TCP or UDP checksum\n"); 2268 2269 /* maximum IP header length is 60 bytes */ 2270 uint8_t saved_ip_header[60]; 2271 memcpy(saved_ip_header, eth_payload_data, hlen); 2272 2273 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2274 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2275 2276 /* add 4 TCP pseudoheader fields */ 2277 /* copy IP source and destination fields */ 2278 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2279 2280 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) 2281 { 2282 DPRINTF("+++ C+ mode calculating TCP checksum for " 2283 "packet with %d bytes data\n", ip_data_len); 2284 2285 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2286 p_tcpip_hdr->zeros = 0; 2287 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2288 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2289 2290 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12); 2291 2292 p_tcp_hdr->th_sum = 0; 2293 2294 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2295 DPRINTF("+++ C+ mode TCP checksum %04x\n", 2296 tcp_checksum); 2297 2298 p_tcp_hdr->th_sum = tcp_checksum; 2299 } 2300 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) 2301 { 2302 DPRINTF("+++ C+ mode calculating UDP checksum for " 2303 "packet with %d bytes data\n", ip_data_len); 2304 2305 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; 2306 p_udpip_hdr->zeros = 0; 2307 p_udpip_hdr->ip_proto = IP_PROTO_UDP; 2308 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2309 2310 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12); 2311 2312 p_udp_hdr->uh_sum = 0; 2313 2314 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2315 DPRINTF("+++ C+ mode UDP checksum %04x\n", 2316 udp_checksum); 2317 2318 p_udp_hdr->uh_sum = udp_checksum; 2319 } 2320 2321 /* restore IP header */ 2322 memcpy(eth_payload_data, saved_ip_header, hlen); 2323 } 2324 } 2325 2326 skip_offload: 2327 /* update tally counter */ 2328 ++s->tally_counters.TxOk; 2329 2330 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size); 2331 2332 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1, 2333 (uint8_t *) dot1q_buffer); 2334 2335 /* restore card space if there was no recursion and reset offset */ 2336 if (!s->cplus_txbuffer) 2337 { 2338 s->cplus_txbuffer = saved_buffer; 2339 s->cplus_txbuffer_len = saved_buffer_len; 2340 s->cplus_txbuffer_offset = 0; 2341 } 2342 else 2343 { 2344 g_free(saved_buffer); 2345 } 2346 } 2347 else 2348 { 2349 DPRINTF("+++ C+ mode transmission continue to next descriptor\n"); 2350 } 2351 2352 return 1; 2353 } 2354 2355 static void rtl8139_cplus_transmit(RTL8139State *s) 2356 { 2357 int txcount = 0; 2358 2359 while (txcount < 64 && rtl8139_cplus_transmit_one(s)) 2360 { 2361 ++txcount; 2362 } 2363 2364 /* Mark transfer completed */ 2365 if (!txcount) 2366 { 2367 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n", 2368 s->currCPlusTxDesc); 2369 } 2370 else 2371 { 2372 /* update interrupt status */ 2373 s->IntrStatus |= TxOK; 2374 rtl8139_update_irq(s); 2375 } 2376 } 2377 2378 static void rtl8139_transmit(RTL8139State *s) 2379 { 2380 int descriptor = s->currTxDesc, txcount = 0; 2381 2382 /*while*/ 2383 if (rtl8139_transmit_one(s, descriptor)) 2384 { 2385 ++s->currTxDesc; 2386 s->currTxDesc %= 4; 2387 ++txcount; 2388 } 2389 2390 /* Mark transfer completed */ 2391 if (!txcount) 2392 { 2393 DPRINTF("transmitter queue stalled, current TxDesc = %d\n", 2394 s->currTxDesc); 2395 } 2396 } 2397 2398 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) 2399 { 2400 2401 int descriptor = txRegOffset/4; 2402 2403 /* handle C+ transmit mode register configuration */ 2404 2405 if (s->cplus_enabled) 2406 { 2407 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x " 2408 "descriptor=%d\n", txRegOffset, val, descriptor); 2409 2410 /* handle Dump Tally Counters command */ 2411 s->TxStatus[descriptor] = val; 2412 2413 if (descriptor == 0 && (val & 0x8)) 2414 { 2415 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); 2416 2417 /* dump tally counters to specified memory location */ 2418 RTL8139TallyCounters_dma_write(s, tc_addr); 2419 2420 /* mark dump completed */ 2421 s->TxStatus[0] &= ~0x8; 2422 } 2423 2424 return; 2425 } 2426 2427 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", 2428 txRegOffset, val, descriptor); 2429 2430 /* mask only reserved bits */ 2431 val &= ~0xff00c000; /* these bits are reset on write */ 2432 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); 2433 2434 s->TxStatus[descriptor] = val; 2435 2436 /* attempt to start transmission */ 2437 rtl8139_transmit(s); 2438 } 2439 2440 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[], 2441 uint32_t base, uint8_t addr, 2442 int size) 2443 { 2444 uint32_t reg = (addr - base) / 4; 2445 uint32_t offset = addr & 0x3; 2446 uint32_t ret = 0; 2447 2448 if (addr & (size - 1)) { 2449 DPRINTF("not implemented read for TxStatus/TxAddr " 2450 "addr=0x%x size=0x%x\n", addr, size); 2451 return ret; 2452 } 2453 2454 switch (size) { 2455 case 1: /* fall through */ 2456 case 2: /* fall through */ 2457 case 4: 2458 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1); 2459 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n", 2460 reg, addr, size, ret); 2461 break; 2462 default: 2463 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size); 2464 break; 2465 } 2466 2467 return ret; 2468 } 2469 2470 static uint16_t rtl8139_TSAD_read(RTL8139State *s) 2471 { 2472 uint16_t ret = 0; 2473 2474 /* Simulate TSAD, it is read only anyway */ 2475 2476 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) 2477 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) 2478 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) 2479 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) 2480 2481 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) 2482 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) 2483 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) 2484 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) 2485 2486 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) 2487 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) 2488 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) 2489 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) 2490 2491 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) 2492 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) 2493 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) 2494 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; 2495 2496 2497 DPRINTF("TSAD read val=0x%04x\n", ret); 2498 2499 return ret; 2500 } 2501 2502 static uint16_t rtl8139_CSCR_read(RTL8139State *s) 2503 { 2504 uint16_t ret = s->CSCR; 2505 2506 DPRINTF("CSCR read val=0x%04x\n", ret); 2507 2508 return ret; 2509 } 2510 2511 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) 2512 { 2513 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val); 2514 2515 s->TxAddr[txAddrOffset/4] = val; 2516 } 2517 2518 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) 2519 { 2520 uint32_t ret = s->TxAddr[txAddrOffset/4]; 2521 2522 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret); 2523 2524 return ret; 2525 } 2526 2527 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) 2528 { 2529 DPRINTF("RxBufPtr write val=0x%04x\n", val); 2530 2531 /* this value is off by 16 */ 2532 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); 2533 2534 /* more buffer space may be available so try to receive */ 2535 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 2536 2537 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", 2538 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 2539 } 2540 2541 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s) 2542 { 2543 /* this value is off by 16 */ 2544 uint32_t ret = s->RxBufPtr - 0x10; 2545 2546 DPRINTF("RxBufPtr read val=0x%04x\n", ret); 2547 2548 return ret; 2549 } 2550 2551 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s) 2552 { 2553 /* this value is NOT off by 16 */ 2554 uint32_t ret = s->RxBufAddr; 2555 2556 DPRINTF("RxBufAddr read val=0x%04x\n", ret); 2557 2558 return ret; 2559 } 2560 2561 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) 2562 { 2563 DPRINTF("RxBuf write val=0x%08x\n", val); 2564 2565 s->RxBuf = val; 2566 2567 /* may need to reset rxring here */ 2568 } 2569 2570 static uint32_t rtl8139_RxBuf_read(RTL8139State *s) 2571 { 2572 uint32_t ret = s->RxBuf; 2573 2574 DPRINTF("RxBuf read val=0x%08x\n", ret); 2575 2576 return ret; 2577 } 2578 2579 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) 2580 { 2581 DPRINTF("IntrMask write(w) val=0x%04x\n", val); 2582 2583 /* mask unwritable bits */ 2584 val = SET_MASKED(val, 0x1e00, s->IntrMask); 2585 2586 s->IntrMask = val; 2587 2588 rtl8139_update_irq(s); 2589 2590 } 2591 2592 static uint32_t rtl8139_IntrMask_read(RTL8139State *s) 2593 { 2594 uint32_t ret = s->IntrMask; 2595 2596 DPRINTF("IntrMask read(w) val=0x%04x\n", ret); 2597 2598 return ret; 2599 } 2600 2601 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) 2602 { 2603 DPRINTF("IntrStatus write(w) val=0x%04x\n", val); 2604 2605 #if 0 2606 2607 /* writing to ISR has no effect */ 2608 2609 return; 2610 2611 #else 2612 uint16_t newStatus = s->IntrStatus & ~val; 2613 2614 /* mask unwritable bits */ 2615 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); 2616 2617 /* writing 1 to interrupt status register bit clears it */ 2618 s->IntrStatus = 0; 2619 rtl8139_update_irq(s); 2620 2621 s->IntrStatus = newStatus; 2622 rtl8139_set_next_tctr_time(s); 2623 rtl8139_update_irq(s); 2624 2625 #endif 2626 } 2627 2628 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) 2629 { 2630 uint32_t ret = s->IntrStatus; 2631 2632 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret); 2633 2634 #if 0 2635 2636 /* reading ISR clears all interrupts */ 2637 s->IntrStatus = 0; 2638 2639 rtl8139_update_irq(s); 2640 2641 #endif 2642 2643 return ret; 2644 } 2645 2646 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) 2647 { 2648 DPRINTF("MultiIntr write(w) val=0x%04x\n", val); 2649 2650 /* mask unwritable bits */ 2651 val = SET_MASKED(val, 0xf000, s->MultiIntr); 2652 2653 s->MultiIntr = val; 2654 } 2655 2656 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s) 2657 { 2658 uint32_t ret = s->MultiIntr; 2659 2660 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret); 2661 2662 return ret; 2663 } 2664 2665 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) 2666 { 2667 RTL8139State *s = opaque; 2668 2669 switch (addr) 2670 { 2671 case MAC0 ... MAC0+4: 2672 s->phys[addr - MAC0] = val; 2673 break; 2674 case MAC0+5: 2675 s->phys[addr - MAC0] = val; 2676 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 2677 break; 2678 case MAC0+6 ... MAC0+7: 2679 /* reserved */ 2680 break; 2681 case MAR0 ... MAR0+7: 2682 s->mult[addr - MAR0] = val; 2683 break; 2684 case ChipCmd: 2685 rtl8139_ChipCmd_write(s, val); 2686 break; 2687 case Cfg9346: 2688 rtl8139_Cfg9346_write(s, val); 2689 break; 2690 case TxConfig: /* windows driver sometimes writes using byte-lenth call */ 2691 rtl8139_TxConfig_writeb(s, val); 2692 break; 2693 case Config0: 2694 rtl8139_Config0_write(s, val); 2695 break; 2696 case Config1: 2697 rtl8139_Config1_write(s, val); 2698 break; 2699 case Config3: 2700 rtl8139_Config3_write(s, val); 2701 break; 2702 case Config4: 2703 rtl8139_Config4_write(s, val); 2704 break; 2705 case Config5: 2706 rtl8139_Config5_write(s, val); 2707 break; 2708 case MediaStatus: 2709 /* ignore */ 2710 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n", 2711 val); 2712 break; 2713 2714 case HltClk: 2715 DPRINTF("HltClk write val=0x%08x\n", val); 2716 if (val == 'R') 2717 { 2718 s->clock_enabled = 1; 2719 } 2720 else if (val == 'H') 2721 { 2722 s->clock_enabled = 0; 2723 } 2724 break; 2725 2726 case TxThresh: 2727 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val); 2728 s->TxThresh = val; 2729 break; 2730 2731 case TxPoll: 2732 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val); 2733 if (val & (1 << 7)) 2734 { 2735 DPRINTF("C+ TxPoll high priority transmission (not " 2736 "implemented)\n"); 2737 //rtl8139_cplus_transmit(s); 2738 } 2739 if (val & (1 << 6)) 2740 { 2741 DPRINTF("C+ TxPoll normal priority transmission\n"); 2742 rtl8139_cplus_transmit(s); 2743 } 2744 2745 break; 2746 2747 default: 2748 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr, 2749 val); 2750 break; 2751 } 2752 } 2753 2754 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) 2755 { 2756 RTL8139State *s = opaque; 2757 2758 switch (addr) 2759 { 2760 case IntrMask: 2761 rtl8139_IntrMask_write(s, val); 2762 break; 2763 2764 case IntrStatus: 2765 rtl8139_IntrStatus_write(s, val); 2766 break; 2767 2768 case MultiIntr: 2769 rtl8139_MultiIntr_write(s, val); 2770 break; 2771 2772 case RxBufPtr: 2773 rtl8139_RxBufPtr_write(s, val); 2774 break; 2775 2776 case BasicModeCtrl: 2777 rtl8139_BasicModeCtrl_write(s, val); 2778 break; 2779 case BasicModeStatus: 2780 rtl8139_BasicModeStatus_write(s, val); 2781 break; 2782 case NWayAdvert: 2783 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val); 2784 s->NWayAdvert = val; 2785 break; 2786 case NWayLPAR: 2787 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val); 2788 break; 2789 case NWayExpansion: 2790 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val); 2791 s->NWayExpansion = val; 2792 break; 2793 2794 case CpCmd: 2795 rtl8139_CpCmd_write(s, val); 2796 break; 2797 2798 case IntrMitigate: 2799 rtl8139_IntrMitigate_write(s, val); 2800 break; 2801 2802 default: 2803 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n", 2804 addr, val); 2805 2806 rtl8139_io_writeb(opaque, addr, val & 0xff); 2807 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2808 break; 2809 } 2810 } 2811 2812 static void rtl8139_set_next_tctr_time(RTL8139State *s) 2813 { 2814 const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32; 2815 2816 DPRINTF("entered rtl8139_set_next_tctr_time\n"); 2817 2818 /* This function is called at least once per period, so it is a good 2819 * place to update the timer base. 2820 * 2821 * After one iteration of this loop the value in the Timer register does 2822 * not change, but the device model is counting up by 2^32 ticks (approx. 2823 * 130 seconds). 2824 */ 2825 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2826 s->TCTR_base += ns_per_period; 2827 } 2828 2829 if (!s->TimerInt) { 2830 timer_del(s->timer); 2831 } else { 2832 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD; 2833 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2834 delta += ns_per_period; 2835 } 2836 timer_mod(s->timer, s->TCTR_base + delta); 2837 } 2838 } 2839 2840 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) 2841 { 2842 RTL8139State *s = opaque; 2843 2844 switch (addr) 2845 { 2846 case RxMissed: 2847 DPRINTF("RxMissed clearing on write\n"); 2848 s->RxMissed = 0; 2849 break; 2850 2851 case TxConfig: 2852 rtl8139_TxConfig_write(s, val); 2853 break; 2854 2855 case RxConfig: 2856 rtl8139_RxConfig_write(s, val); 2857 break; 2858 2859 case TxStatus0 ... TxStatus0+4*4-1: 2860 rtl8139_TxStatus_write(s, addr-TxStatus0, val); 2861 break; 2862 2863 case TxAddr0 ... TxAddr0+4*4-1: 2864 rtl8139_TxAddr_write(s, addr-TxAddr0, val); 2865 break; 2866 2867 case RxBuf: 2868 rtl8139_RxBuf_write(s, val); 2869 break; 2870 2871 case RxRingAddrLO: 2872 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val); 2873 s->RxRingAddrLO = val; 2874 break; 2875 2876 case RxRingAddrHI: 2877 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val); 2878 s->RxRingAddrHI = val; 2879 break; 2880 2881 case Timer: 2882 DPRINTF("TCTR Timer reset on write\n"); 2883 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2884 rtl8139_set_next_tctr_time(s); 2885 break; 2886 2887 case FlashReg: 2888 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val); 2889 if (s->TimerInt != val) { 2890 s->TimerInt = val; 2891 rtl8139_set_next_tctr_time(s); 2892 } 2893 break; 2894 2895 default: 2896 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n", 2897 addr, val); 2898 rtl8139_io_writeb(opaque, addr, val & 0xff); 2899 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2900 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); 2901 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); 2902 break; 2903 } 2904 } 2905 2906 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) 2907 { 2908 RTL8139State *s = opaque; 2909 int ret; 2910 2911 switch (addr) 2912 { 2913 case MAC0 ... MAC0+5: 2914 ret = s->phys[addr - MAC0]; 2915 break; 2916 case MAC0+6 ... MAC0+7: 2917 ret = 0; 2918 break; 2919 case MAR0 ... MAR0+7: 2920 ret = s->mult[addr - MAR0]; 2921 break; 2922 case TxStatus0 ... TxStatus0+4*4-1: 2923 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 2924 addr, 1); 2925 break; 2926 case ChipCmd: 2927 ret = rtl8139_ChipCmd_read(s); 2928 break; 2929 case Cfg9346: 2930 ret = rtl8139_Cfg9346_read(s); 2931 break; 2932 case Config0: 2933 ret = rtl8139_Config0_read(s); 2934 break; 2935 case Config1: 2936 ret = rtl8139_Config1_read(s); 2937 break; 2938 case Config3: 2939 ret = rtl8139_Config3_read(s); 2940 break; 2941 case Config4: 2942 ret = rtl8139_Config4_read(s); 2943 break; 2944 case Config5: 2945 ret = rtl8139_Config5_read(s); 2946 break; 2947 2948 case MediaStatus: 2949 /* The LinkDown bit of MediaStatus is inverse with link status */ 2950 ret = 0xd0 | (~s->BasicModeStatus & 0x04); 2951 DPRINTF("MediaStatus read 0x%x\n", ret); 2952 break; 2953 2954 case HltClk: 2955 ret = s->clock_enabled; 2956 DPRINTF("HltClk read 0x%x\n", ret); 2957 break; 2958 2959 case PCIRevisionID: 2960 ret = RTL8139_PCI_REVID; 2961 DPRINTF("PCI Revision ID read 0x%x\n", ret); 2962 break; 2963 2964 case TxThresh: 2965 ret = s->TxThresh; 2966 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret); 2967 break; 2968 2969 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ 2970 ret = s->TxConfig >> 24; 2971 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret); 2972 break; 2973 2974 default: 2975 DPRINTF("not implemented read(b) addr=0x%x\n", addr); 2976 ret = 0; 2977 break; 2978 } 2979 2980 return ret; 2981 } 2982 2983 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) 2984 { 2985 RTL8139State *s = opaque; 2986 uint32_t ret; 2987 2988 switch (addr) 2989 { 2990 case TxAddr0 ... TxAddr0+4*4-1: 2991 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2); 2992 break; 2993 case IntrMask: 2994 ret = rtl8139_IntrMask_read(s); 2995 break; 2996 2997 case IntrStatus: 2998 ret = rtl8139_IntrStatus_read(s); 2999 break; 3000 3001 case MultiIntr: 3002 ret = rtl8139_MultiIntr_read(s); 3003 break; 3004 3005 case RxBufPtr: 3006 ret = rtl8139_RxBufPtr_read(s); 3007 break; 3008 3009 case RxBufAddr: 3010 ret = rtl8139_RxBufAddr_read(s); 3011 break; 3012 3013 case BasicModeCtrl: 3014 ret = rtl8139_BasicModeCtrl_read(s); 3015 break; 3016 case BasicModeStatus: 3017 ret = rtl8139_BasicModeStatus_read(s); 3018 break; 3019 case NWayAdvert: 3020 ret = s->NWayAdvert; 3021 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret); 3022 break; 3023 case NWayLPAR: 3024 ret = s->NWayLPAR; 3025 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret); 3026 break; 3027 case NWayExpansion: 3028 ret = s->NWayExpansion; 3029 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret); 3030 break; 3031 3032 case CpCmd: 3033 ret = rtl8139_CpCmd_read(s); 3034 break; 3035 3036 case IntrMitigate: 3037 ret = rtl8139_IntrMitigate_read(s); 3038 break; 3039 3040 case TxSummary: 3041 ret = rtl8139_TSAD_read(s); 3042 break; 3043 3044 case CSCR: 3045 ret = rtl8139_CSCR_read(s); 3046 break; 3047 3048 default: 3049 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr); 3050 3051 ret = rtl8139_io_readb(opaque, addr); 3052 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3053 3054 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret); 3055 break; 3056 } 3057 3058 return ret; 3059 } 3060 3061 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) 3062 { 3063 RTL8139State *s = opaque; 3064 uint32_t ret; 3065 3066 switch (addr) 3067 { 3068 case RxMissed: 3069 ret = s->RxMissed; 3070 3071 DPRINTF("RxMissed read val=0x%08x\n", ret); 3072 break; 3073 3074 case TxConfig: 3075 ret = rtl8139_TxConfig_read(s); 3076 break; 3077 3078 case RxConfig: 3079 ret = rtl8139_RxConfig_read(s); 3080 break; 3081 3082 case TxStatus0 ... TxStatus0+4*4-1: 3083 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 3084 addr, 4); 3085 break; 3086 3087 case TxAddr0 ... TxAddr0+4*4-1: 3088 ret = rtl8139_TxAddr_read(s, addr-TxAddr0); 3089 break; 3090 3091 case RxBuf: 3092 ret = rtl8139_RxBuf_read(s); 3093 break; 3094 3095 case RxRingAddrLO: 3096 ret = s->RxRingAddrLO; 3097 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret); 3098 break; 3099 3100 case RxRingAddrHI: 3101 ret = s->RxRingAddrHI; 3102 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret); 3103 break; 3104 3105 case Timer: 3106 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) / 3107 PCI_PERIOD; 3108 DPRINTF("TCTR Timer read val=0x%08x\n", ret); 3109 break; 3110 3111 case FlashReg: 3112 ret = s->TimerInt; 3113 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret); 3114 break; 3115 3116 default: 3117 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr); 3118 3119 ret = rtl8139_io_readb(opaque, addr); 3120 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3121 ret |= rtl8139_io_readb(opaque, addr + 2) << 16; 3122 ret |= rtl8139_io_readb(opaque, addr + 3) << 24; 3123 3124 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret); 3125 break; 3126 } 3127 3128 return ret; 3129 } 3130 3131 /* */ 3132 3133 static int rtl8139_post_load(void *opaque, int version_id) 3134 { 3135 RTL8139State* s = opaque; 3136 rtl8139_set_next_tctr_time(s); 3137 if (version_id < 4) { 3138 s->cplus_enabled = s->CpCmd != 0; 3139 } 3140 3141 /* nc.link_down can't be migrated, so infer link_down according 3142 * to link status bit in BasicModeStatus */ 3143 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0; 3144 3145 return 0; 3146 } 3147 3148 static bool rtl8139_hotplug_ready_needed(void *opaque) 3149 { 3150 return qdev_machine_modified(); 3151 } 3152 3153 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ 3154 .name = "rtl8139/hotplug_ready", 3155 .version_id = 1, 3156 .minimum_version_id = 1, 3157 .needed = rtl8139_hotplug_ready_needed, 3158 .fields = (VMStateField[]) { 3159 VMSTATE_END_OF_LIST() 3160 } 3161 }; 3162 3163 static int rtl8139_pre_save(void *opaque) 3164 { 3165 RTL8139State* s = opaque; 3166 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 3167 3168 /* for migration to older versions */ 3169 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD; 3170 s->rtl8139_mmio_io_addr_dummy = 0; 3171 3172 return 0; 3173 } 3174 3175 static const VMStateDescription vmstate_rtl8139 = { 3176 .name = "rtl8139", 3177 .version_id = 5, 3178 .minimum_version_id = 3, 3179 .post_load = rtl8139_post_load, 3180 .pre_save = rtl8139_pre_save, 3181 .fields = (VMStateField[]) { 3182 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State), 3183 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6), 3184 VMSTATE_BUFFER(mult, RTL8139State), 3185 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4), 3186 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4), 3187 3188 VMSTATE_UINT32(RxBuf, RTL8139State), 3189 VMSTATE_UINT32(RxBufferSize, RTL8139State), 3190 VMSTATE_UINT32(RxBufPtr, RTL8139State), 3191 VMSTATE_UINT32(RxBufAddr, RTL8139State), 3192 3193 VMSTATE_UINT16(IntrStatus, RTL8139State), 3194 VMSTATE_UINT16(IntrMask, RTL8139State), 3195 3196 VMSTATE_UINT32(TxConfig, RTL8139State), 3197 VMSTATE_UINT32(RxConfig, RTL8139State), 3198 VMSTATE_UINT32(RxMissed, RTL8139State), 3199 VMSTATE_UINT16(CSCR, RTL8139State), 3200 3201 VMSTATE_UINT8(Cfg9346, RTL8139State), 3202 VMSTATE_UINT8(Config0, RTL8139State), 3203 VMSTATE_UINT8(Config1, RTL8139State), 3204 VMSTATE_UINT8(Config3, RTL8139State), 3205 VMSTATE_UINT8(Config4, RTL8139State), 3206 VMSTATE_UINT8(Config5, RTL8139State), 3207 3208 VMSTATE_UINT8(clock_enabled, RTL8139State), 3209 VMSTATE_UINT8(bChipCmdState, RTL8139State), 3210 3211 VMSTATE_UINT16(MultiIntr, RTL8139State), 3212 3213 VMSTATE_UINT16(BasicModeCtrl, RTL8139State), 3214 VMSTATE_UINT16(BasicModeStatus, RTL8139State), 3215 VMSTATE_UINT16(NWayAdvert, RTL8139State), 3216 VMSTATE_UINT16(NWayLPAR, RTL8139State), 3217 VMSTATE_UINT16(NWayExpansion, RTL8139State), 3218 3219 VMSTATE_UINT16(CpCmd, RTL8139State), 3220 VMSTATE_UINT8(TxThresh, RTL8139State), 3221 3222 VMSTATE_UNUSED(4), 3223 VMSTATE_MACADDR(conf.macaddr, RTL8139State), 3224 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), 3225 3226 VMSTATE_UINT32(currTxDesc, RTL8139State), 3227 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), 3228 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), 3229 VMSTATE_UINT32(RxRingAddrLO, RTL8139State), 3230 VMSTATE_UINT32(RxRingAddrHI, RTL8139State), 3231 3232 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), 3233 VMSTATE_INT32(eeprom.mode, RTL8139State), 3234 VMSTATE_UINT32(eeprom.tick, RTL8139State), 3235 VMSTATE_UINT8(eeprom.address, RTL8139State), 3236 VMSTATE_UINT16(eeprom.input, RTL8139State), 3237 VMSTATE_UINT16(eeprom.output, RTL8139State), 3238 3239 VMSTATE_UINT8(eeprom.eecs, RTL8139State), 3240 VMSTATE_UINT8(eeprom.eesk, RTL8139State), 3241 VMSTATE_UINT8(eeprom.eedi, RTL8139State), 3242 VMSTATE_UINT8(eeprom.eedo, RTL8139State), 3243 3244 VMSTATE_UINT32(TCTR, RTL8139State), 3245 VMSTATE_UINT32(TimerInt, RTL8139State), 3246 VMSTATE_INT64(TCTR_base, RTL8139State), 3247 3248 VMSTATE_UINT64(tally_counters.TxOk, RTL8139State), 3249 VMSTATE_UINT64(tally_counters.RxOk, RTL8139State), 3250 VMSTATE_UINT64(tally_counters.TxERR, RTL8139State), 3251 VMSTATE_UINT32(tally_counters.RxERR, RTL8139State), 3252 VMSTATE_UINT16(tally_counters.MissPkt, RTL8139State), 3253 VMSTATE_UINT16(tally_counters.FAE, RTL8139State), 3254 VMSTATE_UINT32(tally_counters.Tx1Col, RTL8139State), 3255 VMSTATE_UINT32(tally_counters.TxMCol, RTL8139State), 3256 VMSTATE_UINT64(tally_counters.RxOkPhy, RTL8139State), 3257 VMSTATE_UINT64(tally_counters.RxOkBrd, RTL8139State), 3258 VMSTATE_UINT32_V(tally_counters.RxOkMul, RTL8139State, 5), 3259 VMSTATE_UINT16(tally_counters.TxAbt, RTL8139State), 3260 VMSTATE_UINT16(tally_counters.TxUndrn, RTL8139State), 3261 3262 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4), 3263 VMSTATE_END_OF_LIST() 3264 }, 3265 .subsections = (const VMStateDescription*[]) { 3266 &vmstate_rtl8139_hotplug_ready, 3267 NULL 3268 } 3269 }; 3270 3271 /***********************************************************/ 3272 /* PCI RTL8139 definitions */ 3273 3274 static void rtl8139_ioport_write(void *opaque, hwaddr addr, 3275 uint64_t val, unsigned size) 3276 { 3277 switch (size) { 3278 case 1: 3279 rtl8139_io_writeb(opaque, addr, val); 3280 break; 3281 case 2: 3282 rtl8139_io_writew(opaque, addr, val); 3283 break; 3284 case 4: 3285 rtl8139_io_writel(opaque, addr, val); 3286 break; 3287 } 3288 } 3289 3290 static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr, 3291 unsigned size) 3292 { 3293 switch (size) { 3294 case 1: 3295 return rtl8139_io_readb(opaque, addr); 3296 case 2: 3297 return rtl8139_io_readw(opaque, addr); 3298 case 4: 3299 return rtl8139_io_readl(opaque, addr); 3300 } 3301 3302 return -1; 3303 } 3304 3305 static const MemoryRegionOps rtl8139_io_ops = { 3306 .read = rtl8139_ioport_read, 3307 .write = rtl8139_ioport_write, 3308 .impl = { 3309 .min_access_size = 1, 3310 .max_access_size = 4, 3311 }, 3312 .endianness = DEVICE_LITTLE_ENDIAN, 3313 }; 3314 3315 static void rtl8139_timer(void *opaque) 3316 { 3317 RTL8139State *s = opaque; 3318 3319 if (!s->clock_enabled) 3320 { 3321 DPRINTF(">>> timer: clock is not running\n"); 3322 return; 3323 } 3324 3325 s->IntrStatus |= PCSTimeout; 3326 rtl8139_update_irq(s); 3327 rtl8139_set_next_tctr_time(s); 3328 } 3329 3330 static void pci_rtl8139_uninit(PCIDevice *dev) 3331 { 3332 RTL8139State *s = RTL8139(dev); 3333 3334 g_free(s->cplus_txbuffer); 3335 s->cplus_txbuffer = NULL; 3336 timer_del(s->timer); 3337 timer_free(s->timer); 3338 qemu_del_nic(s->nic); 3339 } 3340 3341 static void rtl8139_set_link_status(NetClientState *nc) 3342 { 3343 RTL8139State *s = qemu_get_nic_opaque(nc); 3344 3345 if (nc->link_down) { 3346 s->BasicModeStatus &= ~0x04; 3347 } else { 3348 s->BasicModeStatus |= 0x04; 3349 } 3350 3351 s->IntrStatus |= RxUnderrun; 3352 rtl8139_update_irq(s); 3353 } 3354 3355 static NetClientInfo net_rtl8139_info = { 3356 .type = NET_CLIENT_DRIVER_NIC, 3357 .size = sizeof(NICState), 3358 .can_receive = rtl8139_can_receive, 3359 .receive = rtl8139_receive, 3360 .link_status_changed = rtl8139_set_link_status, 3361 }; 3362 3363 static void pci_rtl8139_realize(PCIDevice *dev, Error **errp) 3364 { 3365 RTL8139State *s = RTL8139(dev); 3366 DeviceState *d = DEVICE(dev); 3367 uint8_t *pci_conf; 3368 3369 pci_conf = dev->config; 3370 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 3371 /* TODO: start of capability list, but no capability 3372 * list bit in status register, and offset 0xdc seems unused. */ 3373 pci_conf[PCI_CAPABILITY_LIST] = 0xdc; 3374 3375 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s, 3376 "rtl8139", 0x100); 3377 memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io, 3378 0, 0x100); 3379 3380 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io); 3381 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem); 3382 3383 qemu_macaddr_default_if_unset(&s->conf.macaddr); 3384 3385 /* prepare eeprom */ 3386 s->eeprom.contents[0] = 0x8129; 3387 #if 1 3388 /* PCI vendor and device ID should be mirrored here */ 3389 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK; 3390 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139; 3391 #endif 3392 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; 3393 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; 3394 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; 3395 3396 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, 3397 object_get_typename(OBJECT(dev)), d->id, s); 3398 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 3399 3400 s->cplus_txbuffer = NULL; 3401 s->cplus_txbuffer_len = 0; 3402 s->cplus_txbuffer_offset = 0; 3403 3404 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s); 3405 } 3406 3407 static void rtl8139_instance_init(Object *obj) 3408 { 3409 RTL8139State *s = RTL8139(obj); 3410 3411 device_add_bootindex_property(obj, &s->conf.bootindex, 3412 "bootindex", "/ethernet-phy@0", 3413 DEVICE(obj), NULL); 3414 } 3415 3416 static Property rtl8139_properties[] = { 3417 DEFINE_NIC_PROPERTIES(RTL8139State, conf), 3418 DEFINE_PROP_END_OF_LIST(), 3419 }; 3420 3421 static void rtl8139_class_init(ObjectClass *klass, void *data) 3422 { 3423 DeviceClass *dc = DEVICE_CLASS(klass); 3424 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3425 3426 k->realize = pci_rtl8139_realize; 3427 k->exit = pci_rtl8139_uninit; 3428 k->romfile = "efi-rtl8139.rom"; 3429 k->vendor_id = PCI_VENDOR_ID_REALTEK; 3430 k->device_id = PCI_DEVICE_ID_REALTEK_8139; 3431 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */ 3432 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 3433 dc->reset = rtl8139_reset; 3434 dc->vmsd = &vmstate_rtl8139; 3435 dc->props = rtl8139_properties; 3436 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 3437 } 3438 3439 static const TypeInfo rtl8139_info = { 3440 .name = TYPE_RTL8139, 3441 .parent = TYPE_PCI_DEVICE, 3442 .instance_size = sizeof(RTL8139State), 3443 .class_init = rtl8139_class_init, 3444 .instance_init = rtl8139_instance_init, 3445 .interfaces = (InterfaceInfo[]) { 3446 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 3447 { }, 3448 }, 3449 }; 3450 3451 static void rtl8139_register_types(void) 3452 { 3453 type_register_static(&rtl8139_info); 3454 } 3455 3456 type_init(rtl8139_register_types) 3457