1 /** 2 * QEMU RTL8139 emulation 3 * 4 * Copyright (c) 2006 Igor Kovalenko 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 24 * Modifications: 25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver) 26 * 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver 28 * HW revision ID changes for FreeBSD driver 29 * 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver 31 * Corrected packet transfer reassembly routine for 8139C+ mode 32 * Rearranged debugging print statements 33 * Implemented PCI timer interrupt (disabled by default) 34 * Implemented Tally Counters, increased VM load/save version 35 * Implemented IP/TCP/UDP checksum task offloading 36 * 37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading 38 * Fixed MTU=1500 for produced ethernet frames 39 * 40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing 41 * segmentation offloading 42 * Removed slirp.h dependency 43 * Added rx/tx buffer reset when enabling rx/tx operation 44 * 45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only 46 * when strictly needed (required for 47 * Darwin) 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading 49 */ 50 51 /* For crc32 */ 52 #include "qemu/osdep.h" 53 #include <zlib.h> 54 55 #include "hw/hw.h" 56 #include "hw/pci/pci.h" 57 #include "sysemu/dma.h" 58 #include "qemu/timer.h" 59 #include "net/net.h" 60 #include "net/eth.h" 61 #include "hw/loader.h" 62 #include "sysemu/sysemu.h" 63 #include "qemu/iov.h" 64 65 /* debug RTL8139 card */ 66 //#define DEBUG_RTL8139 1 67 68 #define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */ 69 70 #define SET_MASKED(input, mask, curr) \ 71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) 72 73 /* arg % size for size which is a power of 2 */ 74 #define MOD2(input, size) \ 75 ( ( input ) & ( size - 1 ) ) 76 77 #define ETHER_TYPE_LEN 2 78 #define ETH_MTU 1500 79 80 #define VLAN_TCI_LEN 2 81 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) 82 83 #if defined (DEBUG_RTL8139) 84 # define DPRINTF(fmt, ...) \ 85 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) 86 #else 87 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...) 88 { 89 return 0; 90 } 91 #endif 92 93 #define TYPE_RTL8139 "rtl8139" 94 95 #define RTL8139(obj) \ 96 OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139) 97 98 /* Symbolic offsets to registers. */ 99 enum RTL8139_registers { 100 MAC0 = 0, /* Ethernet hardware address. */ 101 MAR0 = 8, /* Multicast filter. */ 102 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ 103 /* Dump Tally Conter control register(64bit). C+ mode only */ 104 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 105 RxBuf = 0x30, 106 ChipCmd = 0x37, 107 RxBufPtr = 0x38, 108 RxBufAddr = 0x3A, 109 IntrMask = 0x3C, 110 IntrStatus = 0x3E, 111 TxConfig = 0x40, 112 RxConfig = 0x44, 113 Timer = 0x48, /* A general-purpose counter. */ 114 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 115 Cfg9346 = 0x50, 116 Config0 = 0x51, 117 Config1 = 0x52, 118 FlashReg = 0x54, 119 MediaStatus = 0x58, 120 Config3 = 0x59, 121 Config4 = 0x5A, /* absent on RTL-8139A */ 122 HltClk = 0x5B, 123 MultiIntr = 0x5C, 124 PCIRevisionID = 0x5E, 125 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ 126 BasicModeCtrl = 0x62, 127 BasicModeStatus = 0x64, 128 NWayAdvert = 0x66, 129 NWayLPAR = 0x68, 130 NWayExpansion = 0x6A, 131 /* Undocumented registers, but required for proper operation. */ 132 FIFOTMS = 0x70, /* FIFO Control and test. */ 133 CSCR = 0x74, /* Chip Status and Configuration Register. */ 134 PARA78 = 0x78, 135 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 136 Config5 = 0xD8, /* absent on RTL-8139A */ 137 /* C+ mode */ 138 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ 139 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ 140 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ 141 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ 142 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ 143 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ 144 TxThresh = 0xEC, /* Early Tx threshold */ 145 }; 146 147 enum ClearBitMasks { 148 MultiIntrClear = 0xF000, 149 ChipCmdClear = 0xE2, 150 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 151 }; 152 153 enum ChipCmdBits { 154 CmdReset = 0x10, 155 CmdRxEnb = 0x08, 156 CmdTxEnb = 0x04, 157 RxBufEmpty = 0x01, 158 }; 159 160 /* C+ mode */ 161 enum CplusCmdBits { 162 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ 163 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ 164 CPlusRxEnb = 0x0002, 165 CPlusTxEnb = 0x0001, 166 }; 167 168 /* Interrupt register bits, using my own meaningful names. */ 169 enum IntrStatusBits { 170 PCIErr = 0x8000, 171 PCSTimeout = 0x4000, 172 RxFIFOOver = 0x40, 173 RxUnderrun = 0x20, /* Packet Underrun / Link Change */ 174 RxOverflow = 0x10, 175 TxErr = 0x08, 176 TxOK = 0x04, 177 RxErr = 0x02, 178 RxOK = 0x01, 179 180 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 181 }; 182 183 enum TxStatusBits { 184 TxHostOwns = 0x2000, 185 TxUnderrun = 0x4000, 186 TxStatOK = 0x8000, 187 TxOutOfWindow = 0x20000000, 188 TxAborted = 0x40000000, 189 TxCarrierLost = 0x80000000, 190 }; 191 enum RxStatusBits { 192 RxMulticast = 0x8000, 193 RxPhysical = 0x4000, 194 RxBroadcast = 0x2000, 195 RxBadSymbol = 0x0020, 196 RxRunt = 0x0010, 197 RxTooLong = 0x0008, 198 RxCRCErr = 0x0004, 199 RxBadAlign = 0x0002, 200 RxStatusOK = 0x0001, 201 }; 202 203 /* Bits in RxConfig. */ 204 enum rx_mode_bits { 205 AcceptErr = 0x20, 206 AcceptRunt = 0x10, 207 AcceptBroadcast = 0x08, 208 AcceptMulticast = 0x04, 209 AcceptMyPhys = 0x02, 210 AcceptAllPhys = 0x01, 211 }; 212 213 /* Bits in TxConfig. */ 214 enum tx_config_bits { 215 216 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 217 TxIFGShift = 24, 218 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 219 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 220 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 221 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 222 223 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 224 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ 225 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 226 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ 227 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ 228 229 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 230 }; 231 232 233 /* Transmit Status of All Descriptors (TSAD) Register */ 234 enum TSAD_bits { 235 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 236 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 237 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 238 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 239 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 240 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 241 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 242 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 243 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 244 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 245 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 246 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 247 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 248 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 249 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 250 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 251 }; 252 253 254 /* Bits in Config1 */ 255 enum Config1Bits { 256 Cfg1_PM_Enable = 0x01, 257 Cfg1_VPD_Enable = 0x02, 258 Cfg1_PIO = 0x04, 259 Cfg1_MMIO = 0x08, 260 LWAKE = 0x10, /* not on 8139, 8139A */ 261 Cfg1_Driver_Load = 0x20, 262 Cfg1_LED0 = 0x40, 263 Cfg1_LED1 = 0x80, 264 SLEEP = (1 << 1), /* only on 8139, 8139A */ 265 PWRDN = (1 << 0), /* only on 8139, 8139A */ 266 }; 267 268 /* Bits in Config3 */ 269 enum Config3Bits { 270 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 271 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 272 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 273 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 274 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 275 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 276 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 277 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 278 }; 279 280 /* Bits in Config4 */ 281 enum Config4Bits { 282 LWPTN = (1 << 2), /* not on 8139, 8139A */ 283 }; 284 285 /* Bits in Config5 */ 286 enum Config5Bits { 287 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 288 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 289 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 290 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ 291 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 292 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 293 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 294 }; 295 296 enum RxConfigBits { 297 /* rx fifo threshold */ 298 RxCfgFIFOShift = 13, 299 RxCfgFIFONone = (7 << RxCfgFIFOShift), 300 301 /* Max DMA burst */ 302 RxCfgDMAShift = 8, 303 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 304 305 /* rx ring buffer length */ 306 RxCfgRcv8K = 0, 307 RxCfgRcv16K = (1 << 11), 308 RxCfgRcv32K = (1 << 12), 309 RxCfgRcv64K = (1 << 11) | (1 << 12), 310 311 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 312 RxNoWrap = (1 << 7), 313 }; 314 315 /* Twister tuning parameters from RealTek. 316 Completely undocumented, but required to tune bad links on some boards. */ 317 /* 318 enum CSCRBits { 319 CSCR_LinkOKBit = 0x0400, 320 CSCR_LinkChangeBit = 0x0800, 321 CSCR_LinkStatusBits = 0x0f000, 322 CSCR_LinkDownOffCmd = 0x003c0, 323 CSCR_LinkDownCmd = 0x0f3c0, 324 */ 325 enum CSCRBits { 326 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ 327 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ 328 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ 329 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ 330 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ 331 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ 332 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ 333 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ 334 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ 335 }; 336 337 enum Cfg9346Bits { 338 Cfg9346_Normal = 0x00, 339 Cfg9346_Autoload = 0x40, 340 Cfg9346_Programming = 0x80, 341 Cfg9346_ConfigWrite = 0xC0, 342 }; 343 344 typedef enum { 345 CH_8139 = 0, 346 CH_8139_K, 347 CH_8139A, 348 CH_8139A_G, 349 CH_8139B, 350 CH_8130, 351 CH_8139C, 352 CH_8100, 353 CH_8100B_8139D, 354 CH_8101, 355 } chip_t; 356 357 enum chip_flags { 358 HasHltClk = (1 << 0), 359 HasLWake = (1 << 1), 360 }; 361 362 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 363 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 364 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 365 366 #define RTL8139_PCI_REVID_8139 0x10 367 #define RTL8139_PCI_REVID_8139CPLUS 0x20 368 369 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS 370 371 /* Size is 64 * 16bit words */ 372 #define EEPROM_9346_ADDR_BITS 6 373 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) 374 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) 375 376 enum Chip9346Operation 377 { 378 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ 379 Chip9346_op_read = 0x80, /* 10 AAAAAA */ 380 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ 381 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ 382 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ 383 Chip9346_op_write_all = 0x10, /* 00 01zzzz */ 384 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ 385 }; 386 387 enum Chip9346Mode 388 { 389 Chip9346_none = 0, 390 Chip9346_enter_command_mode, 391 Chip9346_read_command, 392 Chip9346_data_read, /* from output register */ 393 Chip9346_data_write, /* to input register, then to contents at specified address */ 394 Chip9346_data_write_all, /* to input register, then filling contents */ 395 }; 396 397 typedef struct EEprom9346 398 { 399 uint16_t contents[EEPROM_9346_SIZE]; 400 int mode; 401 uint32_t tick; 402 uint8_t address; 403 uint16_t input; 404 uint16_t output; 405 406 uint8_t eecs; 407 uint8_t eesk; 408 uint8_t eedi; 409 uint8_t eedo; 410 } EEprom9346; 411 412 typedef struct RTL8139TallyCounters 413 { 414 /* Tally counters */ 415 uint64_t TxOk; 416 uint64_t RxOk; 417 uint64_t TxERR; 418 uint32_t RxERR; 419 uint16_t MissPkt; 420 uint16_t FAE; 421 uint32_t Tx1Col; 422 uint32_t TxMCol; 423 uint64_t RxOkPhy; 424 uint64_t RxOkBrd; 425 uint32_t RxOkMul; 426 uint16_t TxAbt; 427 uint16_t TxUndrn; 428 } RTL8139TallyCounters; 429 430 /* Clears all tally counters */ 431 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); 432 433 typedef struct RTL8139State { 434 /*< private >*/ 435 PCIDevice parent_obj; 436 /*< public >*/ 437 438 uint8_t phys[8]; /* mac address */ 439 uint8_t mult[8]; /* multicast mask array */ 440 441 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ 442 uint32_t TxAddr[4]; /* TxAddr0 */ 443 uint32_t RxBuf; /* Receive buffer */ 444 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */ 445 uint32_t RxBufPtr; 446 uint32_t RxBufAddr; 447 448 uint16_t IntrStatus; 449 uint16_t IntrMask; 450 451 uint32_t TxConfig; 452 uint32_t RxConfig; 453 uint32_t RxMissed; 454 455 uint16_t CSCR; 456 457 uint8_t Cfg9346; 458 uint8_t Config0; 459 uint8_t Config1; 460 uint8_t Config3; 461 uint8_t Config4; 462 uint8_t Config5; 463 464 uint8_t clock_enabled; 465 uint8_t bChipCmdState; 466 467 uint16_t MultiIntr; 468 469 uint16_t BasicModeCtrl; 470 uint16_t BasicModeStatus; 471 uint16_t NWayAdvert; 472 uint16_t NWayLPAR; 473 uint16_t NWayExpansion; 474 475 uint16_t CpCmd; 476 uint8_t TxThresh; 477 478 NICState *nic; 479 NICConf conf; 480 481 /* C ring mode */ 482 uint32_t currTxDesc; 483 484 /* C+ mode */ 485 uint32_t cplus_enabled; 486 487 uint32_t currCPlusRxDesc; 488 uint32_t currCPlusTxDesc; 489 490 uint32_t RxRingAddrLO; 491 uint32_t RxRingAddrHI; 492 493 EEprom9346 eeprom; 494 495 uint32_t TCTR; 496 uint32_t TimerInt; 497 int64_t TCTR_base; 498 499 /* Tally counters */ 500 RTL8139TallyCounters tally_counters; 501 502 /* Non-persistent data */ 503 uint8_t *cplus_txbuffer; 504 int cplus_txbuffer_len; 505 int cplus_txbuffer_offset; 506 507 /* PCI interrupt timer */ 508 QEMUTimer *timer; 509 510 MemoryRegion bar_io; 511 MemoryRegion bar_mem; 512 513 /* Support migration to/from old versions */ 514 int rtl8139_mmio_io_addr_dummy; 515 } RTL8139State; 516 517 /* Writes tally counters to memory via DMA */ 518 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr); 519 520 static void rtl8139_set_next_tctr_time(RTL8139State *s); 521 522 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) 523 { 524 DPRINTF("eeprom command 0x%02x\n", command); 525 526 switch (command & Chip9346_op_mask) 527 { 528 case Chip9346_op_read: 529 { 530 eeprom->address = command & EEPROM_9346_ADDR_MASK; 531 eeprom->output = eeprom->contents[eeprom->address]; 532 eeprom->eedo = 0; 533 eeprom->tick = 0; 534 eeprom->mode = Chip9346_data_read; 535 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", 536 eeprom->address, eeprom->output); 537 } 538 break; 539 540 case Chip9346_op_write: 541 { 542 eeprom->address = command & EEPROM_9346_ADDR_MASK; 543 eeprom->input = 0; 544 eeprom->tick = 0; 545 eeprom->mode = Chip9346_none; /* Chip9346_data_write */ 546 DPRINTF("eeprom begin write to address 0x%02x\n", 547 eeprom->address); 548 } 549 break; 550 default: 551 eeprom->mode = Chip9346_none; 552 switch (command & Chip9346_op_ext_mask) 553 { 554 case Chip9346_op_write_enable: 555 DPRINTF("eeprom write enabled\n"); 556 break; 557 case Chip9346_op_write_all: 558 DPRINTF("eeprom begin write all\n"); 559 break; 560 case Chip9346_op_write_disable: 561 DPRINTF("eeprom write disabled\n"); 562 break; 563 } 564 break; 565 } 566 } 567 568 static void prom9346_shift_clock(EEprom9346 *eeprom) 569 { 570 int bit = eeprom->eedi?1:0; 571 572 ++ eeprom->tick; 573 574 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, 575 eeprom->eedo); 576 577 switch (eeprom->mode) 578 { 579 case Chip9346_enter_command_mode: 580 if (bit) 581 { 582 eeprom->mode = Chip9346_read_command; 583 eeprom->tick = 0; 584 eeprom->input = 0; 585 DPRINTF("eeprom: +++ synchronized, begin command read\n"); 586 } 587 break; 588 589 case Chip9346_read_command: 590 eeprom->input = (eeprom->input << 1) | (bit & 1); 591 if (eeprom->tick == 8) 592 { 593 prom9346_decode_command(eeprom, eeprom->input & 0xff); 594 } 595 break; 596 597 case Chip9346_data_read: 598 eeprom->eedo = (eeprom->output & 0x8000)?1:0; 599 eeprom->output <<= 1; 600 if (eeprom->tick == 16) 601 { 602 #if 1 603 // the FreeBSD drivers (rl and re) don't explicitly toggle 604 // CS between reads (or does setting Cfg9346 to 0 count too?), 605 // so we need to enter wait-for-command state here 606 eeprom->mode = Chip9346_enter_command_mode; 607 eeprom->input = 0; 608 eeprom->tick = 0; 609 610 DPRINTF("eeprom: +++ end of read, awaiting next command\n"); 611 #else 612 // original behaviour 613 ++eeprom->address; 614 eeprom->address &= EEPROM_9346_ADDR_MASK; 615 eeprom->output = eeprom->contents[eeprom->address]; 616 eeprom->tick = 0; 617 618 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", 619 eeprom->address, eeprom->output); 620 #endif 621 } 622 break; 623 624 case Chip9346_data_write: 625 eeprom->input = (eeprom->input << 1) | (bit & 1); 626 if (eeprom->tick == 16) 627 { 628 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n", 629 eeprom->address, eeprom->input); 630 631 eeprom->contents[eeprom->address] = eeprom->input; 632 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ 633 eeprom->tick = 0; 634 eeprom->input = 0; 635 } 636 break; 637 638 case Chip9346_data_write_all: 639 eeprom->input = (eeprom->input << 1) | (bit & 1); 640 if (eeprom->tick == 16) 641 { 642 int i; 643 for (i = 0; i < EEPROM_9346_SIZE; i++) 644 { 645 eeprom->contents[i] = eeprom->input; 646 } 647 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); 648 649 eeprom->mode = Chip9346_enter_command_mode; 650 eeprom->tick = 0; 651 eeprom->input = 0; 652 } 653 break; 654 655 default: 656 break; 657 } 658 } 659 660 static int prom9346_get_wire(RTL8139State *s) 661 { 662 EEprom9346 *eeprom = &s->eeprom; 663 if (!eeprom->eecs) 664 return 0; 665 666 return eeprom->eedo; 667 } 668 669 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */ 670 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) 671 { 672 EEprom9346 *eeprom = &s->eeprom; 673 uint8_t old_eecs = eeprom->eecs; 674 uint8_t old_eesk = eeprom->eesk; 675 676 eeprom->eecs = eecs; 677 eeprom->eesk = eesk; 678 eeprom->eedi = eedi; 679 680 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, 681 eeprom->eesk, eeprom->eedi, eeprom->eedo); 682 683 if (!old_eecs && eecs) 684 { 685 /* Synchronize start */ 686 eeprom->tick = 0; 687 eeprom->input = 0; 688 eeprom->output = 0; 689 eeprom->mode = Chip9346_enter_command_mode; 690 691 DPRINTF("=== eeprom: begin access, enter command mode\n"); 692 } 693 694 if (!eecs) 695 { 696 DPRINTF("=== eeprom: end access\n"); 697 return; 698 } 699 700 if (!old_eesk && eesk) 701 { 702 /* SK front rules */ 703 prom9346_shift_clock(eeprom); 704 } 705 } 706 707 static void rtl8139_update_irq(RTL8139State *s) 708 { 709 PCIDevice *d = PCI_DEVICE(s); 710 int isr; 711 isr = (s->IntrStatus & s->IntrMask) & 0xffff; 712 713 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, 714 s->IntrMask); 715 716 pci_set_irq(d, (isr != 0)); 717 } 718 719 static int rtl8139_RxWrap(RTL8139State *s) 720 { 721 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */ 722 return (s->RxConfig & (1 << 7)); 723 } 724 725 static int rtl8139_receiver_enabled(RTL8139State *s) 726 { 727 return s->bChipCmdState & CmdRxEnb; 728 } 729 730 static int rtl8139_transmitter_enabled(RTL8139State *s) 731 { 732 return s->bChipCmdState & CmdTxEnb; 733 } 734 735 static int rtl8139_cp_receiver_enabled(RTL8139State *s) 736 { 737 return s->CpCmd & CPlusRxEnb; 738 } 739 740 static int rtl8139_cp_transmitter_enabled(RTL8139State *s) 741 { 742 return s->CpCmd & CPlusTxEnb; 743 } 744 745 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) 746 { 747 PCIDevice *d = PCI_DEVICE(s); 748 749 if (s->RxBufAddr + size > s->RxBufferSize) 750 { 751 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); 752 753 /* write packet data */ 754 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) 755 { 756 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped); 757 758 if (size > wrapped) 759 { 760 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 761 buf, size-wrapped); 762 } 763 764 /* reset buffer pointer */ 765 s->RxBufAddr = 0; 766 767 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 768 buf + (size-wrapped), wrapped); 769 770 s->RxBufAddr = wrapped; 771 772 return; 773 } 774 } 775 776 /* non-wrapping path or overwrapping enabled */ 777 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size); 778 779 s->RxBufAddr += size; 780 } 781 782 #define MIN_BUF_SIZE 60 783 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high) 784 { 785 return low | ((uint64_t)high << 32); 786 } 787 788 /* Workaround for buggy guest driver such as linux who allocates rx 789 * rings after the receiver were enabled. */ 790 static bool rtl8139_cp_rx_valid(RTL8139State *s) 791 { 792 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0); 793 } 794 795 static int rtl8139_can_receive(NetClientState *nc) 796 { 797 RTL8139State *s = qemu_get_nic_opaque(nc); 798 int avail; 799 800 /* Receive (drop) packets if card is disabled. */ 801 if (!s->clock_enabled) 802 return 1; 803 if (!rtl8139_receiver_enabled(s)) 804 return 1; 805 806 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) { 807 /* ??? Flow control not implemented in c+ mode. 808 This is a hack to work around slirp deficiencies anyway. */ 809 return 1; 810 } else { 811 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, 812 s->RxBufferSize); 813 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow)); 814 } 815 } 816 817 static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) 818 { 819 RTL8139State *s = qemu_get_nic_opaque(nc); 820 PCIDevice *d = PCI_DEVICE(s); 821 /* size is the length of the buffer passed to the driver */ 822 int size = size_; 823 const uint8_t *dot1q_buf = NULL; 824 825 uint32_t packet_header = 0; 826 827 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; 828 static const uint8_t broadcast_macaddr[6] = 829 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 830 831 DPRINTF(">>> received len=%d\n", size); 832 833 /* test if board clock is stopped */ 834 if (!s->clock_enabled) 835 { 836 DPRINTF("stopped ==========================\n"); 837 return -1; 838 } 839 840 /* first check if receiver is enabled */ 841 842 if (!rtl8139_receiver_enabled(s)) 843 { 844 DPRINTF("receiver disabled ================\n"); 845 return -1; 846 } 847 848 /* XXX: check this */ 849 if (s->RxConfig & AcceptAllPhys) { 850 /* promiscuous: receive all */ 851 DPRINTF(">>> packet received in promiscuous mode\n"); 852 853 } else { 854 if (!memcmp(buf, broadcast_macaddr, 6)) { 855 /* broadcast address */ 856 if (!(s->RxConfig & AcceptBroadcast)) 857 { 858 DPRINTF(">>> broadcast packet rejected\n"); 859 860 /* update tally counter */ 861 ++s->tally_counters.RxERR; 862 863 return size; 864 } 865 866 packet_header |= RxBroadcast; 867 868 DPRINTF(">>> broadcast packet received\n"); 869 870 /* update tally counter */ 871 ++s->tally_counters.RxOkBrd; 872 873 } else if (buf[0] & 0x01) { 874 /* multicast */ 875 if (!(s->RxConfig & AcceptMulticast)) 876 { 877 DPRINTF(">>> multicast packet rejected\n"); 878 879 /* update tally counter */ 880 ++s->tally_counters.RxERR; 881 882 return size; 883 } 884 885 int mcast_idx = compute_mcast_idx(buf); 886 887 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) 888 { 889 DPRINTF(">>> multicast address mismatch\n"); 890 891 /* update tally counter */ 892 ++s->tally_counters.RxERR; 893 894 return size; 895 } 896 897 packet_header |= RxMulticast; 898 899 DPRINTF(">>> multicast packet received\n"); 900 901 /* update tally counter */ 902 ++s->tally_counters.RxOkMul; 903 904 } else if (s->phys[0] == buf[0] && 905 s->phys[1] == buf[1] && 906 s->phys[2] == buf[2] && 907 s->phys[3] == buf[3] && 908 s->phys[4] == buf[4] && 909 s->phys[5] == buf[5]) { 910 /* match */ 911 if (!(s->RxConfig & AcceptMyPhys)) 912 { 913 DPRINTF(">>> rejecting physical address matching packet\n"); 914 915 /* update tally counter */ 916 ++s->tally_counters.RxERR; 917 918 return size; 919 } 920 921 packet_header |= RxPhysical; 922 923 DPRINTF(">>> physical address matching packet received\n"); 924 925 /* update tally counter */ 926 ++s->tally_counters.RxOkPhy; 927 928 } else { 929 930 DPRINTF(">>> unknown packet\n"); 931 932 /* update tally counter */ 933 ++s->tally_counters.RxERR; 934 935 return size; 936 } 937 } 938 939 /* if too small buffer, then expand it 940 * Include some tailroom in case a vlan tag is later removed. */ 941 if (size < MIN_BUF_SIZE + VLAN_HLEN) { 942 memcpy(buf1, buf, size); 943 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size); 944 buf = buf1; 945 if (size < MIN_BUF_SIZE) { 946 size = MIN_BUF_SIZE; 947 } 948 } 949 950 if (rtl8139_cp_receiver_enabled(s)) 951 { 952 if (!rtl8139_cp_rx_valid(s)) { 953 return size; 954 } 955 956 DPRINTF("in C+ Rx mode ================\n"); 957 958 /* begin C+ receiver mode */ 959 960 /* w0 ownership flag */ 961 #define CP_RX_OWN (1<<31) 962 /* w0 end of ring flag */ 963 #define CP_RX_EOR (1<<30) 964 /* w0 bits 0...12 : buffer size */ 965 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) 966 /* w1 tag available flag */ 967 #define CP_RX_TAVA (1<<16) 968 /* w1 bits 0...15 : VLAN tag */ 969 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) 970 /* w2 low 32bit of Rx buffer ptr */ 971 /* w3 high 32bit of Rx buffer ptr */ 972 973 int descriptor = s->currCPlusRxDesc; 974 dma_addr_t cplus_rx_ring_desc; 975 976 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); 977 cplus_rx_ring_desc += 16 * descriptor; 978 979 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at " 980 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI, 981 s->RxRingAddrLO, cplus_rx_ring_desc); 982 983 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; 984 985 pci_dma_read(d, cplus_rx_ring_desc, &val, 4); 986 rxdw0 = le32_to_cpu(val); 987 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4); 988 rxdw1 = le32_to_cpu(val); 989 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4); 990 rxbufLO = le32_to_cpu(val); 991 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4); 992 rxbufHI = le32_to_cpu(val); 993 994 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", 995 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); 996 997 if (!(rxdw0 & CP_RX_OWN)) 998 { 999 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n", 1000 descriptor); 1001 1002 s->IntrStatus |= RxOverflow; 1003 ++s->RxMissed; 1004 1005 /* update tally counter */ 1006 ++s->tally_counters.RxERR; 1007 ++s->tally_counters.MissPkt; 1008 1009 rtl8139_update_irq(s); 1010 return size_; 1011 } 1012 1013 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; 1014 1015 /* write VLAN info to descriptor variables. */ 1016 if (s->CpCmd & CPlusRxVLAN && 1017 lduw_be_p(&buf[ETH_ALEN * 2]) == ETH_P_VLAN) { 1018 dot1q_buf = &buf[ETH_ALEN * 2]; 1019 size -= VLAN_HLEN; 1020 /* if too small buffer, use the tailroom added duing expansion */ 1021 if (size < MIN_BUF_SIZE) { 1022 size = MIN_BUF_SIZE; 1023 } 1024 1025 rxdw1 &= ~CP_RX_VLAN_TAG_MASK; 1026 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */ 1027 rxdw1 |= CP_RX_TAVA | lduw_le_p(&dot1q_buf[ETHER_TYPE_LEN]); 1028 1029 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", 1030 lduw_be_p(&dot1q_buf[ETHER_TYPE_LEN])); 1031 } else { 1032 /* reset VLAN tag flag */ 1033 rxdw1 &= ~CP_RX_TAVA; 1034 } 1035 1036 /* TODO: scatter the packet over available receive ring descriptors space */ 1037 1038 if (size+4 > rx_space) 1039 { 1040 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n", 1041 descriptor, rx_space, size); 1042 1043 s->IntrStatus |= RxOverflow; 1044 ++s->RxMissed; 1045 1046 /* update tally counter */ 1047 ++s->tally_counters.RxERR; 1048 ++s->tally_counters.MissPkt; 1049 1050 rtl8139_update_irq(s); 1051 return size_; 1052 } 1053 1054 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); 1055 1056 /* receive/copy to target memory */ 1057 if (dot1q_buf) { 1058 pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN); 1059 pci_dma_write(d, rx_addr + 2 * ETH_ALEN, 1060 buf + 2 * ETH_ALEN + VLAN_HLEN, 1061 size - 2 * ETH_ALEN); 1062 } else { 1063 pci_dma_write(d, rx_addr, buf, size); 1064 } 1065 1066 if (s->CpCmd & CPlusRxChkSum) 1067 { 1068 /* do some packet checksumming */ 1069 } 1070 1071 /* write checksum */ 1072 val = cpu_to_le32(crc32(0, buf, size_)); 1073 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4); 1074 1075 /* first segment of received packet flag */ 1076 #define CP_RX_STATUS_FS (1<<29) 1077 /* last segment of received packet flag */ 1078 #define CP_RX_STATUS_LS (1<<28) 1079 /* multicast packet flag */ 1080 #define CP_RX_STATUS_MAR (1<<26) 1081 /* physical-matching packet flag */ 1082 #define CP_RX_STATUS_PAM (1<<25) 1083 /* broadcast packet flag */ 1084 #define CP_RX_STATUS_BAR (1<<24) 1085 /* runt packet flag */ 1086 #define CP_RX_STATUS_RUNT (1<<19) 1087 /* crc error flag */ 1088 #define CP_RX_STATUS_CRC (1<<18) 1089 /* IP checksum error flag */ 1090 #define CP_RX_STATUS_IPF (1<<15) 1091 /* UDP checksum error flag */ 1092 #define CP_RX_STATUS_UDPF (1<<14) 1093 /* TCP checksum error flag */ 1094 #define CP_RX_STATUS_TCPF (1<<13) 1095 1096 /* transfer ownership to target */ 1097 rxdw0 &= ~CP_RX_OWN; 1098 1099 /* set first segment bit */ 1100 rxdw0 |= CP_RX_STATUS_FS; 1101 1102 /* set last segment bit */ 1103 rxdw0 |= CP_RX_STATUS_LS; 1104 1105 /* set received packet type flags */ 1106 if (packet_header & RxBroadcast) 1107 rxdw0 |= CP_RX_STATUS_BAR; 1108 if (packet_header & RxMulticast) 1109 rxdw0 |= CP_RX_STATUS_MAR; 1110 if (packet_header & RxPhysical) 1111 rxdw0 |= CP_RX_STATUS_PAM; 1112 1113 /* set received size */ 1114 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; 1115 rxdw0 |= (size+4); 1116 1117 /* update ring data */ 1118 val = cpu_to_le32(rxdw0); 1119 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4); 1120 val = cpu_to_le32(rxdw1); 1121 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4); 1122 1123 /* update tally counter */ 1124 ++s->tally_counters.RxOk; 1125 1126 /* seek to next Rx descriptor */ 1127 if (rxdw0 & CP_RX_EOR) 1128 { 1129 s->currCPlusRxDesc = 0; 1130 } 1131 else 1132 { 1133 ++s->currCPlusRxDesc; 1134 } 1135 1136 DPRINTF("done C+ Rx mode ----------------\n"); 1137 1138 } 1139 else 1140 { 1141 DPRINTF("in ring Rx mode ================\n"); 1142 1143 /* begin ring receiver mode */ 1144 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); 1145 1146 /* if receiver buffer is empty then avail == 0 */ 1147 1148 #define RX_ALIGN(x) (((x) + 3) & ~0x3) 1149 1150 if (avail != 0 && RX_ALIGN(size + 8) >= avail) 1151 { 1152 DPRINTF("rx overflow: rx buffer length %d head 0x%04x " 1153 "read 0x%04x === available 0x%04x need 0x%04x\n", 1154 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); 1155 1156 s->IntrStatus |= RxOverflow; 1157 ++s->RxMissed; 1158 rtl8139_update_irq(s); 1159 return 0; 1160 } 1161 1162 packet_header |= RxStatusOK; 1163 1164 packet_header |= (((size+4) << 16) & 0xffff0000); 1165 1166 /* write header */ 1167 uint32_t val = cpu_to_le32(packet_header); 1168 1169 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1170 1171 rtl8139_write_buffer(s, buf, size); 1172 1173 /* write checksum */ 1174 val = cpu_to_le32(crc32(0, buf, size)); 1175 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1176 1177 /* correct buffer write pointer */ 1178 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize); 1179 1180 /* now we can signal we have received something */ 1181 1182 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n", 1183 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 1184 } 1185 1186 s->IntrStatus |= RxOK; 1187 1188 if (do_interrupt) 1189 { 1190 rtl8139_update_irq(s); 1191 } 1192 1193 return size_; 1194 } 1195 1196 static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1197 { 1198 return rtl8139_do_receive(nc, buf, size, 1); 1199 } 1200 1201 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) 1202 { 1203 s->RxBufferSize = bufferSize; 1204 s->RxBufPtr = 0; 1205 s->RxBufAddr = 0; 1206 } 1207 1208 static void rtl8139_reset(DeviceState *d) 1209 { 1210 RTL8139State *s = RTL8139(d); 1211 int i; 1212 1213 /* restore MAC address */ 1214 memcpy(s->phys, s->conf.macaddr.a, 6); 1215 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 1216 1217 /* reset interrupt mask */ 1218 s->IntrStatus = 0; 1219 s->IntrMask = 0; 1220 1221 rtl8139_update_irq(s); 1222 1223 /* mark all status registers as owned by host */ 1224 for (i = 0; i < 4; ++i) 1225 { 1226 s->TxStatus[i] = TxHostOwns; 1227 } 1228 1229 s->currTxDesc = 0; 1230 s->currCPlusRxDesc = 0; 1231 s->currCPlusTxDesc = 0; 1232 1233 s->RxRingAddrLO = 0; 1234 s->RxRingAddrHI = 0; 1235 1236 s->RxBuf = 0; 1237 1238 rtl8139_reset_rxring(s, 8192); 1239 1240 /* ACK the reset */ 1241 s->TxConfig = 0; 1242 1243 #if 0 1244 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk 1245 s->clock_enabled = 0; 1246 #else 1247 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake 1248 s->clock_enabled = 1; 1249 #endif 1250 1251 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; 1252 1253 /* set initial state data */ 1254 s->Config0 = 0x0; /* No boot ROM */ 1255 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ 1256 s->Config3 = 0x1; /* fast back-to-back compatible */ 1257 s->Config5 = 0x0; 1258 1259 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; 1260 1261 s->CpCmd = 0x0; /* reset C+ mode */ 1262 s->cplus_enabled = 0; 1263 1264 1265 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation 1266 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex 1267 s->BasicModeCtrl = 0x1000; // autonegotiation 1268 1269 s->BasicModeStatus = 0x7809; 1270 //s->BasicModeStatus |= 0x0040; /* UTP medium */ 1271 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ 1272 /* preserve link state */ 1273 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04; 1274 1275 s->NWayAdvert = 0x05e1; /* all modes, full duplex */ 1276 s->NWayLPAR = 0x05e1; /* all modes, full duplex */ 1277 s->NWayExpansion = 0x0001; /* autonegotiation supported */ 1278 1279 /* also reset timer and disable timer interrupt */ 1280 s->TCTR = 0; 1281 s->TimerInt = 0; 1282 s->TCTR_base = 0; 1283 rtl8139_set_next_tctr_time(s); 1284 1285 /* reset tally counters */ 1286 RTL8139TallyCounters_clear(&s->tally_counters); 1287 } 1288 1289 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) 1290 { 1291 counters->TxOk = 0; 1292 counters->RxOk = 0; 1293 counters->TxERR = 0; 1294 counters->RxERR = 0; 1295 counters->MissPkt = 0; 1296 counters->FAE = 0; 1297 counters->Tx1Col = 0; 1298 counters->TxMCol = 0; 1299 counters->RxOkPhy = 0; 1300 counters->RxOkBrd = 0; 1301 counters->RxOkMul = 0; 1302 counters->TxAbt = 0; 1303 counters->TxUndrn = 0; 1304 } 1305 1306 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr) 1307 { 1308 PCIDevice *d = PCI_DEVICE(s); 1309 RTL8139TallyCounters *tally_counters = &s->tally_counters; 1310 uint16_t val16; 1311 uint32_t val32; 1312 uint64_t val64; 1313 1314 val64 = cpu_to_le64(tally_counters->TxOk); 1315 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8); 1316 1317 val64 = cpu_to_le64(tally_counters->RxOk); 1318 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8); 1319 1320 val64 = cpu_to_le64(tally_counters->TxERR); 1321 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8); 1322 1323 val32 = cpu_to_le32(tally_counters->RxERR); 1324 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4); 1325 1326 val16 = cpu_to_le16(tally_counters->MissPkt); 1327 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2); 1328 1329 val16 = cpu_to_le16(tally_counters->FAE); 1330 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2); 1331 1332 val32 = cpu_to_le32(tally_counters->Tx1Col); 1333 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4); 1334 1335 val32 = cpu_to_le32(tally_counters->TxMCol); 1336 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4); 1337 1338 val64 = cpu_to_le64(tally_counters->RxOkPhy); 1339 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8); 1340 1341 val64 = cpu_to_le64(tally_counters->RxOkBrd); 1342 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8); 1343 1344 val32 = cpu_to_le32(tally_counters->RxOkMul); 1345 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4); 1346 1347 val16 = cpu_to_le16(tally_counters->TxAbt); 1348 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2); 1349 1350 val16 = cpu_to_le16(tally_counters->TxUndrn); 1351 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2); 1352 } 1353 1354 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) 1355 { 1356 DeviceState *d = DEVICE(s); 1357 1358 val &= 0xff; 1359 1360 DPRINTF("ChipCmd write val=0x%08x\n", val); 1361 1362 if (val & CmdReset) 1363 { 1364 DPRINTF("ChipCmd reset\n"); 1365 rtl8139_reset(d); 1366 } 1367 if (val & CmdRxEnb) 1368 { 1369 DPRINTF("ChipCmd enable receiver\n"); 1370 1371 s->currCPlusRxDesc = 0; 1372 } 1373 if (val & CmdTxEnb) 1374 { 1375 DPRINTF("ChipCmd enable transmitter\n"); 1376 1377 s->currCPlusTxDesc = 0; 1378 } 1379 1380 /* mask unwritable bits */ 1381 val = SET_MASKED(val, 0xe3, s->bChipCmdState); 1382 1383 /* Deassert reset pin before next read */ 1384 val &= ~CmdReset; 1385 1386 s->bChipCmdState = val; 1387 } 1388 1389 static int rtl8139_RxBufferEmpty(RTL8139State *s) 1390 { 1391 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); 1392 1393 if (unread != 0) 1394 { 1395 DPRINTF("receiver buffer data available 0x%04x\n", unread); 1396 return 0; 1397 } 1398 1399 DPRINTF("receiver buffer is empty\n"); 1400 1401 return 1; 1402 } 1403 1404 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s) 1405 { 1406 uint32_t ret = s->bChipCmdState; 1407 1408 if (rtl8139_RxBufferEmpty(s)) 1409 ret |= RxBufEmpty; 1410 1411 DPRINTF("ChipCmd read val=0x%04x\n", ret); 1412 1413 return ret; 1414 } 1415 1416 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) 1417 { 1418 val &= 0xffff; 1419 1420 DPRINTF("C+ command register write(w) val=0x%04x\n", val); 1421 1422 s->cplus_enabled = 1; 1423 1424 /* mask unwritable bits */ 1425 val = SET_MASKED(val, 0xff84, s->CpCmd); 1426 1427 s->CpCmd = val; 1428 } 1429 1430 static uint32_t rtl8139_CpCmd_read(RTL8139State *s) 1431 { 1432 uint32_t ret = s->CpCmd; 1433 1434 DPRINTF("C+ command register read(w) val=0x%04x\n", ret); 1435 1436 return ret; 1437 } 1438 1439 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) 1440 { 1441 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val); 1442 } 1443 1444 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s) 1445 { 1446 uint32_t ret = 0; 1447 1448 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret); 1449 1450 return ret; 1451 } 1452 1453 static int rtl8139_config_writable(RTL8139State *s) 1454 { 1455 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite) 1456 { 1457 return 1; 1458 } 1459 1460 DPRINTF("Configuration registers are write-protected\n"); 1461 1462 return 0; 1463 } 1464 1465 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) 1466 { 1467 val &= 0xffff; 1468 1469 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val); 1470 1471 /* mask unwritable bits */ 1472 uint32_t mask = 0x4cff; 1473 1474 if (1 || !rtl8139_config_writable(s)) 1475 { 1476 /* Speed setting and autonegotiation enable bits are read-only */ 1477 mask |= 0x3000; 1478 /* Duplex mode setting is read-only */ 1479 mask |= 0x0100; 1480 } 1481 1482 val = SET_MASKED(val, mask, s->BasicModeCtrl); 1483 1484 s->BasicModeCtrl = val; 1485 } 1486 1487 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s) 1488 { 1489 uint32_t ret = s->BasicModeCtrl; 1490 1491 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret); 1492 1493 return ret; 1494 } 1495 1496 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) 1497 { 1498 val &= 0xffff; 1499 1500 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val); 1501 1502 /* mask unwritable bits */ 1503 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); 1504 1505 s->BasicModeStatus = val; 1506 } 1507 1508 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s) 1509 { 1510 uint32_t ret = s->BasicModeStatus; 1511 1512 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret); 1513 1514 return ret; 1515 } 1516 1517 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) 1518 { 1519 DeviceState *d = DEVICE(s); 1520 1521 val &= 0xff; 1522 1523 DPRINTF("Cfg9346 write val=0x%02x\n", val); 1524 1525 /* mask unwritable bits */ 1526 val = SET_MASKED(val, 0x31, s->Cfg9346); 1527 1528 uint32_t opmode = val & 0xc0; 1529 uint32_t eeprom_val = val & 0xf; 1530 1531 if (opmode == 0x80) { 1532 /* eeprom access */ 1533 int eecs = (eeprom_val & 0x08)?1:0; 1534 int eesk = (eeprom_val & 0x04)?1:0; 1535 int eedi = (eeprom_val & 0x02)?1:0; 1536 prom9346_set_wire(s, eecs, eesk, eedi); 1537 } else if (opmode == 0x40) { 1538 /* Reset. */ 1539 val = 0; 1540 rtl8139_reset(d); 1541 } 1542 1543 s->Cfg9346 = val; 1544 } 1545 1546 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s) 1547 { 1548 uint32_t ret = s->Cfg9346; 1549 1550 uint32_t opmode = ret & 0xc0; 1551 1552 if (opmode == 0x80) 1553 { 1554 /* eeprom access */ 1555 int eedo = prom9346_get_wire(s); 1556 if (eedo) 1557 { 1558 ret |= 0x01; 1559 } 1560 else 1561 { 1562 ret &= ~0x01; 1563 } 1564 } 1565 1566 DPRINTF("Cfg9346 read val=0x%02x\n", ret); 1567 1568 return ret; 1569 } 1570 1571 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) 1572 { 1573 val &= 0xff; 1574 1575 DPRINTF("Config0 write val=0x%02x\n", val); 1576 1577 if (!rtl8139_config_writable(s)) { 1578 return; 1579 } 1580 1581 /* mask unwritable bits */ 1582 val = SET_MASKED(val, 0xf8, s->Config0); 1583 1584 s->Config0 = val; 1585 } 1586 1587 static uint32_t rtl8139_Config0_read(RTL8139State *s) 1588 { 1589 uint32_t ret = s->Config0; 1590 1591 DPRINTF("Config0 read val=0x%02x\n", ret); 1592 1593 return ret; 1594 } 1595 1596 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) 1597 { 1598 val &= 0xff; 1599 1600 DPRINTF("Config1 write val=0x%02x\n", val); 1601 1602 if (!rtl8139_config_writable(s)) { 1603 return; 1604 } 1605 1606 /* mask unwritable bits */ 1607 val = SET_MASKED(val, 0xC, s->Config1); 1608 1609 s->Config1 = val; 1610 } 1611 1612 static uint32_t rtl8139_Config1_read(RTL8139State *s) 1613 { 1614 uint32_t ret = s->Config1; 1615 1616 DPRINTF("Config1 read val=0x%02x\n", ret); 1617 1618 return ret; 1619 } 1620 1621 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) 1622 { 1623 val &= 0xff; 1624 1625 DPRINTF("Config3 write val=0x%02x\n", val); 1626 1627 if (!rtl8139_config_writable(s)) { 1628 return; 1629 } 1630 1631 /* mask unwritable bits */ 1632 val = SET_MASKED(val, 0x8F, s->Config3); 1633 1634 s->Config3 = val; 1635 } 1636 1637 static uint32_t rtl8139_Config3_read(RTL8139State *s) 1638 { 1639 uint32_t ret = s->Config3; 1640 1641 DPRINTF("Config3 read val=0x%02x\n", ret); 1642 1643 return ret; 1644 } 1645 1646 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) 1647 { 1648 val &= 0xff; 1649 1650 DPRINTF("Config4 write val=0x%02x\n", val); 1651 1652 if (!rtl8139_config_writable(s)) { 1653 return; 1654 } 1655 1656 /* mask unwritable bits */ 1657 val = SET_MASKED(val, 0x0a, s->Config4); 1658 1659 s->Config4 = val; 1660 } 1661 1662 static uint32_t rtl8139_Config4_read(RTL8139State *s) 1663 { 1664 uint32_t ret = s->Config4; 1665 1666 DPRINTF("Config4 read val=0x%02x\n", ret); 1667 1668 return ret; 1669 } 1670 1671 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) 1672 { 1673 val &= 0xff; 1674 1675 DPRINTF("Config5 write val=0x%02x\n", val); 1676 1677 /* mask unwritable bits */ 1678 val = SET_MASKED(val, 0x80, s->Config5); 1679 1680 s->Config5 = val; 1681 } 1682 1683 static uint32_t rtl8139_Config5_read(RTL8139State *s) 1684 { 1685 uint32_t ret = s->Config5; 1686 1687 DPRINTF("Config5 read val=0x%02x\n", ret); 1688 1689 return ret; 1690 } 1691 1692 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) 1693 { 1694 if (!rtl8139_transmitter_enabled(s)) 1695 { 1696 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val); 1697 return; 1698 } 1699 1700 DPRINTF("TxConfig write val=0x%08x\n", val); 1701 1702 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); 1703 1704 s->TxConfig = val; 1705 } 1706 1707 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) 1708 { 1709 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val); 1710 1711 uint32_t tc = s->TxConfig; 1712 tc &= 0xFFFFFF00; 1713 tc |= (val & 0x000000FF); 1714 rtl8139_TxConfig_write(s, tc); 1715 } 1716 1717 static uint32_t rtl8139_TxConfig_read(RTL8139State *s) 1718 { 1719 uint32_t ret = s->TxConfig; 1720 1721 DPRINTF("TxConfig read val=0x%04x\n", ret); 1722 1723 return ret; 1724 } 1725 1726 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) 1727 { 1728 DPRINTF("RxConfig write val=0x%08x\n", val); 1729 1730 /* mask unwritable bits */ 1731 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); 1732 1733 s->RxConfig = val; 1734 1735 /* reset buffer size and read/write pointers */ 1736 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); 1737 1738 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize); 1739 } 1740 1741 static uint32_t rtl8139_RxConfig_read(RTL8139State *s) 1742 { 1743 uint32_t ret = s->RxConfig; 1744 1745 DPRINTF("RxConfig read val=0x%08x\n", ret); 1746 1747 return ret; 1748 } 1749 1750 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, 1751 int do_interrupt, const uint8_t *dot1q_buf) 1752 { 1753 struct iovec *iov = NULL; 1754 struct iovec vlan_iov[3]; 1755 1756 if (!size) 1757 { 1758 DPRINTF("+++ empty ethernet frame\n"); 1759 return; 1760 } 1761 1762 if (dot1q_buf && size >= ETH_ALEN * 2) { 1763 iov = (struct iovec[3]) { 1764 { .iov_base = buf, .iov_len = ETH_ALEN * 2 }, 1765 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN }, 1766 { .iov_base = buf + ETH_ALEN * 2, 1767 .iov_len = size - ETH_ALEN * 2 }, 1768 }; 1769 1770 memcpy(vlan_iov, iov, sizeof(vlan_iov)); 1771 iov = vlan_iov; 1772 } 1773 1774 if (TxLoopBack == (s->TxConfig & TxLoopBack)) 1775 { 1776 size_t buf2_size; 1777 uint8_t *buf2; 1778 1779 if (iov) { 1780 buf2_size = iov_size(iov, 3); 1781 buf2 = g_malloc(buf2_size); 1782 iov_to_buf(iov, 3, 0, buf2, buf2_size); 1783 buf = buf2; 1784 } 1785 1786 DPRINTF("+++ transmit loopback mode\n"); 1787 rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt); 1788 1789 if (iov) { 1790 g_free(buf2); 1791 } 1792 } 1793 else 1794 { 1795 if (iov) { 1796 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3); 1797 } else { 1798 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 1799 } 1800 } 1801 } 1802 1803 static int rtl8139_transmit_one(RTL8139State *s, int descriptor) 1804 { 1805 if (!rtl8139_transmitter_enabled(s)) 1806 { 1807 DPRINTF("+++ cannot transmit from descriptor %d: transmitter " 1808 "disabled\n", descriptor); 1809 return 0; 1810 } 1811 1812 if (s->TxStatus[descriptor] & TxHostOwns) 1813 { 1814 DPRINTF("+++ cannot transmit from descriptor %d: owned by host " 1815 "(%08x)\n", descriptor, s->TxStatus[descriptor]); 1816 return 0; 1817 } 1818 1819 DPRINTF("+++ transmitting from descriptor %d\n", descriptor); 1820 1821 PCIDevice *d = PCI_DEVICE(s); 1822 int txsize = s->TxStatus[descriptor] & 0x1fff; 1823 uint8_t txbuffer[0x2000]; 1824 1825 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n", 1826 txsize, s->TxAddr[descriptor]); 1827 1828 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize); 1829 1830 /* Mark descriptor as transferred */ 1831 s->TxStatus[descriptor] |= TxHostOwns; 1832 s->TxStatus[descriptor] |= TxStatOK; 1833 1834 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); 1835 1836 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize, 1837 descriptor); 1838 1839 /* update interrupt */ 1840 s->IntrStatus |= TxOK; 1841 rtl8139_update_irq(s); 1842 1843 return 1; 1844 } 1845 1846 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off))) 1847 1848 /* produces ones' complement sum of data */ 1849 static uint16_t ones_complement_sum(uint8_t *data, size_t len) 1850 { 1851 uint32_t result = 0; 1852 1853 for (; len > 1; data+=2, len-=2) 1854 { 1855 result += *(uint16_t*)data; 1856 } 1857 1858 /* add the remainder byte */ 1859 if (len) 1860 { 1861 uint8_t odd[2] = {*data, 0}; 1862 result += *(uint16_t*)odd; 1863 } 1864 1865 while (result>>16) 1866 result = (result & 0xffff) + (result >> 16); 1867 1868 return result; 1869 } 1870 1871 static uint16_t ip_checksum(void *data, size_t len) 1872 { 1873 return ~ones_complement_sum((uint8_t*)data, len); 1874 } 1875 1876 static int rtl8139_cplus_transmit_one(RTL8139State *s) 1877 { 1878 if (!rtl8139_transmitter_enabled(s)) 1879 { 1880 DPRINTF("+++ C+ mode: transmitter disabled\n"); 1881 return 0; 1882 } 1883 1884 if (!rtl8139_cp_transmitter_enabled(s)) 1885 { 1886 DPRINTF("+++ C+ mode: C+ transmitter disabled\n"); 1887 return 0 ; 1888 } 1889 1890 PCIDevice *d = PCI_DEVICE(s); 1891 int descriptor = s->currCPlusTxDesc; 1892 1893 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); 1894 1895 /* Normal priority ring */ 1896 cplus_tx_ring_desc += 16 * descriptor; 1897 1898 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at " 1899 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], 1900 s->TxAddr[0], cplus_tx_ring_desc); 1901 1902 uint32_t val, txdw0,txdw1,txbufLO,txbufHI; 1903 1904 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 1905 txdw0 = le32_to_cpu(val); 1906 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4); 1907 txdw1 = le32_to_cpu(val); 1908 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4); 1909 txbufLO = le32_to_cpu(val); 1910 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4); 1911 txbufHI = le32_to_cpu(val); 1912 1913 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor, 1914 txdw0, txdw1, txbufLO, txbufHI); 1915 1916 /* w0 ownership flag */ 1917 #define CP_TX_OWN (1<<31) 1918 /* w0 end of ring flag */ 1919 #define CP_TX_EOR (1<<30) 1920 /* first segment of received packet flag */ 1921 #define CP_TX_FS (1<<29) 1922 /* last segment of received packet flag */ 1923 #define CP_TX_LS (1<<28) 1924 /* large send packet flag */ 1925 #define CP_TX_LGSEN (1<<27) 1926 /* large send MSS mask, bits 16...25 */ 1927 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) 1928 1929 /* IP checksum offload flag */ 1930 #define CP_TX_IPCS (1<<18) 1931 /* UDP checksum offload flag */ 1932 #define CP_TX_UDPCS (1<<17) 1933 /* TCP checksum offload flag */ 1934 #define CP_TX_TCPCS (1<<16) 1935 1936 /* w0 bits 0...15 : buffer size */ 1937 #define CP_TX_BUFFER_SIZE (1<<16) 1938 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) 1939 /* w1 add tag flag */ 1940 #define CP_TX_TAGC (1<<17) 1941 /* w1 bits 0...15 : VLAN tag (big endian) */ 1942 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) 1943 /* w2 low 32bit of Rx buffer ptr */ 1944 /* w3 high 32bit of Rx buffer ptr */ 1945 1946 /* set after transmission */ 1947 /* FIFO underrun flag */ 1948 #define CP_TX_STATUS_UNF (1<<25) 1949 /* transmit error summary flag, valid if set any of three below */ 1950 #define CP_TX_STATUS_TES (1<<23) 1951 /* out-of-window collision flag */ 1952 #define CP_TX_STATUS_OWC (1<<22) 1953 /* link failure flag */ 1954 #define CP_TX_STATUS_LNKF (1<<21) 1955 /* excessive collisions flag */ 1956 #define CP_TX_STATUS_EXC (1<<20) 1957 1958 if (!(txdw0 & CP_TX_OWN)) 1959 { 1960 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor); 1961 return 0 ; 1962 } 1963 1964 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor); 1965 1966 if (txdw0 & CP_TX_FS) 1967 { 1968 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment " 1969 "descriptor\n", descriptor); 1970 1971 /* reset internal buffer offset */ 1972 s->cplus_txbuffer_offset = 0; 1973 } 1974 1975 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; 1976 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); 1977 1978 /* make sure we have enough space to assemble the packet */ 1979 if (!s->cplus_txbuffer) 1980 { 1981 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; 1982 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len); 1983 s->cplus_txbuffer_offset = 0; 1984 1985 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n", 1986 s->cplus_txbuffer_len); 1987 } 1988 1989 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) 1990 { 1991 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */ 1992 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; 1993 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor" 1994 "length to %d\n", txsize); 1995 } 1996 1997 /* append more data to the packet */ 1998 1999 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at " 2000 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr, 2001 s->cplus_txbuffer_offset); 2002 2003 pci_dma_read(d, tx_addr, 2004 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); 2005 s->cplus_txbuffer_offset += txsize; 2006 2007 /* seek to next Rx descriptor */ 2008 if (txdw0 & CP_TX_EOR) 2009 { 2010 s->currCPlusTxDesc = 0; 2011 } 2012 else 2013 { 2014 ++s->currCPlusTxDesc; 2015 if (s->currCPlusTxDesc >= 64) 2016 s->currCPlusTxDesc = 0; 2017 } 2018 2019 /* transfer ownership to target */ 2020 txdw0 &= ~CP_TX_OWN; 2021 2022 /* reset error indicator bits */ 2023 txdw0 &= ~CP_TX_STATUS_UNF; 2024 txdw0 &= ~CP_TX_STATUS_TES; 2025 txdw0 &= ~CP_TX_STATUS_OWC; 2026 txdw0 &= ~CP_TX_STATUS_LNKF; 2027 txdw0 &= ~CP_TX_STATUS_EXC; 2028 2029 /* update ring data */ 2030 val = cpu_to_le32(txdw0); 2031 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 2032 2033 /* Now decide if descriptor being processed is holding the last segment of packet */ 2034 if (txdw0 & CP_TX_LS) 2035 { 2036 uint8_t dot1q_buffer_space[VLAN_HLEN]; 2037 uint16_t *dot1q_buffer; 2038 2039 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n", 2040 descriptor); 2041 2042 /* can transfer fully assembled packet */ 2043 2044 uint8_t *saved_buffer = s->cplus_txbuffer; 2045 int saved_size = s->cplus_txbuffer_offset; 2046 int saved_buffer_len = s->cplus_txbuffer_len; 2047 2048 /* create vlan tag */ 2049 if (txdw1 & CP_TX_TAGC) { 2050 /* the vlan tag is in BE byte order in the descriptor 2051 * BE + le_to_cpu() + ~swap()~ = cpu */ 2052 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", 2053 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); 2054 2055 dot1q_buffer = (uint16_t *) dot1q_buffer_space; 2056 dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN); 2057 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */ 2058 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK); 2059 } else { 2060 dot1q_buffer = NULL; 2061 } 2062 2063 /* reset the card space to protect from recursive call */ 2064 s->cplus_txbuffer = NULL; 2065 s->cplus_txbuffer_offset = 0; 2066 s->cplus_txbuffer_len = 0; 2067 2068 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) 2069 { 2070 DPRINTF("+++ C+ mode offloaded task checksum\n"); 2071 2072 /* Large enough for Ethernet and IP headers? */ 2073 if (saved_size < ETH_HLEN + sizeof(struct ip_header)) { 2074 goto skip_offload; 2075 } 2076 2077 /* ip packet header */ 2078 struct ip_header *ip = NULL; 2079 int hlen = 0; 2080 uint8_t ip_protocol = 0; 2081 uint16_t ip_data_len = 0; 2082 2083 uint8_t *eth_payload_data = NULL; 2084 size_t eth_payload_len = 0; 2085 2086 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); 2087 if (proto != ETH_P_IP) 2088 { 2089 goto skip_offload; 2090 } 2091 2092 DPRINTF("+++ C+ mode has IP packet\n"); 2093 2094 /* Note on memory alignment: eth_payload_data is 16-bit aligned 2095 * since saved_buffer is allocated with g_malloc() and ETH_HLEN is 2096 * even. 32-bit accesses must use ldl/stl wrappers to avoid 2097 * unaligned accesses. 2098 */ 2099 eth_payload_data = saved_buffer + ETH_HLEN; 2100 eth_payload_len = saved_size - ETH_HLEN; 2101 2102 ip = (struct ip_header*)eth_payload_data; 2103 2104 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) { 2105 DPRINTF("+++ C+ mode packet has bad IP version %d " 2106 "expected %d\n", IP_HEADER_VERSION(ip), 2107 IP_HEADER_VERSION_4); 2108 goto skip_offload; 2109 } 2110 2111 hlen = IP_HDR_GET_LEN(ip); 2112 if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) { 2113 goto skip_offload; 2114 } 2115 2116 ip_protocol = ip->ip_p; 2117 2118 ip_data_len = be16_to_cpu(ip->ip_len); 2119 if (ip_data_len < hlen || ip_data_len > eth_payload_len) { 2120 goto skip_offload; 2121 } 2122 ip_data_len -= hlen; 2123 2124 if (txdw0 & CP_TX_IPCS) 2125 { 2126 DPRINTF("+++ C+ mode need IP checksum\n"); 2127 2128 ip->ip_sum = 0; 2129 ip->ip_sum = ip_checksum(ip, hlen); 2130 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n", 2131 hlen, ip->ip_sum); 2132 } 2133 2134 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) 2135 { 2136 /* Large enough for the TCP header? */ 2137 if (ip_data_len < sizeof(tcp_header)) { 2138 goto skip_offload; 2139 } 2140 2141 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; 2142 2143 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d " 2144 "frame data %d specified MSS=%d\n", ETH_MTU, 2145 ip_data_len, saved_size - ETH_HLEN, large_send_mss); 2146 2147 int tcp_send_offset = 0; 2148 int send_count = 0; 2149 2150 /* maximum IP header length is 60 bytes */ 2151 uint8_t saved_ip_header[60]; 2152 2153 /* save IP header template; data area is used in tcp checksum calculation */ 2154 memcpy(saved_ip_header, eth_payload_data, hlen); 2155 2156 /* a placeholder for checksum calculation routine in tcp case */ 2157 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2158 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2159 2160 /* pointer to TCP header */ 2161 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); 2162 2163 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr); 2164 2165 /* Invalid TCP data offset? */ 2166 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) { 2167 goto skip_offload; 2168 } 2169 2170 /* ETH_MTU = ip header len + tcp header len + payload */ 2171 int tcp_data_len = ip_data_len - tcp_hlen; 2172 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen; 2173 2174 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP " 2175 "data len %d TCP chunk size %d\n", ip_data_len, 2176 tcp_hlen, tcp_data_len, tcp_chunk_size); 2177 2178 /* note the cycle below overwrites IP header data, 2179 but restores it from saved_ip_header before sending packet */ 2180 2181 int is_last_frame = 0; 2182 2183 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) 2184 { 2185 uint16_t chunk_size = tcp_chunk_size; 2186 2187 /* check if this is the last frame */ 2188 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len) 2189 { 2190 is_last_frame = 1; 2191 chunk_size = tcp_data_len - tcp_send_offset; 2192 } 2193 2194 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n", 2195 ldl_be_p(&p_tcp_hdr->th_seq)); 2196 2197 /* add 4 TCP pseudoheader fields */ 2198 /* copy IP source and destination fields */ 2199 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2200 2201 DPRINTF("+++ C+ mode TSO calculating TCP checksum for " 2202 "packet with %d bytes data\n", tcp_hlen + 2203 chunk_size); 2204 2205 if (tcp_send_offset) 2206 { 2207 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); 2208 } 2209 2210 /* keep PUSH and FIN flags only for the last frame */ 2211 if (!is_last_frame) 2212 { 2213 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN); 2214 } 2215 2216 /* recalculate TCP checksum */ 2217 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2218 p_tcpip_hdr->zeros = 0; 2219 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2220 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); 2221 2222 p_tcp_hdr->th_sum = 0; 2223 2224 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); 2225 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n", 2226 tcp_checksum); 2227 2228 p_tcp_hdr->th_sum = tcp_checksum; 2229 2230 /* restore IP header */ 2231 memcpy(eth_payload_data, saved_ip_header, hlen); 2232 2233 /* set IP data length and recalculate IP checksum */ 2234 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); 2235 2236 /* increment IP id for subsequent frames */ 2237 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); 2238 2239 ip->ip_sum = 0; 2240 ip->ip_sum = ip_checksum(eth_payload_data, hlen); 2241 DPRINTF("+++ C+ mode TSO IP header len=%d " 2242 "checksum=%04x\n", hlen, ip->ip_sum); 2243 2244 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size; 2245 DPRINTF("+++ C+ mode TSO transferring packet size " 2246 "%d\n", tso_send_size); 2247 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 2248 0, (uint8_t *) dot1q_buffer); 2249 2250 /* add transferred count to TCP sequence number */ 2251 stl_be_p(&p_tcp_hdr->th_seq, 2252 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq)); 2253 ++send_count; 2254 } 2255 2256 /* Stop sending this frame */ 2257 saved_size = 0; 2258 } 2259 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) 2260 { 2261 DPRINTF("+++ C+ mode need TCP or UDP checksum\n"); 2262 2263 /* maximum IP header length is 60 bytes */ 2264 uint8_t saved_ip_header[60]; 2265 memcpy(saved_ip_header, eth_payload_data, hlen); 2266 2267 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2268 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2269 2270 /* add 4 TCP pseudoheader fields */ 2271 /* copy IP source and destination fields */ 2272 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2273 2274 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) 2275 { 2276 DPRINTF("+++ C+ mode calculating TCP checksum for " 2277 "packet with %d bytes data\n", ip_data_len); 2278 2279 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2280 p_tcpip_hdr->zeros = 0; 2281 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2282 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2283 2284 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12); 2285 2286 p_tcp_hdr->th_sum = 0; 2287 2288 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2289 DPRINTF("+++ C+ mode TCP checksum %04x\n", 2290 tcp_checksum); 2291 2292 p_tcp_hdr->th_sum = tcp_checksum; 2293 } 2294 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) 2295 { 2296 DPRINTF("+++ C+ mode calculating UDP checksum for " 2297 "packet with %d bytes data\n", ip_data_len); 2298 2299 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; 2300 p_udpip_hdr->zeros = 0; 2301 p_udpip_hdr->ip_proto = IP_PROTO_UDP; 2302 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2303 2304 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12); 2305 2306 p_udp_hdr->uh_sum = 0; 2307 2308 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2309 DPRINTF("+++ C+ mode UDP checksum %04x\n", 2310 udp_checksum); 2311 2312 p_udp_hdr->uh_sum = udp_checksum; 2313 } 2314 2315 /* restore IP header */ 2316 memcpy(eth_payload_data, saved_ip_header, hlen); 2317 } 2318 } 2319 2320 skip_offload: 2321 /* update tally counter */ 2322 ++s->tally_counters.TxOk; 2323 2324 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size); 2325 2326 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1, 2327 (uint8_t *) dot1q_buffer); 2328 2329 /* restore card space if there was no recursion and reset offset */ 2330 if (!s->cplus_txbuffer) 2331 { 2332 s->cplus_txbuffer = saved_buffer; 2333 s->cplus_txbuffer_len = saved_buffer_len; 2334 s->cplus_txbuffer_offset = 0; 2335 } 2336 else 2337 { 2338 g_free(saved_buffer); 2339 } 2340 } 2341 else 2342 { 2343 DPRINTF("+++ C+ mode transmission continue to next descriptor\n"); 2344 } 2345 2346 return 1; 2347 } 2348 2349 static void rtl8139_cplus_transmit(RTL8139State *s) 2350 { 2351 int txcount = 0; 2352 2353 while (txcount < 64 && rtl8139_cplus_transmit_one(s)) 2354 { 2355 ++txcount; 2356 } 2357 2358 /* Mark transfer completed */ 2359 if (!txcount) 2360 { 2361 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n", 2362 s->currCPlusTxDesc); 2363 } 2364 else 2365 { 2366 /* update interrupt status */ 2367 s->IntrStatus |= TxOK; 2368 rtl8139_update_irq(s); 2369 } 2370 } 2371 2372 static void rtl8139_transmit(RTL8139State *s) 2373 { 2374 int descriptor = s->currTxDesc, txcount = 0; 2375 2376 /*while*/ 2377 if (rtl8139_transmit_one(s, descriptor)) 2378 { 2379 ++s->currTxDesc; 2380 s->currTxDesc %= 4; 2381 ++txcount; 2382 } 2383 2384 /* Mark transfer completed */ 2385 if (!txcount) 2386 { 2387 DPRINTF("transmitter queue stalled, current TxDesc = %d\n", 2388 s->currTxDesc); 2389 } 2390 } 2391 2392 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) 2393 { 2394 2395 int descriptor = txRegOffset/4; 2396 2397 /* handle C+ transmit mode register configuration */ 2398 2399 if (s->cplus_enabled) 2400 { 2401 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x " 2402 "descriptor=%d\n", txRegOffset, val, descriptor); 2403 2404 /* handle Dump Tally Counters command */ 2405 s->TxStatus[descriptor] = val; 2406 2407 if (descriptor == 0 && (val & 0x8)) 2408 { 2409 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); 2410 2411 /* dump tally counters to specified memory location */ 2412 RTL8139TallyCounters_dma_write(s, tc_addr); 2413 2414 /* mark dump completed */ 2415 s->TxStatus[0] &= ~0x8; 2416 } 2417 2418 return; 2419 } 2420 2421 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", 2422 txRegOffset, val, descriptor); 2423 2424 /* mask only reserved bits */ 2425 val &= ~0xff00c000; /* these bits are reset on write */ 2426 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); 2427 2428 s->TxStatus[descriptor] = val; 2429 2430 /* attempt to start transmission */ 2431 rtl8139_transmit(s); 2432 } 2433 2434 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[], 2435 uint32_t base, uint8_t addr, 2436 int size) 2437 { 2438 uint32_t reg = (addr - base) / 4; 2439 uint32_t offset = addr & 0x3; 2440 uint32_t ret = 0; 2441 2442 if (addr & (size - 1)) { 2443 DPRINTF("not implemented read for TxStatus/TxAddr " 2444 "addr=0x%x size=0x%x\n", addr, size); 2445 return ret; 2446 } 2447 2448 switch (size) { 2449 case 1: /* fall through */ 2450 case 2: /* fall through */ 2451 case 4: 2452 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1); 2453 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n", 2454 reg, addr, size, ret); 2455 break; 2456 default: 2457 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size); 2458 break; 2459 } 2460 2461 return ret; 2462 } 2463 2464 static uint16_t rtl8139_TSAD_read(RTL8139State *s) 2465 { 2466 uint16_t ret = 0; 2467 2468 /* Simulate TSAD, it is read only anyway */ 2469 2470 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) 2471 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) 2472 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) 2473 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) 2474 2475 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) 2476 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) 2477 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) 2478 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) 2479 2480 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) 2481 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) 2482 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) 2483 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) 2484 2485 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) 2486 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) 2487 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) 2488 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; 2489 2490 2491 DPRINTF("TSAD read val=0x%04x\n", ret); 2492 2493 return ret; 2494 } 2495 2496 static uint16_t rtl8139_CSCR_read(RTL8139State *s) 2497 { 2498 uint16_t ret = s->CSCR; 2499 2500 DPRINTF("CSCR read val=0x%04x\n", ret); 2501 2502 return ret; 2503 } 2504 2505 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) 2506 { 2507 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val); 2508 2509 s->TxAddr[txAddrOffset/4] = val; 2510 } 2511 2512 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) 2513 { 2514 uint32_t ret = s->TxAddr[txAddrOffset/4]; 2515 2516 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret); 2517 2518 return ret; 2519 } 2520 2521 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) 2522 { 2523 DPRINTF("RxBufPtr write val=0x%04x\n", val); 2524 2525 /* this value is off by 16 */ 2526 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); 2527 2528 /* more buffer space may be available so try to receive */ 2529 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 2530 2531 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", 2532 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 2533 } 2534 2535 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s) 2536 { 2537 /* this value is off by 16 */ 2538 uint32_t ret = s->RxBufPtr - 0x10; 2539 2540 DPRINTF("RxBufPtr read val=0x%04x\n", ret); 2541 2542 return ret; 2543 } 2544 2545 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s) 2546 { 2547 /* this value is NOT off by 16 */ 2548 uint32_t ret = s->RxBufAddr; 2549 2550 DPRINTF("RxBufAddr read val=0x%04x\n", ret); 2551 2552 return ret; 2553 } 2554 2555 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) 2556 { 2557 DPRINTF("RxBuf write val=0x%08x\n", val); 2558 2559 s->RxBuf = val; 2560 2561 /* may need to reset rxring here */ 2562 } 2563 2564 static uint32_t rtl8139_RxBuf_read(RTL8139State *s) 2565 { 2566 uint32_t ret = s->RxBuf; 2567 2568 DPRINTF("RxBuf read val=0x%08x\n", ret); 2569 2570 return ret; 2571 } 2572 2573 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) 2574 { 2575 DPRINTF("IntrMask write(w) val=0x%04x\n", val); 2576 2577 /* mask unwritable bits */ 2578 val = SET_MASKED(val, 0x1e00, s->IntrMask); 2579 2580 s->IntrMask = val; 2581 2582 rtl8139_update_irq(s); 2583 2584 } 2585 2586 static uint32_t rtl8139_IntrMask_read(RTL8139State *s) 2587 { 2588 uint32_t ret = s->IntrMask; 2589 2590 DPRINTF("IntrMask read(w) val=0x%04x\n", ret); 2591 2592 return ret; 2593 } 2594 2595 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) 2596 { 2597 DPRINTF("IntrStatus write(w) val=0x%04x\n", val); 2598 2599 #if 0 2600 2601 /* writing to ISR has no effect */ 2602 2603 return; 2604 2605 #else 2606 uint16_t newStatus = s->IntrStatus & ~val; 2607 2608 /* mask unwritable bits */ 2609 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); 2610 2611 /* writing 1 to interrupt status register bit clears it */ 2612 s->IntrStatus = 0; 2613 rtl8139_update_irq(s); 2614 2615 s->IntrStatus = newStatus; 2616 rtl8139_set_next_tctr_time(s); 2617 rtl8139_update_irq(s); 2618 2619 #endif 2620 } 2621 2622 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) 2623 { 2624 uint32_t ret = s->IntrStatus; 2625 2626 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret); 2627 2628 #if 0 2629 2630 /* reading ISR clears all interrupts */ 2631 s->IntrStatus = 0; 2632 2633 rtl8139_update_irq(s); 2634 2635 #endif 2636 2637 return ret; 2638 } 2639 2640 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) 2641 { 2642 DPRINTF("MultiIntr write(w) val=0x%04x\n", val); 2643 2644 /* mask unwritable bits */ 2645 val = SET_MASKED(val, 0xf000, s->MultiIntr); 2646 2647 s->MultiIntr = val; 2648 } 2649 2650 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s) 2651 { 2652 uint32_t ret = s->MultiIntr; 2653 2654 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret); 2655 2656 return ret; 2657 } 2658 2659 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) 2660 { 2661 RTL8139State *s = opaque; 2662 2663 switch (addr) 2664 { 2665 case MAC0 ... MAC0+4: 2666 s->phys[addr - MAC0] = val; 2667 break; 2668 case MAC0+5: 2669 s->phys[addr - MAC0] = val; 2670 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 2671 break; 2672 case MAC0+6 ... MAC0+7: 2673 /* reserved */ 2674 break; 2675 case MAR0 ... MAR0+7: 2676 s->mult[addr - MAR0] = val; 2677 break; 2678 case ChipCmd: 2679 rtl8139_ChipCmd_write(s, val); 2680 break; 2681 case Cfg9346: 2682 rtl8139_Cfg9346_write(s, val); 2683 break; 2684 case TxConfig: /* windows driver sometimes writes using byte-lenth call */ 2685 rtl8139_TxConfig_writeb(s, val); 2686 break; 2687 case Config0: 2688 rtl8139_Config0_write(s, val); 2689 break; 2690 case Config1: 2691 rtl8139_Config1_write(s, val); 2692 break; 2693 case Config3: 2694 rtl8139_Config3_write(s, val); 2695 break; 2696 case Config4: 2697 rtl8139_Config4_write(s, val); 2698 break; 2699 case Config5: 2700 rtl8139_Config5_write(s, val); 2701 break; 2702 case MediaStatus: 2703 /* ignore */ 2704 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n", 2705 val); 2706 break; 2707 2708 case HltClk: 2709 DPRINTF("HltClk write val=0x%08x\n", val); 2710 if (val == 'R') 2711 { 2712 s->clock_enabled = 1; 2713 } 2714 else if (val == 'H') 2715 { 2716 s->clock_enabled = 0; 2717 } 2718 break; 2719 2720 case TxThresh: 2721 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val); 2722 s->TxThresh = val; 2723 break; 2724 2725 case TxPoll: 2726 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val); 2727 if (val & (1 << 7)) 2728 { 2729 DPRINTF("C+ TxPoll high priority transmission (not " 2730 "implemented)\n"); 2731 //rtl8139_cplus_transmit(s); 2732 } 2733 if (val & (1 << 6)) 2734 { 2735 DPRINTF("C+ TxPoll normal priority transmission\n"); 2736 rtl8139_cplus_transmit(s); 2737 } 2738 2739 break; 2740 2741 default: 2742 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr, 2743 val); 2744 break; 2745 } 2746 } 2747 2748 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) 2749 { 2750 RTL8139State *s = opaque; 2751 2752 switch (addr) 2753 { 2754 case IntrMask: 2755 rtl8139_IntrMask_write(s, val); 2756 break; 2757 2758 case IntrStatus: 2759 rtl8139_IntrStatus_write(s, val); 2760 break; 2761 2762 case MultiIntr: 2763 rtl8139_MultiIntr_write(s, val); 2764 break; 2765 2766 case RxBufPtr: 2767 rtl8139_RxBufPtr_write(s, val); 2768 break; 2769 2770 case BasicModeCtrl: 2771 rtl8139_BasicModeCtrl_write(s, val); 2772 break; 2773 case BasicModeStatus: 2774 rtl8139_BasicModeStatus_write(s, val); 2775 break; 2776 case NWayAdvert: 2777 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val); 2778 s->NWayAdvert = val; 2779 break; 2780 case NWayLPAR: 2781 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val); 2782 break; 2783 case NWayExpansion: 2784 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val); 2785 s->NWayExpansion = val; 2786 break; 2787 2788 case CpCmd: 2789 rtl8139_CpCmd_write(s, val); 2790 break; 2791 2792 case IntrMitigate: 2793 rtl8139_IntrMitigate_write(s, val); 2794 break; 2795 2796 default: 2797 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n", 2798 addr, val); 2799 2800 rtl8139_io_writeb(opaque, addr, val & 0xff); 2801 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2802 break; 2803 } 2804 } 2805 2806 static void rtl8139_set_next_tctr_time(RTL8139State *s) 2807 { 2808 const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32; 2809 2810 DPRINTF("entered rtl8139_set_next_tctr_time\n"); 2811 2812 /* This function is called at least once per period, so it is a good 2813 * place to update the timer base. 2814 * 2815 * After one iteration of this loop the value in the Timer register does 2816 * not change, but the device model is counting up by 2^32 ticks (approx. 2817 * 130 seconds). 2818 */ 2819 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2820 s->TCTR_base += ns_per_period; 2821 } 2822 2823 if (!s->TimerInt) { 2824 timer_del(s->timer); 2825 } else { 2826 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD; 2827 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2828 delta += ns_per_period; 2829 } 2830 timer_mod(s->timer, s->TCTR_base + delta); 2831 } 2832 } 2833 2834 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) 2835 { 2836 RTL8139State *s = opaque; 2837 2838 switch (addr) 2839 { 2840 case RxMissed: 2841 DPRINTF("RxMissed clearing on write\n"); 2842 s->RxMissed = 0; 2843 break; 2844 2845 case TxConfig: 2846 rtl8139_TxConfig_write(s, val); 2847 break; 2848 2849 case RxConfig: 2850 rtl8139_RxConfig_write(s, val); 2851 break; 2852 2853 case TxStatus0 ... TxStatus0+4*4-1: 2854 rtl8139_TxStatus_write(s, addr-TxStatus0, val); 2855 break; 2856 2857 case TxAddr0 ... TxAddr0+4*4-1: 2858 rtl8139_TxAddr_write(s, addr-TxAddr0, val); 2859 break; 2860 2861 case RxBuf: 2862 rtl8139_RxBuf_write(s, val); 2863 break; 2864 2865 case RxRingAddrLO: 2866 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val); 2867 s->RxRingAddrLO = val; 2868 break; 2869 2870 case RxRingAddrHI: 2871 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val); 2872 s->RxRingAddrHI = val; 2873 break; 2874 2875 case Timer: 2876 DPRINTF("TCTR Timer reset on write\n"); 2877 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2878 rtl8139_set_next_tctr_time(s); 2879 break; 2880 2881 case FlashReg: 2882 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val); 2883 if (s->TimerInt != val) { 2884 s->TimerInt = val; 2885 rtl8139_set_next_tctr_time(s); 2886 } 2887 break; 2888 2889 default: 2890 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n", 2891 addr, val); 2892 rtl8139_io_writeb(opaque, addr, val & 0xff); 2893 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2894 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); 2895 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); 2896 break; 2897 } 2898 } 2899 2900 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) 2901 { 2902 RTL8139State *s = opaque; 2903 int ret; 2904 2905 switch (addr) 2906 { 2907 case MAC0 ... MAC0+5: 2908 ret = s->phys[addr - MAC0]; 2909 break; 2910 case MAC0+6 ... MAC0+7: 2911 ret = 0; 2912 break; 2913 case MAR0 ... MAR0+7: 2914 ret = s->mult[addr - MAR0]; 2915 break; 2916 case TxStatus0 ... TxStatus0+4*4-1: 2917 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 2918 addr, 1); 2919 break; 2920 case ChipCmd: 2921 ret = rtl8139_ChipCmd_read(s); 2922 break; 2923 case Cfg9346: 2924 ret = rtl8139_Cfg9346_read(s); 2925 break; 2926 case Config0: 2927 ret = rtl8139_Config0_read(s); 2928 break; 2929 case Config1: 2930 ret = rtl8139_Config1_read(s); 2931 break; 2932 case Config3: 2933 ret = rtl8139_Config3_read(s); 2934 break; 2935 case Config4: 2936 ret = rtl8139_Config4_read(s); 2937 break; 2938 case Config5: 2939 ret = rtl8139_Config5_read(s); 2940 break; 2941 2942 case MediaStatus: 2943 /* The LinkDown bit of MediaStatus is inverse with link status */ 2944 ret = 0xd0 | (~s->BasicModeStatus & 0x04); 2945 DPRINTF("MediaStatus read 0x%x\n", ret); 2946 break; 2947 2948 case HltClk: 2949 ret = s->clock_enabled; 2950 DPRINTF("HltClk read 0x%x\n", ret); 2951 break; 2952 2953 case PCIRevisionID: 2954 ret = RTL8139_PCI_REVID; 2955 DPRINTF("PCI Revision ID read 0x%x\n", ret); 2956 break; 2957 2958 case TxThresh: 2959 ret = s->TxThresh; 2960 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret); 2961 break; 2962 2963 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ 2964 ret = s->TxConfig >> 24; 2965 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret); 2966 break; 2967 2968 default: 2969 DPRINTF("not implemented read(b) addr=0x%x\n", addr); 2970 ret = 0; 2971 break; 2972 } 2973 2974 return ret; 2975 } 2976 2977 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) 2978 { 2979 RTL8139State *s = opaque; 2980 uint32_t ret; 2981 2982 switch (addr) 2983 { 2984 case TxAddr0 ... TxAddr0+4*4-1: 2985 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2); 2986 break; 2987 case IntrMask: 2988 ret = rtl8139_IntrMask_read(s); 2989 break; 2990 2991 case IntrStatus: 2992 ret = rtl8139_IntrStatus_read(s); 2993 break; 2994 2995 case MultiIntr: 2996 ret = rtl8139_MultiIntr_read(s); 2997 break; 2998 2999 case RxBufPtr: 3000 ret = rtl8139_RxBufPtr_read(s); 3001 break; 3002 3003 case RxBufAddr: 3004 ret = rtl8139_RxBufAddr_read(s); 3005 break; 3006 3007 case BasicModeCtrl: 3008 ret = rtl8139_BasicModeCtrl_read(s); 3009 break; 3010 case BasicModeStatus: 3011 ret = rtl8139_BasicModeStatus_read(s); 3012 break; 3013 case NWayAdvert: 3014 ret = s->NWayAdvert; 3015 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret); 3016 break; 3017 case NWayLPAR: 3018 ret = s->NWayLPAR; 3019 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret); 3020 break; 3021 case NWayExpansion: 3022 ret = s->NWayExpansion; 3023 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret); 3024 break; 3025 3026 case CpCmd: 3027 ret = rtl8139_CpCmd_read(s); 3028 break; 3029 3030 case IntrMitigate: 3031 ret = rtl8139_IntrMitigate_read(s); 3032 break; 3033 3034 case TxSummary: 3035 ret = rtl8139_TSAD_read(s); 3036 break; 3037 3038 case CSCR: 3039 ret = rtl8139_CSCR_read(s); 3040 break; 3041 3042 default: 3043 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr); 3044 3045 ret = rtl8139_io_readb(opaque, addr); 3046 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3047 3048 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret); 3049 break; 3050 } 3051 3052 return ret; 3053 } 3054 3055 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) 3056 { 3057 RTL8139State *s = opaque; 3058 uint32_t ret; 3059 3060 switch (addr) 3061 { 3062 case RxMissed: 3063 ret = s->RxMissed; 3064 3065 DPRINTF("RxMissed read val=0x%08x\n", ret); 3066 break; 3067 3068 case TxConfig: 3069 ret = rtl8139_TxConfig_read(s); 3070 break; 3071 3072 case RxConfig: 3073 ret = rtl8139_RxConfig_read(s); 3074 break; 3075 3076 case TxStatus0 ... TxStatus0+4*4-1: 3077 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 3078 addr, 4); 3079 break; 3080 3081 case TxAddr0 ... TxAddr0+4*4-1: 3082 ret = rtl8139_TxAddr_read(s, addr-TxAddr0); 3083 break; 3084 3085 case RxBuf: 3086 ret = rtl8139_RxBuf_read(s); 3087 break; 3088 3089 case RxRingAddrLO: 3090 ret = s->RxRingAddrLO; 3091 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret); 3092 break; 3093 3094 case RxRingAddrHI: 3095 ret = s->RxRingAddrHI; 3096 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret); 3097 break; 3098 3099 case Timer: 3100 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) / 3101 PCI_PERIOD; 3102 DPRINTF("TCTR Timer read val=0x%08x\n", ret); 3103 break; 3104 3105 case FlashReg: 3106 ret = s->TimerInt; 3107 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret); 3108 break; 3109 3110 default: 3111 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr); 3112 3113 ret = rtl8139_io_readb(opaque, addr); 3114 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3115 ret |= rtl8139_io_readb(opaque, addr + 2) << 16; 3116 ret |= rtl8139_io_readb(opaque, addr + 3) << 24; 3117 3118 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret); 3119 break; 3120 } 3121 3122 return ret; 3123 } 3124 3125 /* */ 3126 3127 static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) 3128 { 3129 rtl8139_io_writeb(opaque, addr & 0xFF, val); 3130 } 3131 3132 static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val) 3133 { 3134 rtl8139_io_writew(opaque, addr & 0xFF, val); 3135 } 3136 3137 static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val) 3138 { 3139 rtl8139_io_writel(opaque, addr & 0xFF, val); 3140 } 3141 3142 static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr) 3143 { 3144 return rtl8139_io_readb(opaque, addr & 0xFF); 3145 } 3146 3147 static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr) 3148 { 3149 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF); 3150 return val; 3151 } 3152 3153 static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr) 3154 { 3155 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF); 3156 return val; 3157 } 3158 3159 static int rtl8139_post_load(void *opaque, int version_id) 3160 { 3161 RTL8139State* s = opaque; 3162 rtl8139_set_next_tctr_time(s); 3163 if (version_id < 4) { 3164 s->cplus_enabled = s->CpCmd != 0; 3165 } 3166 3167 /* nc.link_down can't be migrated, so infer link_down according 3168 * to link status bit in BasicModeStatus */ 3169 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0; 3170 3171 return 0; 3172 } 3173 3174 static bool rtl8139_hotplug_ready_needed(void *opaque) 3175 { 3176 return qdev_machine_modified(); 3177 } 3178 3179 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ 3180 .name = "rtl8139/hotplug_ready", 3181 .version_id = 1, 3182 .minimum_version_id = 1, 3183 .needed = rtl8139_hotplug_ready_needed, 3184 .fields = (VMStateField[]) { 3185 VMSTATE_END_OF_LIST() 3186 } 3187 }; 3188 3189 static void rtl8139_pre_save(void *opaque) 3190 { 3191 RTL8139State* s = opaque; 3192 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 3193 3194 /* for migration to older versions */ 3195 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD; 3196 s->rtl8139_mmio_io_addr_dummy = 0; 3197 } 3198 3199 static const VMStateDescription vmstate_rtl8139 = { 3200 .name = "rtl8139", 3201 .version_id = 5, 3202 .minimum_version_id = 3, 3203 .post_load = rtl8139_post_load, 3204 .pre_save = rtl8139_pre_save, 3205 .fields = (VMStateField[]) { 3206 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State), 3207 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6), 3208 VMSTATE_BUFFER(mult, RTL8139State), 3209 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4), 3210 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4), 3211 3212 VMSTATE_UINT32(RxBuf, RTL8139State), 3213 VMSTATE_UINT32(RxBufferSize, RTL8139State), 3214 VMSTATE_UINT32(RxBufPtr, RTL8139State), 3215 VMSTATE_UINT32(RxBufAddr, RTL8139State), 3216 3217 VMSTATE_UINT16(IntrStatus, RTL8139State), 3218 VMSTATE_UINT16(IntrMask, RTL8139State), 3219 3220 VMSTATE_UINT32(TxConfig, RTL8139State), 3221 VMSTATE_UINT32(RxConfig, RTL8139State), 3222 VMSTATE_UINT32(RxMissed, RTL8139State), 3223 VMSTATE_UINT16(CSCR, RTL8139State), 3224 3225 VMSTATE_UINT8(Cfg9346, RTL8139State), 3226 VMSTATE_UINT8(Config0, RTL8139State), 3227 VMSTATE_UINT8(Config1, RTL8139State), 3228 VMSTATE_UINT8(Config3, RTL8139State), 3229 VMSTATE_UINT8(Config4, RTL8139State), 3230 VMSTATE_UINT8(Config5, RTL8139State), 3231 3232 VMSTATE_UINT8(clock_enabled, RTL8139State), 3233 VMSTATE_UINT8(bChipCmdState, RTL8139State), 3234 3235 VMSTATE_UINT16(MultiIntr, RTL8139State), 3236 3237 VMSTATE_UINT16(BasicModeCtrl, RTL8139State), 3238 VMSTATE_UINT16(BasicModeStatus, RTL8139State), 3239 VMSTATE_UINT16(NWayAdvert, RTL8139State), 3240 VMSTATE_UINT16(NWayLPAR, RTL8139State), 3241 VMSTATE_UINT16(NWayExpansion, RTL8139State), 3242 3243 VMSTATE_UINT16(CpCmd, RTL8139State), 3244 VMSTATE_UINT8(TxThresh, RTL8139State), 3245 3246 VMSTATE_UNUSED(4), 3247 VMSTATE_MACADDR(conf.macaddr, RTL8139State), 3248 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), 3249 3250 VMSTATE_UINT32(currTxDesc, RTL8139State), 3251 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), 3252 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), 3253 VMSTATE_UINT32(RxRingAddrLO, RTL8139State), 3254 VMSTATE_UINT32(RxRingAddrHI, RTL8139State), 3255 3256 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), 3257 VMSTATE_INT32(eeprom.mode, RTL8139State), 3258 VMSTATE_UINT32(eeprom.tick, RTL8139State), 3259 VMSTATE_UINT8(eeprom.address, RTL8139State), 3260 VMSTATE_UINT16(eeprom.input, RTL8139State), 3261 VMSTATE_UINT16(eeprom.output, RTL8139State), 3262 3263 VMSTATE_UINT8(eeprom.eecs, RTL8139State), 3264 VMSTATE_UINT8(eeprom.eesk, RTL8139State), 3265 VMSTATE_UINT8(eeprom.eedi, RTL8139State), 3266 VMSTATE_UINT8(eeprom.eedo, RTL8139State), 3267 3268 VMSTATE_UINT32(TCTR, RTL8139State), 3269 VMSTATE_UINT32(TimerInt, RTL8139State), 3270 VMSTATE_INT64(TCTR_base, RTL8139State), 3271 3272 VMSTATE_UINT64(tally_counters.TxOk, RTL8139State), 3273 VMSTATE_UINT64(tally_counters.RxOk, RTL8139State), 3274 VMSTATE_UINT64(tally_counters.TxERR, RTL8139State), 3275 VMSTATE_UINT32(tally_counters.RxERR, RTL8139State), 3276 VMSTATE_UINT16(tally_counters.MissPkt, RTL8139State), 3277 VMSTATE_UINT16(tally_counters.FAE, RTL8139State), 3278 VMSTATE_UINT32(tally_counters.Tx1Col, RTL8139State), 3279 VMSTATE_UINT32(tally_counters.TxMCol, RTL8139State), 3280 VMSTATE_UINT64(tally_counters.RxOkPhy, RTL8139State), 3281 VMSTATE_UINT64(tally_counters.RxOkBrd, RTL8139State), 3282 VMSTATE_UINT32_V(tally_counters.RxOkMul, RTL8139State, 5), 3283 VMSTATE_UINT16(tally_counters.TxAbt, RTL8139State), 3284 VMSTATE_UINT16(tally_counters.TxUndrn, RTL8139State), 3285 3286 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4), 3287 VMSTATE_END_OF_LIST() 3288 }, 3289 .subsections = (const VMStateDescription*[]) { 3290 &vmstate_rtl8139_hotplug_ready, 3291 NULL 3292 } 3293 }; 3294 3295 /***********************************************************/ 3296 /* PCI RTL8139 definitions */ 3297 3298 static void rtl8139_ioport_write(void *opaque, hwaddr addr, 3299 uint64_t val, unsigned size) 3300 { 3301 switch (size) { 3302 case 1: 3303 rtl8139_io_writeb(opaque, addr, val); 3304 break; 3305 case 2: 3306 rtl8139_io_writew(opaque, addr, val); 3307 break; 3308 case 4: 3309 rtl8139_io_writel(opaque, addr, val); 3310 break; 3311 } 3312 } 3313 3314 static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr, 3315 unsigned size) 3316 { 3317 switch (size) { 3318 case 1: 3319 return rtl8139_io_readb(opaque, addr); 3320 case 2: 3321 return rtl8139_io_readw(opaque, addr); 3322 case 4: 3323 return rtl8139_io_readl(opaque, addr); 3324 } 3325 3326 return -1; 3327 } 3328 3329 static const MemoryRegionOps rtl8139_io_ops = { 3330 .read = rtl8139_ioport_read, 3331 .write = rtl8139_ioport_write, 3332 .impl = { 3333 .min_access_size = 1, 3334 .max_access_size = 4, 3335 }, 3336 .endianness = DEVICE_LITTLE_ENDIAN, 3337 }; 3338 3339 static const MemoryRegionOps rtl8139_mmio_ops = { 3340 .old_mmio = { 3341 .read = { 3342 rtl8139_mmio_readb, 3343 rtl8139_mmio_readw, 3344 rtl8139_mmio_readl, 3345 }, 3346 .write = { 3347 rtl8139_mmio_writeb, 3348 rtl8139_mmio_writew, 3349 rtl8139_mmio_writel, 3350 }, 3351 }, 3352 .endianness = DEVICE_LITTLE_ENDIAN, 3353 }; 3354 3355 static void rtl8139_timer(void *opaque) 3356 { 3357 RTL8139State *s = opaque; 3358 3359 if (!s->clock_enabled) 3360 { 3361 DPRINTF(">>> timer: clock is not running\n"); 3362 return; 3363 } 3364 3365 s->IntrStatus |= PCSTimeout; 3366 rtl8139_update_irq(s); 3367 rtl8139_set_next_tctr_time(s); 3368 } 3369 3370 static void pci_rtl8139_uninit(PCIDevice *dev) 3371 { 3372 RTL8139State *s = RTL8139(dev); 3373 3374 g_free(s->cplus_txbuffer); 3375 s->cplus_txbuffer = NULL; 3376 timer_del(s->timer); 3377 timer_free(s->timer); 3378 qemu_del_nic(s->nic); 3379 } 3380 3381 static void rtl8139_set_link_status(NetClientState *nc) 3382 { 3383 RTL8139State *s = qemu_get_nic_opaque(nc); 3384 3385 if (nc->link_down) { 3386 s->BasicModeStatus &= ~0x04; 3387 } else { 3388 s->BasicModeStatus |= 0x04; 3389 } 3390 3391 s->IntrStatus |= RxUnderrun; 3392 rtl8139_update_irq(s); 3393 } 3394 3395 static NetClientInfo net_rtl8139_info = { 3396 .type = NET_CLIENT_DRIVER_NIC, 3397 .size = sizeof(NICState), 3398 .can_receive = rtl8139_can_receive, 3399 .receive = rtl8139_receive, 3400 .link_status_changed = rtl8139_set_link_status, 3401 }; 3402 3403 static void pci_rtl8139_realize(PCIDevice *dev, Error **errp) 3404 { 3405 RTL8139State *s = RTL8139(dev); 3406 DeviceState *d = DEVICE(dev); 3407 uint8_t *pci_conf; 3408 3409 pci_conf = dev->config; 3410 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 3411 /* TODO: start of capability list, but no capability 3412 * list bit in status register, and offset 0xdc seems unused. */ 3413 pci_conf[PCI_CAPABILITY_LIST] = 0xdc; 3414 3415 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s, 3416 "rtl8139", 0x100); 3417 memory_region_init_io(&s->bar_mem, OBJECT(s), &rtl8139_mmio_ops, s, 3418 "rtl8139", 0x100); 3419 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io); 3420 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem); 3421 3422 qemu_macaddr_default_if_unset(&s->conf.macaddr); 3423 3424 /* prepare eeprom */ 3425 s->eeprom.contents[0] = 0x8129; 3426 #if 1 3427 /* PCI vendor and device ID should be mirrored here */ 3428 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK; 3429 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139; 3430 #endif 3431 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; 3432 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; 3433 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; 3434 3435 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, 3436 object_get_typename(OBJECT(dev)), d->id, s); 3437 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 3438 3439 s->cplus_txbuffer = NULL; 3440 s->cplus_txbuffer_len = 0; 3441 s->cplus_txbuffer_offset = 0; 3442 3443 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s); 3444 } 3445 3446 static void rtl8139_instance_init(Object *obj) 3447 { 3448 RTL8139State *s = RTL8139(obj); 3449 3450 device_add_bootindex_property(obj, &s->conf.bootindex, 3451 "bootindex", "/ethernet-phy@0", 3452 DEVICE(obj), NULL); 3453 } 3454 3455 static Property rtl8139_properties[] = { 3456 DEFINE_NIC_PROPERTIES(RTL8139State, conf), 3457 DEFINE_PROP_END_OF_LIST(), 3458 }; 3459 3460 static void rtl8139_class_init(ObjectClass *klass, void *data) 3461 { 3462 DeviceClass *dc = DEVICE_CLASS(klass); 3463 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3464 3465 k->realize = pci_rtl8139_realize; 3466 k->exit = pci_rtl8139_uninit; 3467 k->romfile = "efi-rtl8139.rom"; 3468 k->vendor_id = PCI_VENDOR_ID_REALTEK; 3469 k->device_id = PCI_DEVICE_ID_REALTEK_8139; 3470 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */ 3471 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 3472 dc->reset = rtl8139_reset; 3473 dc->vmsd = &vmstate_rtl8139; 3474 dc->props = rtl8139_properties; 3475 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 3476 } 3477 3478 static const TypeInfo rtl8139_info = { 3479 .name = TYPE_RTL8139, 3480 .parent = TYPE_PCI_DEVICE, 3481 .instance_size = sizeof(RTL8139State), 3482 .class_init = rtl8139_class_init, 3483 .instance_init = rtl8139_instance_init, 3484 }; 3485 3486 static void rtl8139_register_types(void) 3487 { 3488 type_register_static(&rtl8139_info); 3489 } 3490 3491 type_init(rtl8139_register_types) 3492