1 /* 2 * QEMU AMD PC-Net II (Am79C970A) PCI emulation 3 * 4 * Copyright (c) 2004 Antony T Curtis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* This software was written to be compatible with the specification: 26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet 27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/irq.h" 32 #include "hw/pci/pci.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "net/net.h" 36 #include "qemu/module.h" 37 #include "qemu/timer.h" 38 #include "sysemu/dma.h" 39 #include "sysemu/sysemu.h" 40 #include "trace.h" 41 42 #include "pcnet.h" 43 #include "qom/object.h" 44 45 //#define PCNET_DEBUG 46 //#define PCNET_DEBUG_IO 47 //#define PCNET_DEBUG_BCR 48 //#define PCNET_DEBUG_CSR 49 //#define PCNET_DEBUG_RMD 50 //#define PCNET_DEBUG_TMD 51 //#define PCNET_DEBUG_MATCH 52 53 #define TYPE_PCI_PCNET "pcnet" 54 55 typedef struct PCIPCNetState PCIPCNetState; 56 DECLARE_INSTANCE_CHECKER(PCIPCNetState, PCI_PCNET, 57 TYPE_PCI_PCNET) 58 59 struct PCIPCNetState { 60 /*< private >*/ 61 PCIDevice parent_obj; 62 /*< public >*/ 63 64 PCNetState state; 65 MemoryRegion io_bar; 66 }; 67 68 static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) 69 { 70 PCNetState *s = opaque; 71 72 trace_pcnet_aprom_writeb(opaque, addr, val); 73 if (BCR_APROMWE(s)) { 74 s->prom[addr & 15] = val; 75 } 76 } 77 78 static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr) 79 { 80 PCNetState *s = opaque; 81 uint32_t val = s->prom[addr & 15]; 82 83 trace_pcnet_aprom_readb(opaque, addr, val); 84 return val; 85 } 86 87 static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr, 88 unsigned size) 89 { 90 PCNetState *d = opaque; 91 92 trace_pcnet_ioport_read(opaque, addr, size); 93 if (addr < 0x10) { 94 if (!BCR_DWIO(d) && size == 1) { 95 return pcnet_aprom_readb(d, addr); 96 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 97 return pcnet_aprom_readb(d, addr) | 98 (pcnet_aprom_readb(d, addr + 1) << 8); 99 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 100 return pcnet_aprom_readb(d, addr) | 101 (pcnet_aprom_readb(d, addr + 1) << 8) | 102 (pcnet_aprom_readb(d, addr + 2) << 16) | 103 (pcnet_aprom_readb(d, addr + 3) << 24); 104 } 105 } else { 106 if (size == 2) { 107 return pcnet_ioport_readw(d, addr); 108 } else if (size == 4) { 109 return pcnet_ioport_readl(d, addr); 110 } 111 } 112 return ((uint64_t)1 << (size * 8)) - 1; 113 } 114 115 static void pcnet_ioport_write(void *opaque, hwaddr addr, 116 uint64_t data, unsigned size) 117 { 118 PCNetState *d = opaque; 119 120 trace_pcnet_ioport_write(opaque, addr, data, size); 121 if (addr < 0x10) { 122 if (!BCR_DWIO(d) && size == 1) { 123 pcnet_aprom_writeb(d, addr, data); 124 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 125 pcnet_aprom_writeb(d, addr, data & 0xff); 126 pcnet_aprom_writeb(d, addr + 1, data >> 8); 127 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 128 pcnet_aprom_writeb(d, addr, data & 0xff); 129 pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff); 130 pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff); 131 pcnet_aprom_writeb(d, addr + 3, data >> 24); 132 } 133 } else { 134 if (size == 2) { 135 pcnet_ioport_writew(d, addr, data); 136 } else if (size == 4) { 137 pcnet_ioport_writel(d, addr, data); 138 } 139 } 140 } 141 142 static const MemoryRegionOps pcnet_io_ops = { 143 .read = pcnet_ioport_read, 144 .write = pcnet_ioport_write, 145 .endianness = DEVICE_LITTLE_ENDIAN, 146 }; 147 148 static const VMStateDescription vmstate_pci_pcnet = { 149 .name = "pcnet", 150 .version_id = 3, 151 .minimum_version_id = 2, 152 .fields = (VMStateField[]) { 153 VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState), 154 VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState), 155 VMSTATE_END_OF_LIST() 156 } 157 }; 158 159 /* PCI interface */ 160 161 static const MemoryRegionOps pcnet_mmio_ops = { 162 .read = pcnet_ioport_read, 163 .write = pcnet_ioport_write, 164 .valid.min_access_size = 1, 165 .valid.max_access_size = 4, 166 .impl.min_access_size = 1, 167 .impl.max_access_size = 4, 168 .endianness = DEVICE_LITTLE_ENDIAN, 169 }; 170 171 static void pci_physical_memory_write(void *dma_opaque, hwaddr addr, 172 uint8_t *buf, int len, int do_bswap) 173 { 174 pci_dma_write(dma_opaque, addr, buf, len); 175 } 176 177 static void pci_physical_memory_read(void *dma_opaque, hwaddr addr, 178 uint8_t *buf, int len, int do_bswap) 179 { 180 pci_dma_read(dma_opaque, addr, buf, len); 181 } 182 183 static void pci_pcnet_uninit(PCIDevice *dev) 184 { 185 PCIPCNetState *d = PCI_PCNET(dev); 186 187 qemu_free_irq(d->state.irq); 188 timer_del(d->state.poll_timer); 189 timer_free(d->state.poll_timer); 190 qemu_del_nic(d->state.nic); 191 } 192 193 static NetClientInfo net_pci_pcnet_info = { 194 .type = NET_CLIENT_DRIVER_NIC, 195 .size = sizeof(NICState), 196 .receive = pcnet_receive, 197 .link_status_changed = pcnet_set_link_status, 198 }; 199 200 static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp) 201 { 202 PCIPCNetState *d = PCI_PCNET(pci_dev); 203 PCNetState *s = &d->state; 204 uint8_t *pci_conf; 205 206 #if 0 207 printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n", 208 sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD)); 209 #endif 210 211 pci_conf = pci_dev->config; 212 213 pci_set_word(pci_conf + PCI_STATUS, 214 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 215 216 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); 217 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); 218 219 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 220 pci_conf[PCI_MIN_GNT] = 0x06; 221 pci_conf[PCI_MAX_LAT] = 0xff; 222 223 /* Handler for memory-mapped I/O */ 224 memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s, 225 "pcnet-mmio", PCNET_PNPMMIO_SIZE); 226 227 memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io", 228 PCNET_IOPORT_SIZE); 229 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar); 230 231 pci_register_bar(pci_dev, 1, 0, &s->mmio); 232 233 s->irq = pci_allocate_irq(pci_dev); 234 s->phys_mem_read = pci_physical_memory_read; 235 s->phys_mem_write = pci_physical_memory_write; 236 s->dma_opaque = DEVICE(pci_dev); 237 238 pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info); 239 } 240 241 static void pci_reset(DeviceState *dev) 242 { 243 PCIPCNetState *d = PCI_PCNET(dev); 244 245 pcnet_h_reset(&d->state); 246 } 247 248 static void pcnet_instance_init(Object *obj) 249 { 250 PCIPCNetState *d = PCI_PCNET(obj); 251 PCNetState *s = &d->state; 252 253 device_add_bootindex_property(obj, &s->conf.bootindex, 254 "bootindex", "/ethernet-phy@0", 255 DEVICE(obj)); 256 } 257 258 static Property pcnet_properties[] = { 259 DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf), 260 DEFINE_PROP_END_OF_LIST(), 261 }; 262 263 static void pcnet_class_init(ObjectClass *klass, void *data) 264 { 265 DeviceClass *dc = DEVICE_CLASS(klass); 266 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 267 268 k->realize = pci_pcnet_realize; 269 k->exit = pci_pcnet_uninit; 270 k->romfile = "efi-pcnet.rom", 271 k->vendor_id = PCI_VENDOR_ID_AMD; 272 k->device_id = PCI_DEVICE_ID_AMD_LANCE; 273 k->revision = 0x10; 274 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 275 dc->reset = pci_reset; 276 dc->vmsd = &vmstate_pci_pcnet; 277 device_class_set_props(dc, pcnet_properties); 278 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 279 } 280 281 static const TypeInfo pcnet_info = { 282 .name = TYPE_PCI_PCNET, 283 .parent = TYPE_PCI_DEVICE, 284 .instance_size = sizeof(PCIPCNetState), 285 .class_init = pcnet_class_init, 286 .instance_init = pcnet_instance_init, 287 .interfaces = (InterfaceInfo[]) { 288 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 289 { }, 290 }, 291 }; 292 293 static void pci_pcnet_register_types(void) 294 { 295 type_register_static(&pcnet_info); 296 } 297 298 type_init(pci_pcnet_register_types) 299