1 /* 2 * QEMU AMD PC-Net II (Am79C970A) PCI emulation 3 * 4 * Copyright (c) 2004 Antony T Curtis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* This software was written to be compatible with the specification: 26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet 27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/pci/pci.h" 32 #include "net/net.h" 33 #include "hw/loader.h" 34 #include "qemu/timer.h" 35 #include "sysemu/dma.h" 36 #include "sysemu/sysemu.h" 37 #include "trace.h" 38 39 #include "pcnet.h" 40 41 //#define PCNET_DEBUG 42 //#define PCNET_DEBUG_IO 43 //#define PCNET_DEBUG_BCR 44 //#define PCNET_DEBUG_CSR 45 //#define PCNET_DEBUG_RMD 46 //#define PCNET_DEBUG_TMD 47 //#define PCNET_DEBUG_MATCH 48 49 #define TYPE_PCI_PCNET "pcnet" 50 51 #define PCI_PCNET(obj) \ 52 OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET) 53 54 typedef struct { 55 /*< private >*/ 56 PCIDevice parent_obj; 57 /*< public >*/ 58 59 PCNetState state; 60 MemoryRegion io_bar; 61 } PCIPCNetState; 62 63 static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) 64 { 65 PCNetState *s = opaque; 66 67 trace_pcnet_aprom_writeb(opaque, addr, val); 68 if (BCR_APROMWE(s)) { 69 s->prom[addr & 15] = val; 70 } 71 } 72 73 static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr) 74 { 75 PCNetState *s = opaque; 76 uint32_t val = s->prom[addr & 15]; 77 78 trace_pcnet_aprom_readb(opaque, addr, val); 79 return val; 80 } 81 82 static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr, 83 unsigned size) 84 { 85 PCNetState *d = opaque; 86 87 trace_pcnet_ioport_read(opaque, addr, size); 88 if (addr < 0x10) { 89 if (!BCR_DWIO(d) && size == 1) { 90 return pcnet_aprom_readb(d, addr); 91 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 92 return pcnet_aprom_readb(d, addr) | 93 (pcnet_aprom_readb(d, addr + 1) << 8); 94 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 95 return pcnet_aprom_readb(d, addr) | 96 (pcnet_aprom_readb(d, addr + 1) << 8) | 97 (pcnet_aprom_readb(d, addr + 2) << 16) | 98 (pcnet_aprom_readb(d, addr + 3) << 24); 99 } 100 } else { 101 if (size == 2) { 102 return pcnet_ioport_readw(d, addr); 103 } else if (size == 4) { 104 return pcnet_ioport_readl(d, addr); 105 } 106 } 107 return ((uint64_t)1 << (size * 8)) - 1; 108 } 109 110 static void pcnet_ioport_write(void *opaque, hwaddr addr, 111 uint64_t data, unsigned size) 112 { 113 PCNetState *d = opaque; 114 115 trace_pcnet_ioport_write(opaque, addr, data, size); 116 if (addr < 0x10) { 117 if (!BCR_DWIO(d) && size == 1) { 118 pcnet_aprom_writeb(d, addr, data); 119 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 120 pcnet_aprom_writeb(d, addr, data & 0xff); 121 pcnet_aprom_writeb(d, addr + 1, data >> 8); 122 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 123 pcnet_aprom_writeb(d, addr, data & 0xff); 124 pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff); 125 pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff); 126 pcnet_aprom_writeb(d, addr + 3, data >> 24); 127 } 128 } else { 129 if (size == 2) { 130 pcnet_ioport_writew(d, addr, data); 131 } else if (size == 4) { 132 pcnet_ioport_writel(d, addr, data); 133 } 134 } 135 } 136 137 static const MemoryRegionOps pcnet_io_ops = { 138 .read = pcnet_ioport_read, 139 .write = pcnet_ioport_write, 140 .endianness = DEVICE_LITTLE_ENDIAN, 141 }; 142 143 static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) 144 { 145 PCNetState *d = opaque; 146 147 trace_pcnet_mmio_writeb(opaque, addr, val); 148 if (!(addr & 0x10)) 149 pcnet_aprom_writeb(d, addr & 0x0f, val); 150 } 151 152 static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr) 153 { 154 PCNetState *d = opaque; 155 uint32_t val = -1; 156 157 if (!(addr & 0x10)) 158 val = pcnet_aprom_readb(d, addr & 0x0f); 159 trace_pcnet_mmio_readb(opaque, addr, val); 160 return val; 161 } 162 163 static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val) 164 { 165 PCNetState *d = opaque; 166 167 trace_pcnet_mmio_writew(opaque, addr, val); 168 if (addr & 0x10) 169 pcnet_ioport_writew(d, addr & 0x0f, val); 170 else { 171 addr &= 0x0f; 172 pcnet_aprom_writeb(d, addr, val & 0xff); 173 pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8); 174 } 175 } 176 177 static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr) 178 { 179 PCNetState *d = opaque; 180 uint32_t val = -1; 181 182 if (addr & 0x10) 183 val = pcnet_ioport_readw(d, addr & 0x0f); 184 else { 185 addr &= 0x0f; 186 val = pcnet_aprom_readb(d, addr+1); 187 val <<= 8; 188 val |= pcnet_aprom_readb(d, addr); 189 } 190 trace_pcnet_mmio_readw(opaque, addr, val); 191 return val; 192 } 193 194 static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val) 195 { 196 PCNetState *d = opaque; 197 198 trace_pcnet_mmio_writel(opaque, addr, val); 199 if (addr & 0x10) 200 pcnet_ioport_writel(d, addr & 0x0f, val); 201 else { 202 addr &= 0x0f; 203 pcnet_aprom_writeb(d, addr, val & 0xff); 204 pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8); 205 pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16); 206 pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24); 207 } 208 } 209 210 static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr) 211 { 212 PCNetState *d = opaque; 213 uint32_t val; 214 215 if (addr & 0x10) 216 val = pcnet_ioport_readl(d, addr & 0x0f); 217 else { 218 addr &= 0x0f; 219 val = pcnet_aprom_readb(d, addr+3); 220 val <<= 8; 221 val |= pcnet_aprom_readb(d, addr+2); 222 val <<= 8; 223 val |= pcnet_aprom_readb(d, addr+1); 224 val <<= 8; 225 val |= pcnet_aprom_readb(d, addr); 226 } 227 trace_pcnet_mmio_readl(opaque, addr, val); 228 return val; 229 } 230 231 static const VMStateDescription vmstate_pci_pcnet = { 232 .name = "pcnet", 233 .version_id = 3, 234 .minimum_version_id = 2, 235 .fields = (VMStateField[]) { 236 VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState), 237 VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState), 238 VMSTATE_END_OF_LIST() 239 } 240 }; 241 242 /* PCI interface */ 243 244 static const MemoryRegionOps pcnet_mmio_ops = { 245 .old_mmio = { 246 .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl }, 247 .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel }, 248 }, 249 .endianness = DEVICE_LITTLE_ENDIAN, 250 }; 251 252 static void pci_physical_memory_write(void *dma_opaque, hwaddr addr, 253 uint8_t *buf, int len, int do_bswap) 254 { 255 pci_dma_write(dma_opaque, addr, buf, len); 256 } 257 258 static void pci_physical_memory_read(void *dma_opaque, hwaddr addr, 259 uint8_t *buf, int len, int do_bswap) 260 { 261 pci_dma_read(dma_opaque, addr, buf, len); 262 } 263 264 static void pci_pcnet_uninit(PCIDevice *dev) 265 { 266 PCIPCNetState *d = PCI_PCNET(dev); 267 268 qemu_free_irq(d->state.irq); 269 timer_del(d->state.poll_timer); 270 timer_free(d->state.poll_timer); 271 qemu_del_nic(d->state.nic); 272 } 273 274 static NetClientInfo net_pci_pcnet_info = { 275 .type = NET_CLIENT_DRIVER_NIC, 276 .size = sizeof(NICState), 277 .receive = pcnet_receive, 278 .link_status_changed = pcnet_set_link_status, 279 }; 280 281 static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp) 282 { 283 PCIPCNetState *d = PCI_PCNET(pci_dev); 284 PCNetState *s = &d->state; 285 uint8_t *pci_conf; 286 287 #if 0 288 printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n", 289 sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD)); 290 #endif 291 292 pci_conf = pci_dev->config; 293 294 pci_set_word(pci_conf + PCI_STATUS, 295 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 296 297 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); 298 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); 299 300 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 301 pci_conf[PCI_MIN_GNT] = 0x06; 302 pci_conf[PCI_MAX_LAT] = 0xff; 303 304 /* Handler for memory-mapped I/O */ 305 memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s, 306 "pcnet-mmio", PCNET_PNPMMIO_SIZE); 307 308 memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io", 309 PCNET_IOPORT_SIZE); 310 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar); 311 312 pci_register_bar(pci_dev, 1, 0, &s->mmio); 313 314 s->irq = pci_allocate_irq(pci_dev); 315 s->phys_mem_read = pci_physical_memory_read; 316 s->phys_mem_write = pci_physical_memory_write; 317 s->dma_opaque = pci_dev; 318 319 pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info); 320 } 321 322 static void pci_reset(DeviceState *dev) 323 { 324 PCIPCNetState *d = PCI_PCNET(dev); 325 326 pcnet_h_reset(&d->state); 327 } 328 329 static void pcnet_instance_init(Object *obj) 330 { 331 PCIPCNetState *d = PCI_PCNET(obj); 332 PCNetState *s = &d->state; 333 334 device_add_bootindex_property(obj, &s->conf.bootindex, 335 "bootindex", "/ethernet-phy@0", 336 DEVICE(obj), NULL); 337 } 338 339 static Property pcnet_properties[] = { 340 DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf), 341 DEFINE_PROP_END_OF_LIST(), 342 }; 343 344 static void pcnet_class_init(ObjectClass *klass, void *data) 345 { 346 DeviceClass *dc = DEVICE_CLASS(klass); 347 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 348 349 k->realize = pci_pcnet_realize; 350 k->exit = pci_pcnet_uninit; 351 k->romfile = "efi-pcnet.rom", 352 k->vendor_id = PCI_VENDOR_ID_AMD; 353 k->device_id = PCI_DEVICE_ID_AMD_LANCE; 354 k->revision = 0x10; 355 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 356 dc->reset = pci_reset; 357 dc->vmsd = &vmstate_pci_pcnet; 358 dc->props = pcnet_properties; 359 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 360 } 361 362 static const TypeInfo pcnet_info = { 363 .name = TYPE_PCI_PCNET, 364 .parent = TYPE_PCI_DEVICE, 365 .instance_size = sizeof(PCIPCNetState), 366 .class_init = pcnet_class_init, 367 .instance_init = pcnet_instance_init, 368 }; 369 370 static void pci_pcnet_register_types(void) 371 { 372 type_register_static(&pcnet_info); 373 } 374 375 type_init(pci_pcnet_register_types) 376