xref: /openbmc/qemu/hw/net/pcnet-pci.c (revision 650d103d3ea959212f826acb9d3fe80cf30e347b)
1 /*
2  * QEMU AMD PC-Net II (Am79C970A) PCI emulation
3  *
4  * Copyright (c) 2004 Antony T Curtis
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 /* This software was written to be compatible with the specification:
26  * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
27  * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
28  */
29 
30 #include "qemu/osdep.h"
31 #include "hw/irq.h"
32 #include "hw/pci/pci.h"
33 #include "migration/vmstate.h"
34 #include "net/net.h"
35 #include "qemu/module.h"
36 #include "qemu/timer.h"
37 #include "sysemu/dma.h"
38 #include "sysemu/sysemu.h"
39 #include "trace.h"
40 
41 #include "pcnet.h"
42 
43 //#define PCNET_DEBUG
44 //#define PCNET_DEBUG_IO
45 //#define PCNET_DEBUG_BCR
46 //#define PCNET_DEBUG_CSR
47 //#define PCNET_DEBUG_RMD
48 //#define PCNET_DEBUG_TMD
49 //#define PCNET_DEBUG_MATCH
50 
51 #define TYPE_PCI_PCNET "pcnet"
52 
53 #define PCI_PCNET(obj) \
54      OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)
55 
56 typedef struct {
57     /*< private >*/
58     PCIDevice parent_obj;
59     /*< public >*/
60 
61     PCNetState state;
62     MemoryRegion io_bar;
63 } PCIPCNetState;
64 
65 static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
66 {
67     PCNetState *s = opaque;
68 
69     trace_pcnet_aprom_writeb(opaque, addr, val);
70     if (BCR_APROMWE(s)) {
71         s->prom[addr & 15] = val;
72     }
73 }
74 
75 static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
76 {
77     PCNetState *s = opaque;
78     uint32_t val = s->prom[addr & 15];
79 
80     trace_pcnet_aprom_readb(opaque, addr, val);
81     return val;
82 }
83 
84 static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
85                                   unsigned size)
86 {
87     PCNetState *d = opaque;
88 
89     trace_pcnet_ioport_read(opaque, addr, size);
90     if (addr < 0x10) {
91         if (!BCR_DWIO(d) && size == 1) {
92             return pcnet_aprom_readb(d, addr);
93         } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
94             return pcnet_aprom_readb(d, addr) |
95                    (pcnet_aprom_readb(d, addr + 1) << 8);
96         } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
97             return pcnet_aprom_readb(d, addr) |
98                    (pcnet_aprom_readb(d, addr + 1) << 8) |
99                    (pcnet_aprom_readb(d, addr + 2) << 16) |
100                    (pcnet_aprom_readb(d, addr + 3) << 24);
101         }
102     } else {
103         if (size == 2) {
104             return pcnet_ioport_readw(d, addr);
105         } else if (size == 4) {
106             return pcnet_ioport_readl(d, addr);
107         }
108     }
109     return ((uint64_t)1 << (size * 8)) - 1;
110 }
111 
112 static void pcnet_ioport_write(void *opaque, hwaddr addr,
113                                uint64_t data, unsigned size)
114 {
115     PCNetState *d = opaque;
116 
117     trace_pcnet_ioport_write(opaque, addr, data, size);
118     if (addr < 0x10) {
119         if (!BCR_DWIO(d) && size == 1) {
120             pcnet_aprom_writeb(d, addr, data);
121         } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
122             pcnet_aprom_writeb(d, addr, data & 0xff);
123             pcnet_aprom_writeb(d, addr + 1, data >> 8);
124         } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
125             pcnet_aprom_writeb(d, addr, data & 0xff);
126             pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
127             pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
128             pcnet_aprom_writeb(d, addr + 3, data >> 24);
129         }
130     } else {
131         if (size == 2) {
132             pcnet_ioport_writew(d, addr, data);
133         } else if (size == 4) {
134             pcnet_ioport_writel(d, addr, data);
135         }
136     }
137 }
138 
139 static const MemoryRegionOps pcnet_io_ops = {
140     .read = pcnet_ioport_read,
141     .write = pcnet_ioport_write,
142     .endianness = DEVICE_LITTLE_ENDIAN,
143 };
144 
145 static const VMStateDescription vmstate_pci_pcnet = {
146     .name = "pcnet",
147     .version_id = 3,
148     .minimum_version_id = 2,
149     .fields = (VMStateField[]) {
150         VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
151         VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
152         VMSTATE_END_OF_LIST()
153     }
154 };
155 
156 /* PCI interface */
157 
158 static const MemoryRegionOps pcnet_mmio_ops = {
159     .read = pcnet_ioport_read,
160     .write = pcnet_ioport_write,
161     .valid.min_access_size = 1,
162     .valid.max_access_size = 4,
163     .impl.min_access_size = 1,
164     .impl.max_access_size = 4,
165     .endianness = DEVICE_LITTLE_ENDIAN,
166 };
167 
168 static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
169                                       uint8_t *buf, int len, int do_bswap)
170 {
171     pci_dma_write(dma_opaque, addr, buf, len);
172 }
173 
174 static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
175                                      uint8_t *buf, int len, int do_bswap)
176 {
177     pci_dma_read(dma_opaque, addr, buf, len);
178 }
179 
180 static void pci_pcnet_uninit(PCIDevice *dev)
181 {
182     PCIPCNetState *d = PCI_PCNET(dev);
183 
184     qemu_free_irq(d->state.irq);
185     timer_del(d->state.poll_timer);
186     timer_free(d->state.poll_timer);
187     qemu_del_nic(d->state.nic);
188 }
189 
190 static NetClientInfo net_pci_pcnet_info = {
191     .type = NET_CLIENT_DRIVER_NIC,
192     .size = sizeof(NICState),
193     .receive = pcnet_receive,
194     .link_status_changed = pcnet_set_link_status,
195 };
196 
197 static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp)
198 {
199     PCIPCNetState *d = PCI_PCNET(pci_dev);
200     PCNetState *s = &d->state;
201     uint8_t *pci_conf;
202 
203 #if 0
204     printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
205         sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
206 #endif
207 
208     pci_conf = pci_dev->config;
209 
210     pci_set_word(pci_conf + PCI_STATUS,
211                  PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
212 
213     pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
214     pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
215 
216     pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
217     pci_conf[PCI_MIN_GNT] = 0x06;
218     pci_conf[PCI_MAX_LAT] = 0xff;
219 
220     /* Handler for memory-mapped I/O */
221     memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s,
222                           "pcnet-mmio", PCNET_PNPMMIO_SIZE);
223 
224     memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io",
225                           PCNET_IOPORT_SIZE);
226     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
227 
228     pci_register_bar(pci_dev, 1, 0, &s->mmio);
229 
230     s->irq = pci_allocate_irq(pci_dev);
231     s->phys_mem_read = pci_physical_memory_read;
232     s->phys_mem_write = pci_physical_memory_write;
233     s->dma_opaque = pci_dev;
234 
235     pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
236 }
237 
238 static void pci_reset(DeviceState *dev)
239 {
240     PCIPCNetState *d = PCI_PCNET(dev);
241 
242     pcnet_h_reset(&d->state);
243 }
244 
245 static void pcnet_instance_init(Object *obj)
246 {
247     PCIPCNetState *d = PCI_PCNET(obj);
248     PCNetState *s = &d->state;
249 
250     device_add_bootindex_property(obj, &s->conf.bootindex,
251                                   "bootindex", "/ethernet-phy@0",
252                                   DEVICE(obj), NULL);
253 }
254 
255 static Property pcnet_properties[] = {
256     DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
257     DEFINE_PROP_END_OF_LIST(),
258 };
259 
260 static void pcnet_class_init(ObjectClass *klass, void *data)
261 {
262     DeviceClass *dc = DEVICE_CLASS(klass);
263     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
264 
265     k->realize = pci_pcnet_realize;
266     k->exit = pci_pcnet_uninit;
267     k->romfile = "efi-pcnet.rom",
268     k->vendor_id = PCI_VENDOR_ID_AMD;
269     k->device_id = PCI_DEVICE_ID_AMD_LANCE;
270     k->revision = 0x10;
271     k->class_id = PCI_CLASS_NETWORK_ETHERNET;
272     dc->reset = pci_reset;
273     dc->vmsd = &vmstate_pci_pcnet;
274     dc->props = pcnet_properties;
275     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
276 }
277 
278 static const TypeInfo pcnet_info = {
279     .name          = TYPE_PCI_PCNET,
280     .parent        = TYPE_PCI_DEVICE,
281     .instance_size = sizeof(PCIPCNetState),
282     .class_init    = pcnet_class_init,
283     .instance_init = pcnet_instance_init,
284     .interfaces = (InterfaceInfo[]) {
285         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
286         { },
287     },
288 };
289 
290 static void pci_pcnet_register_types(void)
291 {
292     type_register_static(&pcnet_info);
293 }
294 
295 type_init(pci_pcnet_register_types)
296