1 /* 2 * QEMU AMD PC-Net II (Am79C970A) PCI emulation 3 * 4 * Copyright (c) 2004 Antony T Curtis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* This software was written to be compatible with the specification: 26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet 27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/pci/pci.h" 32 #include "net/net.h" 33 #include "qemu/timer.h" 34 #include "sysemu/dma.h" 35 #include "sysemu/sysemu.h" 36 #include "trace.h" 37 38 #include "pcnet.h" 39 40 //#define PCNET_DEBUG 41 //#define PCNET_DEBUG_IO 42 //#define PCNET_DEBUG_BCR 43 //#define PCNET_DEBUG_CSR 44 //#define PCNET_DEBUG_RMD 45 //#define PCNET_DEBUG_TMD 46 //#define PCNET_DEBUG_MATCH 47 48 #define TYPE_PCI_PCNET "pcnet" 49 50 #define PCI_PCNET(obj) \ 51 OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET) 52 53 typedef struct { 54 /*< private >*/ 55 PCIDevice parent_obj; 56 /*< public >*/ 57 58 PCNetState state; 59 MemoryRegion io_bar; 60 } PCIPCNetState; 61 62 static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) 63 { 64 PCNetState *s = opaque; 65 66 trace_pcnet_aprom_writeb(opaque, addr, val); 67 if (BCR_APROMWE(s)) { 68 s->prom[addr & 15] = val; 69 } 70 } 71 72 static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr) 73 { 74 PCNetState *s = opaque; 75 uint32_t val = s->prom[addr & 15]; 76 77 trace_pcnet_aprom_readb(opaque, addr, val); 78 return val; 79 } 80 81 static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr, 82 unsigned size) 83 { 84 PCNetState *d = opaque; 85 86 trace_pcnet_ioport_read(opaque, addr, size); 87 if (addr < 0x10) { 88 if (!BCR_DWIO(d) && size == 1) { 89 return pcnet_aprom_readb(d, addr); 90 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 91 return pcnet_aprom_readb(d, addr) | 92 (pcnet_aprom_readb(d, addr + 1) << 8); 93 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 94 return pcnet_aprom_readb(d, addr) | 95 (pcnet_aprom_readb(d, addr + 1) << 8) | 96 (pcnet_aprom_readb(d, addr + 2) << 16) | 97 (pcnet_aprom_readb(d, addr + 3) << 24); 98 } 99 } else { 100 if (size == 2) { 101 return pcnet_ioport_readw(d, addr); 102 } else if (size == 4) { 103 return pcnet_ioport_readl(d, addr); 104 } 105 } 106 return ((uint64_t)1 << (size * 8)) - 1; 107 } 108 109 static void pcnet_ioport_write(void *opaque, hwaddr addr, 110 uint64_t data, unsigned size) 111 { 112 PCNetState *d = opaque; 113 114 trace_pcnet_ioport_write(opaque, addr, data, size); 115 if (addr < 0x10) { 116 if (!BCR_DWIO(d) && size == 1) { 117 pcnet_aprom_writeb(d, addr, data); 118 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 119 pcnet_aprom_writeb(d, addr, data & 0xff); 120 pcnet_aprom_writeb(d, addr + 1, data >> 8); 121 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 122 pcnet_aprom_writeb(d, addr, data & 0xff); 123 pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff); 124 pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff); 125 pcnet_aprom_writeb(d, addr + 3, data >> 24); 126 } 127 } else { 128 if (size == 2) { 129 pcnet_ioport_writew(d, addr, data); 130 } else if (size == 4) { 131 pcnet_ioport_writel(d, addr, data); 132 } 133 } 134 } 135 136 static const MemoryRegionOps pcnet_io_ops = { 137 .read = pcnet_ioport_read, 138 .write = pcnet_ioport_write, 139 .endianness = DEVICE_LITTLE_ENDIAN, 140 }; 141 142 static const VMStateDescription vmstate_pci_pcnet = { 143 .name = "pcnet", 144 .version_id = 3, 145 .minimum_version_id = 2, 146 .fields = (VMStateField[]) { 147 VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState), 148 VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState), 149 VMSTATE_END_OF_LIST() 150 } 151 }; 152 153 /* PCI interface */ 154 155 static const MemoryRegionOps pcnet_mmio_ops = { 156 .read = pcnet_ioport_read, 157 .write = pcnet_ioport_write, 158 .valid.min_access_size = 1, 159 .valid.max_access_size = 4, 160 .impl.min_access_size = 1, 161 .impl.max_access_size = 4, 162 .endianness = DEVICE_LITTLE_ENDIAN, 163 }; 164 165 static void pci_physical_memory_write(void *dma_opaque, hwaddr addr, 166 uint8_t *buf, int len, int do_bswap) 167 { 168 pci_dma_write(dma_opaque, addr, buf, len); 169 } 170 171 static void pci_physical_memory_read(void *dma_opaque, hwaddr addr, 172 uint8_t *buf, int len, int do_bswap) 173 { 174 pci_dma_read(dma_opaque, addr, buf, len); 175 } 176 177 static void pci_pcnet_uninit(PCIDevice *dev) 178 { 179 PCIPCNetState *d = PCI_PCNET(dev); 180 181 qemu_free_irq(d->state.irq); 182 timer_del(d->state.poll_timer); 183 timer_free(d->state.poll_timer); 184 qemu_del_nic(d->state.nic); 185 } 186 187 static NetClientInfo net_pci_pcnet_info = { 188 .type = NET_CLIENT_DRIVER_NIC, 189 .size = sizeof(NICState), 190 .receive = pcnet_receive, 191 .link_status_changed = pcnet_set_link_status, 192 }; 193 194 static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp) 195 { 196 PCIPCNetState *d = PCI_PCNET(pci_dev); 197 PCNetState *s = &d->state; 198 uint8_t *pci_conf; 199 200 #if 0 201 printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n", 202 sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD)); 203 #endif 204 205 pci_conf = pci_dev->config; 206 207 pci_set_word(pci_conf + PCI_STATUS, 208 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 209 210 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); 211 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); 212 213 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 214 pci_conf[PCI_MIN_GNT] = 0x06; 215 pci_conf[PCI_MAX_LAT] = 0xff; 216 217 /* Handler for memory-mapped I/O */ 218 memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s, 219 "pcnet-mmio", PCNET_PNPMMIO_SIZE); 220 221 memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io", 222 PCNET_IOPORT_SIZE); 223 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar); 224 225 pci_register_bar(pci_dev, 1, 0, &s->mmio); 226 227 s->irq = pci_allocate_irq(pci_dev); 228 s->phys_mem_read = pci_physical_memory_read; 229 s->phys_mem_write = pci_physical_memory_write; 230 s->dma_opaque = pci_dev; 231 232 pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info); 233 } 234 235 static void pci_reset(DeviceState *dev) 236 { 237 PCIPCNetState *d = PCI_PCNET(dev); 238 239 pcnet_h_reset(&d->state); 240 } 241 242 static void pcnet_instance_init(Object *obj) 243 { 244 PCIPCNetState *d = PCI_PCNET(obj); 245 PCNetState *s = &d->state; 246 247 device_add_bootindex_property(obj, &s->conf.bootindex, 248 "bootindex", "/ethernet-phy@0", 249 DEVICE(obj), NULL); 250 } 251 252 static Property pcnet_properties[] = { 253 DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf), 254 DEFINE_PROP_END_OF_LIST(), 255 }; 256 257 static void pcnet_class_init(ObjectClass *klass, void *data) 258 { 259 DeviceClass *dc = DEVICE_CLASS(klass); 260 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 261 262 k->realize = pci_pcnet_realize; 263 k->exit = pci_pcnet_uninit; 264 k->romfile = "efi-pcnet.rom", 265 k->vendor_id = PCI_VENDOR_ID_AMD; 266 k->device_id = PCI_DEVICE_ID_AMD_LANCE; 267 k->revision = 0x10; 268 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 269 dc->reset = pci_reset; 270 dc->vmsd = &vmstate_pci_pcnet; 271 dc->props = pcnet_properties; 272 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 273 } 274 275 static const TypeInfo pcnet_info = { 276 .name = TYPE_PCI_PCNET, 277 .parent = TYPE_PCI_DEVICE, 278 .instance_size = sizeof(PCIPCNetState), 279 .class_init = pcnet_class_init, 280 .instance_init = pcnet_instance_init, 281 .interfaces = (InterfaceInfo[]) { 282 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 283 { }, 284 }, 285 }; 286 287 static void pci_pcnet_register_types(void) 288 { 289 type_register_static(&pcnet_info); 290 } 291 292 type_init(pci_pcnet_register_types) 293