1 /* 2 * OpenCores Ethernet MAC 10/100 + subset of 3 * National Semiconductors DP83848C 10/100 PHY 4 * 5 * http://opencores.org/svnget,ethmac?file=%2Ftrunk%2F%2Fdoc%2Feth_speci.pdf 6 * http://cache.national.com/ds/DP/DP83848C.pdf 7 * 8 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions are met: 13 * * Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * * Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * * Neither the name of the Open Source and Linux Lab nor the 19 * names of its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "qemu/osdep.h" 35 #include "hw/hw.h" 36 #include "hw/irq.h" 37 #include "hw/net/mii.h" 38 #include "hw/sysbus.h" 39 #include "net/net.h" 40 #include "qemu/module.h" 41 #include "net/eth.h" 42 #include "sysemu/sysemu.h" 43 #include "trace.h" 44 45 /* RECSMALL is not used because it breaks tap networking in linux: 46 * incoming ARP responses are too short 47 */ 48 #undef USE_RECSMALL 49 50 #define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN)) 51 #define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field)) 52 #define GET_REGFIELD(s, reg, field) \ 53 GET_FIELD((s)->regs[reg], reg ## _ ## field) 54 55 #define SET_FIELD(v, field, data) \ 56 ((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field)))) 57 #define SET_REGFIELD(s, reg, field, data) \ 58 SET_FIELD((s)->regs[reg], reg ## _ ## field, data) 59 60 /* PHY MII registers */ 61 enum { 62 MII_REG_MAX = 16, 63 }; 64 65 typedef struct Mii { 66 uint16_t regs[MII_REG_MAX]; 67 bool link_ok; 68 } Mii; 69 70 static void mii_set_link(Mii *s, bool link_ok) 71 { 72 if (link_ok) { 73 s->regs[MII_BMSR] |= MII_BMSR_LINK_ST; 74 s->regs[MII_ANLPAR] |= MII_ANLPAR_TXFD | MII_ANLPAR_TX | 75 MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD; 76 } else { 77 s->regs[MII_BMSR] &= ~MII_BMSR_LINK_ST; 78 s->regs[MII_ANLPAR] &= 0x01ff; 79 } 80 s->link_ok = link_ok; 81 } 82 83 static void mii_reset(Mii *s) 84 { 85 memset(s->regs, 0, sizeof(s->regs)); 86 s->regs[MII_BMCR] = MII_BMCR_AUTOEN; 87 s->regs[MII_BMSR] = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | 88 MII_BMSR_10T_FD | MII_BMSR_10T_HD | MII_BMSR_MFPS | 89 MII_BMSR_AN_COMP | MII_BMSR_AUTONEG; 90 s->regs[MII_PHYID1] = 0x2000; 91 s->regs[MII_PHYID2] = 0x5c90; 92 s->regs[MII_ANAR] = MII_ANAR_TXFD | MII_ANAR_TX | 93 MII_ANAR_10FD | MII_ANAR_10 | MII_ANAR_CSMACD; 94 mii_set_link(s, s->link_ok); 95 } 96 97 static void mii_ro(Mii *s, uint16_t v) 98 { 99 } 100 101 static void mii_write_bmcr(Mii *s, uint16_t v) 102 { 103 if (v & MII_BMCR_RESET) { 104 mii_reset(s); 105 } else { 106 s->regs[MII_BMCR] = v; 107 } 108 } 109 110 static void mii_write_host(Mii *s, unsigned idx, uint16_t v) 111 { 112 static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = { 113 [MII_BMCR] = mii_write_bmcr, 114 [MII_BMSR] = mii_ro, 115 [MII_PHYID1] = mii_ro, 116 [MII_PHYID2] = mii_ro, 117 }; 118 119 if (idx < MII_REG_MAX) { 120 trace_open_eth_mii_write(idx, v); 121 if (reg_write[idx]) { 122 reg_write[idx](s, v); 123 } else { 124 s->regs[idx] = v; 125 } 126 } 127 } 128 129 static uint16_t mii_read_host(Mii *s, unsigned idx) 130 { 131 trace_open_eth_mii_read(idx, s->regs[idx]); 132 return s->regs[idx]; 133 } 134 135 /* OpenCores Ethernet registers */ 136 enum { 137 MODER, 138 INT_SOURCE, 139 INT_MASK, 140 IPGT, 141 IPGR1, 142 IPGR2, 143 PACKETLEN, 144 COLLCONF, 145 TX_BD_NUM, 146 CTRLMODER, 147 MIIMODER, 148 MIICOMMAND, 149 MIIADDRESS, 150 MIITX_DATA, 151 MIIRX_DATA, 152 MIISTATUS, 153 MAC_ADDR0, 154 MAC_ADDR1, 155 HASH0, 156 HASH1, 157 TXCTRL, 158 REG_MAX, 159 }; 160 161 enum { 162 MODER_RECSMALL = 0x10000, 163 MODER_PAD = 0x8000, 164 MODER_HUGEN = 0x4000, 165 MODER_RST = 0x800, 166 MODER_LOOPBCK = 0x80, 167 MODER_PRO = 0x20, 168 MODER_IAM = 0x10, 169 MODER_BRO = 0x8, 170 MODER_TXEN = 0x2, 171 MODER_RXEN = 0x1, 172 }; 173 174 enum { 175 INT_SOURCE_BUSY = 0x10, 176 INT_SOURCE_RXB = 0x4, 177 INT_SOURCE_TXB = 0x1, 178 }; 179 180 enum { 181 PACKETLEN_MINFL = 0xffff0000, 182 PACKETLEN_MINFL_LBN = 16, 183 PACKETLEN_MAXFL = 0xffff, 184 PACKETLEN_MAXFL_LBN = 0, 185 }; 186 187 enum { 188 MIICOMMAND_WCTRLDATA = 0x4, 189 MIICOMMAND_RSTAT = 0x2, 190 MIICOMMAND_SCANSTAT = 0x1, 191 }; 192 193 enum { 194 MIIADDRESS_RGAD = 0x1f00, 195 MIIADDRESS_RGAD_LBN = 8, 196 MIIADDRESS_FIAD = 0x1f, 197 MIIADDRESS_FIAD_LBN = 0, 198 }; 199 200 enum { 201 MIITX_DATA_CTRLDATA = 0xffff, 202 MIITX_DATA_CTRLDATA_LBN = 0, 203 }; 204 205 enum { 206 MIIRX_DATA_PRSD = 0xffff, 207 MIIRX_DATA_PRSD_LBN = 0, 208 }; 209 210 enum { 211 MIISTATUS_LINKFAIL = 0x1, 212 MIISTATUS_LINKFAIL_LBN = 0, 213 }; 214 215 enum { 216 MAC_ADDR0_BYTE2 = 0xff000000, 217 MAC_ADDR0_BYTE2_LBN = 24, 218 MAC_ADDR0_BYTE3 = 0xff0000, 219 MAC_ADDR0_BYTE3_LBN = 16, 220 MAC_ADDR0_BYTE4 = 0xff00, 221 MAC_ADDR0_BYTE4_LBN = 8, 222 MAC_ADDR0_BYTE5 = 0xff, 223 MAC_ADDR0_BYTE5_LBN = 0, 224 }; 225 226 enum { 227 MAC_ADDR1_BYTE0 = 0xff00, 228 MAC_ADDR1_BYTE0_LBN = 8, 229 MAC_ADDR1_BYTE1 = 0xff, 230 MAC_ADDR1_BYTE1_LBN = 0, 231 }; 232 233 enum { 234 TXD_LEN = 0xffff0000, 235 TXD_LEN_LBN = 16, 236 TXD_RD = 0x8000, 237 TXD_IRQ = 0x4000, 238 TXD_WR = 0x2000, 239 TXD_PAD = 0x1000, 240 TXD_CRC = 0x800, 241 TXD_UR = 0x100, 242 TXD_RTRY = 0xf0, 243 TXD_RTRY_LBN = 4, 244 TXD_RL = 0x8, 245 TXD_LC = 0x4, 246 TXD_DF = 0x2, 247 TXD_CS = 0x1, 248 }; 249 250 enum { 251 RXD_LEN = 0xffff0000, 252 RXD_LEN_LBN = 16, 253 RXD_E = 0x8000, 254 RXD_IRQ = 0x4000, 255 RXD_WRAP = 0x2000, 256 RXD_CF = 0x100, 257 RXD_M = 0x80, 258 RXD_OR = 0x40, 259 RXD_IS = 0x20, 260 RXD_DN = 0x10, 261 RXD_TL = 0x8, 262 RXD_SF = 0x4, 263 RXD_CRC = 0x2, 264 RXD_LC = 0x1, 265 }; 266 267 typedef struct desc { 268 uint32_t len_flags; 269 uint32_t buf_ptr; 270 } desc; 271 272 #define DEFAULT_PHY 1 273 274 #define TYPE_OPEN_ETH "open_eth" 275 #define OPEN_ETH(obj) OBJECT_CHECK(OpenEthState, (obj), TYPE_OPEN_ETH) 276 277 typedef struct OpenEthState { 278 SysBusDevice parent_obj; 279 280 NICState *nic; 281 NICConf conf; 282 MemoryRegion reg_io; 283 MemoryRegion desc_io; 284 qemu_irq irq; 285 286 Mii mii; 287 uint32_t regs[REG_MAX]; 288 unsigned tx_desc; 289 unsigned rx_desc; 290 desc desc[128]; 291 } OpenEthState; 292 293 static desc *rx_desc(OpenEthState *s) 294 { 295 return s->desc + s->rx_desc; 296 } 297 298 static desc *tx_desc(OpenEthState *s) 299 { 300 return s->desc + s->tx_desc; 301 } 302 303 static void open_eth_update_irq(OpenEthState *s, 304 uint32_t old, uint32_t new) 305 { 306 if (!old != !new) { 307 trace_open_eth_update_irq(new); 308 qemu_set_irq(s->irq, new); 309 } 310 } 311 312 static void open_eth_int_source_write(OpenEthState *s, 313 uint32_t val) 314 { 315 uint32_t old_val = s->regs[INT_SOURCE]; 316 317 s->regs[INT_SOURCE] = val; 318 open_eth_update_irq(s, old_val & s->regs[INT_MASK], 319 s->regs[INT_SOURCE] & s->regs[INT_MASK]); 320 } 321 322 static void open_eth_set_link_status(NetClientState *nc) 323 { 324 OpenEthState *s = qemu_get_nic_opaque(nc); 325 326 if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) { 327 SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down); 328 } 329 mii_set_link(&s->mii, !nc->link_down); 330 } 331 332 static void open_eth_reset(void *opaque) 333 { 334 OpenEthState *s = opaque; 335 336 memset(s->regs, 0, sizeof(s->regs)); 337 s->regs[MODER] = 0xa000; 338 s->regs[IPGT] = 0x12; 339 s->regs[IPGR1] = 0xc; 340 s->regs[IPGR2] = 0x12; 341 s->regs[PACKETLEN] = 0x400600; 342 s->regs[COLLCONF] = 0xf003f; 343 s->regs[TX_BD_NUM] = 0x40; 344 s->regs[MIIMODER] = 0x64; 345 346 s->tx_desc = 0; 347 s->rx_desc = 0x40; 348 349 mii_reset(&s->mii); 350 open_eth_set_link_status(qemu_get_queue(s->nic)); 351 } 352 353 static int open_eth_can_receive(NetClientState *nc) 354 { 355 OpenEthState *s = qemu_get_nic_opaque(nc); 356 357 return GET_REGBIT(s, MODER, RXEN) && 358 (s->regs[TX_BD_NUM] < 0x80); 359 } 360 361 static ssize_t open_eth_receive(NetClientState *nc, 362 const uint8_t *buf, size_t size) 363 { 364 OpenEthState *s = qemu_get_nic_opaque(nc); 365 size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL); 366 size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL); 367 size_t fcsl = 4; 368 bool miss = true; 369 370 trace_open_eth_receive((unsigned)size); 371 372 if (size >= 6) { 373 static const uint8_t bcast_addr[] = { 374 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 375 }; 376 if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) { 377 miss = GET_REGBIT(s, MODER, BRO); 378 } else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) { 379 unsigned mcast_idx = net_crc32(buf, ETH_ALEN) >> 26; 380 miss = !(s->regs[HASH0 + mcast_idx / 32] & 381 (1 << (mcast_idx % 32))); 382 trace_open_eth_receive_mcast( 383 mcast_idx, s->regs[HASH0], s->regs[HASH1]); 384 } else { 385 miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] || 386 GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] || 387 GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] || 388 GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] || 389 GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] || 390 GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5]; 391 } 392 } 393 394 if (miss && !GET_REGBIT(s, MODER, PRO)) { 395 trace_open_eth_receive_reject(); 396 return size; 397 } 398 399 #ifdef USE_RECSMALL 400 if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) { 401 #else 402 { 403 #endif 404 static const uint8_t zero[64] = {0}; 405 desc *desc = rx_desc(s); 406 size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl; 407 408 if (!(desc->len_flags & RXD_E)) { 409 open_eth_int_source_write(s, 410 s->regs[INT_SOURCE] | INT_SOURCE_BUSY); 411 return size; 412 } 413 414 desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR | 415 RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC); 416 417 if (copy_size > size) { 418 copy_size = size; 419 } else { 420 fcsl = 0; 421 } 422 if (miss) { 423 desc->len_flags |= RXD_M; 424 } 425 if (GET_REGBIT(s, MODER, HUGEN) && size > maxfl) { 426 desc->len_flags |= RXD_TL; 427 } 428 #ifdef USE_RECSMALL 429 if (size < minfl) { 430 desc->len_flags |= RXD_SF; 431 } 432 #endif 433 434 cpu_physical_memory_write(desc->buf_ptr, buf, copy_size); 435 436 if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) { 437 if (minfl - copy_size > fcsl) { 438 fcsl = 0; 439 } else { 440 fcsl -= minfl - copy_size; 441 } 442 while (copy_size < minfl) { 443 size_t zero_sz = minfl - copy_size < sizeof(zero) ? 444 minfl - copy_size : sizeof(zero); 445 446 cpu_physical_memory_write(desc->buf_ptr + copy_size, 447 zero, zero_sz); 448 copy_size += zero_sz; 449 } 450 } 451 452 /* There's no FCS in the frames handed to us by the QEMU, zero fill it. 453 * Don't do it if the frame is cut at the MAXFL or padded with 4 or 454 * more bytes to the MINFL. 455 */ 456 cpu_physical_memory_write(desc->buf_ptr + copy_size, zero, fcsl); 457 copy_size += fcsl; 458 459 SET_FIELD(desc->len_flags, RXD_LEN, copy_size); 460 461 if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) { 462 s->rx_desc = s->regs[TX_BD_NUM]; 463 } else { 464 ++s->rx_desc; 465 } 466 desc->len_flags &= ~RXD_E; 467 468 trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags); 469 470 if (desc->len_flags & RXD_IRQ) { 471 open_eth_int_source_write(s, 472 s->regs[INT_SOURCE] | INT_SOURCE_RXB); 473 } 474 } 475 return size; 476 } 477 478 static NetClientInfo net_open_eth_info = { 479 .type = NET_CLIENT_DRIVER_NIC, 480 .size = sizeof(NICState), 481 .can_receive = open_eth_can_receive, 482 .receive = open_eth_receive, 483 .link_status_changed = open_eth_set_link_status, 484 }; 485 486 static void open_eth_start_xmit(OpenEthState *s, desc *tx) 487 { 488 uint8_t *buf = NULL; 489 uint8_t buffer[0x600]; 490 unsigned len = GET_FIELD(tx->len_flags, TXD_LEN); 491 unsigned tx_len = len; 492 493 if ((tx->len_flags & TXD_PAD) && 494 tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) { 495 tx_len = GET_REGFIELD(s, PACKETLEN, MINFL); 496 } 497 if (!GET_REGBIT(s, MODER, HUGEN) && 498 tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) { 499 tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL); 500 } 501 502 trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len); 503 504 if (tx_len > sizeof(buffer)) { 505 buf = g_new(uint8_t, tx_len); 506 } else { 507 buf = buffer; 508 } 509 if (len > tx_len) { 510 len = tx_len; 511 } 512 cpu_physical_memory_read(tx->buf_ptr, buf, len); 513 if (tx_len > len) { 514 memset(buf + len, 0, tx_len - len); 515 } 516 qemu_send_packet(qemu_get_queue(s->nic), buf, tx_len); 517 if (tx_len > sizeof(buffer)) { 518 g_free(buf); 519 } 520 521 if (tx->len_flags & TXD_WR) { 522 s->tx_desc = 0; 523 } else { 524 ++s->tx_desc; 525 if (s->tx_desc >= s->regs[TX_BD_NUM]) { 526 s->tx_desc = 0; 527 } 528 } 529 tx->len_flags &= ~(TXD_RD | TXD_UR | 530 TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS); 531 if (tx->len_flags & TXD_IRQ) { 532 open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB); 533 } 534 535 } 536 537 static void open_eth_check_start_xmit(OpenEthState *s) 538 { 539 desc *tx = tx_desc(s); 540 if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 && 541 (tx->len_flags & TXD_RD) && 542 GET_FIELD(tx->len_flags, TXD_LEN) > 4) { 543 open_eth_start_xmit(s, tx); 544 } 545 } 546 547 static uint64_t open_eth_reg_read(void *opaque, 548 hwaddr addr, unsigned int size) 549 { 550 static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = { 551 }; 552 OpenEthState *s = opaque; 553 unsigned idx = addr / 4; 554 uint64_t v = 0; 555 556 if (idx < REG_MAX) { 557 if (reg_read[idx]) { 558 v = reg_read[idx](s); 559 } else { 560 v = s->regs[idx]; 561 } 562 } 563 trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v); 564 return v; 565 } 566 567 static void open_eth_notify_can_receive(OpenEthState *s) 568 { 569 NetClientState *nc = qemu_get_queue(s->nic); 570 571 if (open_eth_can_receive(nc)) { 572 qemu_flush_queued_packets(nc); 573 } 574 } 575 576 static void open_eth_ro(OpenEthState *s, uint32_t val) 577 { 578 } 579 580 static void open_eth_moder_host_write(OpenEthState *s, uint32_t val) 581 { 582 uint32_t set = val & ~s->regs[MODER]; 583 584 if (set & MODER_RST) { 585 open_eth_reset(s); 586 } 587 588 s->regs[MODER] = val; 589 590 if (set & MODER_RXEN) { 591 s->rx_desc = s->regs[TX_BD_NUM]; 592 open_eth_notify_can_receive(s); 593 } 594 if (set & MODER_TXEN) { 595 s->tx_desc = 0; 596 open_eth_check_start_xmit(s); 597 } 598 } 599 600 static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val) 601 { 602 uint32_t old = s->regs[INT_SOURCE]; 603 604 s->regs[INT_SOURCE] &= ~val; 605 open_eth_update_irq(s, old & s->regs[INT_MASK], 606 s->regs[INT_SOURCE] & s->regs[INT_MASK]); 607 } 608 609 static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val) 610 { 611 uint32_t old = s->regs[INT_MASK]; 612 613 s->regs[INT_MASK] = val; 614 open_eth_update_irq(s, s->regs[INT_SOURCE] & old, 615 s->regs[INT_SOURCE] & s->regs[INT_MASK]); 616 } 617 618 static void open_eth_tx_bd_num_host_write(OpenEthState *s, uint32_t val) 619 { 620 if (val < 0x80) { 621 bool enable = s->regs[TX_BD_NUM] == 0x80; 622 623 s->regs[TX_BD_NUM] = val; 624 if (enable) { 625 open_eth_notify_can_receive(s); 626 } 627 } 628 } 629 630 static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val) 631 { 632 unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD); 633 unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD); 634 635 if (val & MIICOMMAND_WCTRLDATA) { 636 if (fiad == DEFAULT_PHY) { 637 mii_write_host(&s->mii, rgad, 638 GET_REGFIELD(s, MIITX_DATA, CTRLDATA)); 639 } 640 } 641 if (val & MIICOMMAND_RSTAT) { 642 if (fiad == DEFAULT_PHY) { 643 SET_REGFIELD(s, MIIRX_DATA, PRSD, 644 mii_read_host(&s->mii, rgad)); 645 } else { 646 s->regs[MIIRX_DATA] = 0xffff; 647 } 648 SET_REGFIELD(s, MIISTATUS, LINKFAIL, qemu_get_queue(s->nic)->link_down); 649 } 650 } 651 652 static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val) 653 { 654 SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val); 655 if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) { 656 mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD), 657 GET_REGFIELD(s, MIITX_DATA, CTRLDATA)); 658 } 659 } 660 661 static void open_eth_reg_write(void *opaque, 662 hwaddr addr, uint64_t val, unsigned int size) 663 { 664 static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = { 665 [MODER] = open_eth_moder_host_write, 666 [INT_SOURCE] = open_eth_int_source_host_write, 667 [INT_MASK] = open_eth_int_mask_host_write, 668 [TX_BD_NUM] = open_eth_tx_bd_num_host_write, 669 [MIICOMMAND] = open_eth_mii_command_host_write, 670 [MIITX_DATA] = open_eth_mii_tx_host_write, 671 [MIISTATUS] = open_eth_ro, 672 }; 673 OpenEthState *s = opaque; 674 unsigned idx = addr / 4; 675 676 if (idx < REG_MAX) { 677 trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val); 678 if (reg_write[idx]) { 679 reg_write[idx](s, val); 680 } else { 681 s->regs[idx] = val; 682 } 683 } 684 } 685 686 static uint64_t open_eth_desc_read(void *opaque, 687 hwaddr addr, unsigned int size) 688 { 689 OpenEthState *s = opaque; 690 uint64_t v = 0; 691 692 addr &= 0x3ff; 693 memcpy(&v, (uint8_t *)s->desc + addr, size); 694 trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v); 695 return v; 696 } 697 698 static void open_eth_desc_write(void *opaque, 699 hwaddr addr, uint64_t val, unsigned int size) 700 { 701 OpenEthState *s = opaque; 702 703 addr &= 0x3ff; 704 trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val); 705 memcpy((uint8_t *)s->desc + addr, &val, size); 706 open_eth_check_start_xmit(s); 707 } 708 709 710 static const MemoryRegionOps open_eth_reg_ops = { 711 .read = open_eth_reg_read, 712 .write = open_eth_reg_write, 713 }; 714 715 static const MemoryRegionOps open_eth_desc_ops = { 716 .read = open_eth_desc_read, 717 .write = open_eth_desc_write, 718 }; 719 720 static void sysbus_open_eth_realize(DeviceState *dev, Error **errp) 721 { 722 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 723 OpenEthState *s = OPEN_ETH(dev); 724 725 memory_region_init_io(&s->reg_io, OBJECT(dev), &open_eth_reg_ops, s, 726 "open_eth.regs", 0x54); 727 sysbus_init_mmio(sbd, &s->reg_io); 728 729 memory_region_init_io(&s->desc_io, OBJECT(dev), &open_eth_desc_ops, s, 730 "open_eth.desc", 0x400); 731 sysbus_init_mmio(sbd, &s->desc_io); 732 733 sysbus_init_irq(sbd, &s->irq); 734 735 s->nic = qemu_new_nic(&net_open_eth_info, &s->conf, 736 object_get_typename(OBJECT(s)), dev->id, s); 737 } 738 739 static void qdev_open_eth_reset(DeviceState *dev) 740 { 741 OpenEthState *d = OPEN_ETH(dev); 742 743 open_eth_reset(d); 744 } 745 746 static Property open_eth_properties[] = { 747 DEFINE_NIC_PROPERTIES(OpenEthState, conf), 748 DEFINE_PROP_END_OF_LIST(), 749 }; 750 751 static void open_eth_class_init(ObjectClass *klass, void *data) 752 { 753 DeviceClass *dc = DEVICE_CLASS(klass); 754 755 dc->realize = sysbus_open_eth_realize; 756 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 757 dc->desc = "Opencores 10/100 Mbit Ethernet"; 758 dc->reset = qdev_open_eth_reset; 759 dc->props = open_eth_properties; 760 } 761 762 static const TypeInfo open_eth_info = { 763 .name = TYPE_OPEN_ETH, 764 .parent = TYPE_SYS_BUS_DEVICE, 765 .instance_size = sizeof(OpenEthState), 766 .class_init = open_eth_class_init, 767 }; 768 769 static void open_eth_register_types(void) 770 { 771 type_register_static(&open_eth_info); 772 } 773 774 type_init(open_eth_register_types) 775