xref: /openbmc/qemu/hw/net/opencores_eth.c (revision 4a09d0bb)
1 /*
2  * OpenCores Ethernet MAC 10/100 + subset of
3  * National Semiconductors DP83848C 10/100 PHY
4  *
5  * http://opencores.org/svnget,ethmac?file=%2Ftrunk%2F%2Fdoc%2Feth_speci.pdf
6  * http://cache.national.com/ds/DP/DP83848C.pdf
7  *
8  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
9  * All rights reserved.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions are met:
13  *     * Redistributions of source code must retain the above copyright
14  *       notice, this list of conditions and the following disclaimer.
15  *     * Redistributions in binary form must reproduce the above copyright
16  *       notice, this list of conditions and the following disclaimer in the
17  *       documentation and/or other materials provided with the distribution.
18  *     * Neither the name of the Open Source and Linux Lab nor the
19  *       names of its contributors may be used to endorse or promote products
20  *       derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
26  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #include "qemu/osdep.h"
35 #include "hw/hw.h"
36 #include "hw/net/mii.h"
37 #include "hw/sysbus.h"
38 #include "net/net.h"
39 #include "sysemu/sysemu.h"
40 #include "trace.h"
41 
42 /* RECSMALL is not used because it breaks tap networking in linux:
43  * incoming ARP responses are too short
44  */
45 #undef USE_RECSMALL
46 
47 #define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN))
48 #define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field))
49 #define GET_REGFIELD(s, reg, field) \
50     GET_FIELD((s)->regs[reg], reg ## _ ## field)
51 
52 #define SET_FIELD(v, field, data) \
53     ((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field))))
54 #define SET_REGFIELD(s, reg, field, data) \
55     SET_FIELD((s)->regs[reg], reg ## _ ## field, data)
56 
57 /* PHY MII registers */
58 enum {
59     MII_REG_MAX = 16,
60 };
61 
62 typedef struct Mii {
63     uint16_t regs[MII_REG_MAX];
64     bool link_ok;
65 } Mii;
66 
67 static void mii_set_link(Mii *s, bool link_ok)
68 {
69     if (link_ok) {
70         s->regs[MII_BMSR] |= MII_BMSR_LINK_ST;
71         s->regs[MII_ANLPAR] |= MII_ANLPAR_TXFD | MII_ANLPAR_TX |
72             MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
73     } else {
74         s->regs[MII_BMSR] &= ~MII_BMSR_LINK_ST;
75         s->regs[MII_ANLPAR] &= 0x01ff;
76     }
77     s->link_ok = link_ok;
78 }
79 
80 static void mii_reset(Mii *s)
81 {
82     memset(s->regs, 0, sizeof(s->regs));
83     s->regs[MII_BMCR] = MII_BMCR_AUTOEN;
84     s->regs[MII_BMSR] = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD |
85         MII_BMSR_10T_FD | MII_BMSR_10T_HD | MII_BMSR_MFPS |
86         MII_BMSR_AN_COMP | MII_BMSR_AUTONEG;
87     s->regs[MII_PHYID1] = 0x2000;
88     s->regs[MII_PHYID2] = 0x5c90;
89     s->regs[MII_ANAR] = MII_ANAR_TXFD | MII_ANAR_TX |
90         MII_ANAR_10FD | MII_ANAR_10 | MII_ANAR_CSMACD;
91     mii_set_link(s, s->link_ok);
92 }
93 
94 static void mii_ro(Mii *s, uint16_t v)
95 {
96 }
97 
98 static void mii_write_bmcr(Mii *s, uint16_t v)
99 {
100     if (v & MII_BMCR_RESET) {
101         mii_reset(s);
102     } else {
103         s->regs[MII_BMCR] = v;
104     }
105 }
106 
107 static void mii_write_host(Mii *s, unsigned idx, uint16_t v)
108 {
109     static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = {
110         [MII_BMCR] = mii_write_bmcr,
111         [MII_BMSR] = mii_ro,
112         [MII_PHYID1] = mii_ro,
113         [MII_PHYID2] = mii_ro,
114     };
115 
116     if (idx < MII_REG_MAX) {
117         trace_open_eth_mii_write(idx, v);
118         if (reg_write[idx]) {
119             reg_write[idx](s, v);
120         } else {
121             s->regs[idx] = v;
122         }
123     }
124 }
125 
126 static uint16_t mii_read_host(Mii *s, unsigned idx)
127 {
128     trace_open_eth_mii_read(idx, s->regs[idx]);
129     return s->regs[idx];
130 }
131 
132 /* OpenCores Ethernet registers */
133 enum {
134     MODER,
135     INT_SOURCE,
136     INT_MASK,
137     IPGT,
138     IPGR1,
139     IPGR2,
140     PACKETLEN,
141     COLLCONF,
142     TX_BD_NUM,
143     CTRLMODER,
144     MIIMODER,
145     MIICOMMAND,
146     MIIADDRESS,
147     MIITX_DATA,
148     MIIRX_DATA,
149     MIISTATUS,
150     MAC_ADDR0,
151     MAC_ADDR1,
152     HASH0,
153     HASH1,
154     TXCTRL,
155     REG_MAX,
156 };
157 
158 enum {
159     MODER_RECSMALL = 0x10000,
160     MODER_PAD = 0x8000,
161     MODER_HUGEN = 0x4000,
162     MODER_RST = 0x800,
163     MODER_LOOPBCK = 0x80,
164     MODER_PRO = 0x20,
165     MODER_IAM = 0x10,
166     MODER_BRO = 0x8,
167     MODER_TXEN = 0x2,
168     MODER_RXEN = 0x1,
169 };
170 
171 enum {
172     INT_SOURCE_BUSY = 0x10,
173     INT_SOURCE_RXB = 0x4,
174     INT_SOURCE_TXB = 0x1,
175 };
176 
177 enum {
178     PACKETLEN_MINFL = 0xffff0000,
179     PACKETLEN_MINFL_LBN = 16,
180     PACKETLEN_MAXFL = 0xffff,
181     PACKETLEN_MAXFL_LBN = 0,
182 };
183 
184 enum {
185     MIICOMMAND_WCTRLDATA = 0x4,
186     MIICOMMAND_RSTAT = 0x2,
187     MIICOMMAND_SCANSTAT = 0x1,
188 };
189 
190 enum {
191     MIIADDRESS_RGAD = 0x1f00,
192     MIIADDRESS_RGAD_LBN = 8,
193     MIIADDRESS_FIAD = 0x1f,
194     MIIADDRESS_FIAD_LBN = 0,
195 };
196 
197 enum {
198     MIITX_DATA_CTRLDATA = 0xffff,
199     MIITX_DATA_CTRLDATA_LBN = 0,
200 };
201 
202 enum {
203     MIIRX_DATA_PRSD = 0xffff,
204     MIIRX_DATA_PRSD_LBN = 0,
205 };
206 
207 enum {
208     MIISTATUS_LINKFAIL = 0x1,
209     MIISTATUS_LINKFAIL_LBN = 0,
210 };
211 
212 enum {
213     MAC_ADDR0_BYTE2 = 0xff000000,
214     MAC_ADDR0_BYTE2_LBN = 24,
215     MAC_ADDR0_BYTE3 = 0xff0000,
216     MAC_ADDR0_BYTE3_LBN = 16,
217     MAC_ADDR0_BYTE4 = 0xff00,
218     MAC_ADDR0_BYTE4_LBN = 8,
219     MAC_ADDR0_BYTE5 = 0xff,
220     MAC_ADDR0_BYTE5_LBN = 0,
221 };
222 
223 enum {
224     MAC_ADDR1_BYTE0 = 0xff00,
225     MAC_ADDR1_BYTE0_LBN = 8,
226     MAC_ADDR1_BYTE1 = 0xff,
227     MAC_ADDR1_BYTE1_LBN = 0,
228 };
229 
230 enum {
231     TXD_LEN = 0xffff0000,
232     TXD_LEN_LBN = 16,
233     TXD_RD = 0x8000,
234     TXD_IRQ = 0x4000,
235     TXD_WR = 0x2000,
236     TXD_PAD = 0x1000,
237     TXD_CRC = 0x800,
238     TXD_UR = 0x100,
239     TXD_RTRY = 0xf0,
240     TXD_RTRY_LBN = 4,
241     TXD_RL = 0x8,
242     TXD_LC = 0x4,
243     TXD_DF = 0x2,
244     TXD_CS = 0x1,
245 };
246 
247 enum {
248     RXD_LEN = 0xffff0000,
249     RXD_LEN_LBN = 16,
250     RXD_E = 0x8000,
251     RXD_IRQ = 0x4000,
252     RXD_WRAP = 0x2000,
253     RXD_CF = 0x100,
254     RXD_M = 0x80,
255     RXD_OR = 0x40,
256     RXD_IS = 0x20,
257     RXD_DN = 0x10,
258     RXD_TL = 0x8,
259     RXD_SF = 0x4,
260     RXD_CRC = 0x2,
261     RXD_LC = 0x1,
262 };
263 
264 typedef struct desc {
265     uint32_t len_flags;
266     uint32_t buf_ptr;
267 } desc;
268 
269 #define DEFAULT_PHY 1
270 
271 #define TYPE_OPEN_ETH "open_eth"
272 #define OPEN_ETH(obj) OBJECT_CHECK(OpenEthState, (obj), TYPE_OPEN_ETH)
273 
274 typedef struct OpenEthState {
275     SysBusDevice parent_obj;
276 
277     NICState *nic;
278     NICConf conf;
279     MemoryRegion reg_io;
280     MemoryRegion desc_io;
281     qemu_irq irq;
282 
283     Mii mii;
284     uint32_t regs[REG_MAX];
285     unsigned tx_desc;
286     unsigned rx_desc;
287     desc desc[128];
288 } OpenEthState;
289 
290 static desc *rx_desc(OpenEthState *s)
291 {
292     return s->desc + s->rx_desc;
293 }
294 
295 static desc *tx_desc(OpenEthState *s)
296 {
297     return s->desc + s->tx_desc;
298 }
299 
300 static void open_eth_update_irq(OpenEthState *s,
301         uint32_t old, uint32_t new)
302 {
303     if (!old != !new) {
304         trace_open_eth_update_irq(new);
305         qemu_set_irq(s->irq, new);
306     }
307 }
308 
309 static void open_eth_int_source_write(OpenEthState *s,
310         uint32_t val)
311 {
312     uint32_t old_val = s->regs[INT_SOURCE];
313 
314     s->regs[INT_SOURCE] = val;
315     open_eth_update_irq(s, old_val & s->regs[INT_MASK],
316             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
317 }
318 
319 static void open_eth_set_link_status(NetClientState *nc)
320 {
321     OpenEthState *s = qemu_get_nic_opaque(nc);
322 
323     if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) {
324         SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down);
325     }
326     mii_set_link(&s->mii, !nc->link_down);
327 }
328 
329 static void open_eth_reset(void *opaque)
330 {
331     OpenEthState *s = opaque;
332 
333     memset(s->regs, 0, sizeof(s->regs));
334     s->regs[MODER] = 0xa000;
335     s->regs[IPGT] = 0x12;
336     s->regs[IPGR1] = 0xc;
337     s->regs[IPGR2] = 0x12;
338     s->regs[PACKETLEN] = 0x400600;
339     s->regs[COLLCONF] = 0xf003f;
340     s->regs[TX_BD_NUM] = 0x40;
341     s->regs[MIIMODER] = 0x64;
342 
343     s->tx_desc = 0;
344     s->rx_desc = 0x40;
345 
346     mii_reset(&s->mii);
347     open_eth_set_link_status(qemu_get_queue(s->nic));
348 }
349 
350 static int open_eth_can_receive(NetClientState *nc)
351 {
352     OpenEthState *s = qemu_get_nic_opaque(nc);
353 
354     return GET_REGBIT(s, MODER, RXEN) &&
355         (s->regs[TX_BD_NUM] < 0x80);
356 }
357 
358 static ssize_t open_eth_receive(NetClientState *nc,
359         const uint8_t *buf, size_t size)
360 {
361     OpenEthState *s = qemu_get_nic_opaque(nc);
362     size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL);
363     size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL);
364     size_t fcsl = 4;
365     bool miss = true;
366 
367     trace_open_eth_receive((unsigned)size);
368 
369     if (size >= 6) {
370         static const uint8_t bcast_addr[] = {
371             0xff, 0xff, 0xff, 0xff, 0xff, 0xff
372         };
373         if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) {
374             miss = GET_REGBIT(s, MODER, BRO);
375         } else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) {
376             unsigned mcast_idx = compute_mcast_idx(buf);
377             miss = !(s->regs[HASH0 + mcast_idx / 32] &
378                     (1 << (mcast_idx % 32)));
379             trace_open_eth_receive_mcast(
380                     mcast_idx, s->regs[HASH0], s->regs[HASH1]);
381         } else {
382             miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] ||
383                 GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] ||
384                 GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] ||
385                 GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] ||
386                 GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] ||
387                 GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5];
388         }
389     }
390 
391     if (miss && !GET_REGBIT(s, MODER, PRO)) {
392         trace_open_eth_receive_reject();
393         return size;
394     }
395 
396 #ifdef USE_RECSMALL
397     if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) {
398 #else
399     {
400 #endif
401         static const uint8_t zero[64] = {0};
402         desc *desc = rx_desc(s);
403         size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl;
404 
405         if (!(desc->len_flags & RXD_E)) {
406             open_eth_int_source_write(s,
407                     s->regs[INT_SOURCE] | INT_SOURCE_BUSY);
408             return size;
409         }
410 
411         desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR |
412                 RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC);
413 
414         if (copy_size > size) {
415             copy_size = size;
416         } else {
417             fcsl = 0;
418         }
419         if (miss) {
420             desc->len_flags |= RXD_M;
421         }
422         if (GET_REGBIT(s, MODER, HUGEN) && size > maxfl) {
423             desc->len_flags |= RXD_TL;
424         }
425 #ifdef USE_RECSMALL
426         if (size < minfl) {
427             desc->len_flags |= RXD_SF;
428         }
429 #endif
430 
431         cpu_physical_memory_write(desc->buf_ptr, buf, copy_size);
432 
433         if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) {
434             if (minfl - copy_size > fcsl) {
435                 fcsl = 0;
436             } else {
437                 fcsl -= minfl - copy_size;
438             }
439             while (copy_size < minfl) {
440                 size_t zero_sz = minfl - copy_size < sizeof(zero) ?
441                     minfl - copy_size : sizeof(zero);
442 
443                 cpu_physical_memory_write(desc->buf_ptr + copy_size,
444                         zero, zero_sz);
445                 copy_size += zero_sz;
446             }
447         }
448 
449         /* There's no FCS in the frames handed to us by the QEMU, zero fill it.
450          * Don't do it if the frame is cut at the MAXFL or padded with 4 or
451          * more bytes to the MINFL.
452          */
453         cpu_physical_memory_write(desc->buf_ptr + copy_size, zero, fcsl);
454         copy_size += fcsl;
455 
456         SET_FIELD(desc->len_flags, RXD_LEN, copy_size);
457 
458         if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) {
459             s->rx_desc = s->regs[TX_BD_NUM];
460         } else {
461             ++s->rx_desc;
462         }
463         desc->len_flags &= ~RXD_E;
464 
465         trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags);
466 
467         if (desc->len_flags & RXD_IRQ) {
468             open_eth_int_source_write(s,
469                     s->regs[INT_SOURCE] | INT_SOURCE_RXB);
470         }
471     }
472     return size;
473 }
474 
475 static NetClientInfo net_open_eth_info = {
476     .type = NET_CLIENT_DRIVER_NIC,
477     .size = sizeof(NICState),
478     .can_receive = open_eth_can_receive,
479     .receive = open_eth_receive,
480     .link_status_changed = open_eth_set_link_status,
481 };
482 
483 static void open_eth_start_xmit(OpenEthState *s, desc *tx)
484 {
485     uint8_t *buf = NULL;
486     uint8_t buffer[0x600];
487     unsigned len = GET_FIELD(tx->len_flags, TXD_LEN);
488     unsigned tx_len = len;
489 
490     if ((tx->len_flags & TXD_PAD) &&
491             tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) {
492         tx_len = GET_REGFIELD(s, PACKETLEN, MINFL);
493     }
494     if (!GET_REGBIT(s, MODER, HUGEN) &&
495             tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) {
496         tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL);
497     }
498 
499     trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len);
500 
501     if (tx_len > sizeof(buffer)) {
502         buf = g_new(uint8_t, tx_len);
503     } else {
504         buf = buffer;
505     }
506     if (len > tx_len) {
507         len = tx_len;
508     }
509     cpu_physical_memory_read(tx->buf_ptr, buf, len);
510     if (tx_len > len) {
511         memset(buf + len, 0, tx_len - len);
512     }
513     qemu_send_packet(qemu_get_queue(s->nic), buf, tx_len);
514     if (tx_len > sizeof(buffer)) {
515         g_free(buf);
516     }
517 
518     if (tx->len_flags & TXD_WR) {
519         s->tx_desc = 0;
520     } else {
521         ++s->tx_desc;
522         if (s->tx_desc >= s->regs[TX_BD_NUM]) {
523             s->tx_desc = 0;
524         }
525     }
526     tx->len_flags &= ~(TXD_RD | TXD_UR |
527             TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS);
528     if (tx->len_flags & TXD_IRQ) {
529         open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB);
530     }
531 
532 }
533 
534 static void open_eth_check_start_xmit(OpenEthState *s)
535 {
536     desc *tx = tx_desc(s);
537     if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 &&
538             (tx->len_flags & TXD_RD) &&
539             GET_FIELD(tx->len_flags, TXD_LEN) > 4) {
540         open_eth_start_xmit(s, tx);
541     }
542 }
543 
544 static uint64_t open_eth_reg_read(void *opaque,
545         hwaddr addr, unsigned int size)
546 {
547     static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
548     };
549     OpenEthState *s = opaque;
550     unsigned idx = addr / 4;
551     uint64_t v = 0;
552 
553     if (idx < REG_MAX) {
554         if (reg_read[idx]) {
555             v = reg_read[idx](s);
556         } else {
557             v = s->regs[idx];
558         }
559     }
560     trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v);
561     return v;
562 }
563 
564 static void open_eth_notify_can_receive(OpenEthState *s)
565 {
566     NetClientState *nc = qemu_get_queue(s->nic);
567 
568     if (open_eth_can_receive(nc)) {
569         qemu_flush_queued_packets(nc);
570     }
571 }
572 
573 static void open_eth_ro(OpenEthState *s, uint32_t val)
574 {
575 }
576 
577 static void open_eth_moder_host_write(OpenEthState *s, uint32_t val)
578 {
579     uint32_t set = val & ~s->regs[MODER];
580 
581     if (set & MODER_RST) {
582         open_eth_reset(s);
583     }
584 
585     s->regs[MODER] = val;
586 
587     if (set & MODER_RXEN) {
588         s->rx_desc = s->regs[TX_BD_NUM];
589         open_eth_notify_can_receive(s);
590     }
591     if (set & MODER_TXEN) {
592         s->tx_desc = 0;
593         open_eth_check_start_xmit(s);
594     }
595 }
596 
597 static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val)
598 {
599     uint32_t old = s->regs[INT_SOURCE];
600 
601     s->regs[INT_SOURCE] &= ~val;
602     open_eth_update_irq(s, old & s->regs[INT_MASK],
603             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
604 }
605 
606 static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val)
607 {
608     uint32_t old = s->regs[INT_MASK];
609 
610     s->regs[INT_MASK] = val;
611     open_eth_update_irq(s, s->regs[INT_SOURCE] & old,
612             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
613 }
614 
615 static void open_eth_tx_bd_num_host_write(OpenEthState *s, uint32_t val)
616 {
617     if (val < 0x80) {
618         bool enable = s->regs[TX_BD_NUM] == 0x80;
619 
620         s->regs[TX_BD_NUM] = val;
621         if (enable) {
622             open_eth_notify_can_receive(s);
623         }
624     }
625 }
626 
627 static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val)
628 {
629     unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD);
630     unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD);
631 
632     if (val & MIICOMMAND_WCTRLDATA) {
633         if (fiad == DEFAULT_PHY) {
634             mii_write_host(&s->mii, rgad,
635                     GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
636         }
637     }
638     if (val & MIICOMMAND_RSTAT) {
639         if (fiad == DEFAULT_PHY) {
640             SET_REGFIELD(s, MIIRX_DATA, PRSD,
641                     mii_read_host(&s->mii, rgad));
642         } else {
643             s->regs[MIIRX_DATA] = 0xffff;
644         }
645         SET_REGFIELD(s, MIISTATUS, LINKFAIL, qemu_get_queue(s->nic)->link_down);
646     }
647 }
648 
649 static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val)
650 {
651     SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val);
652     if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) {
653         mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD),
654                 GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
655     }
656 }
657 
658 static void open_eth_reg_write(void *opaque,
659         hwaddr addr, uint64_t val, unsigned int size)
660 {
661     static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
662         [MODER] = open_eth_moder_host_write,
663         [INT_SOURCE] = open_eth_int_source_host_write,
664         [INT_MASK] = open_eth_int_mask_host_write,
665         [TX_BD_NUM] = open_eth_tx_bd_num_host_write,
666         [MIICOMMAND] = open_eth_mii_command_host_write,
667         [MIITX_DATA] = open_eth_mii_tx_host_write,
668         [MIISTATUS] = open_eth_ro,
669     };
670     OpenEthState *s = opaque;
671     unsigned idx = addr / 4;
672 
673     if (idx < REG_MAX) {
674         trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val);
675         if (reg_write[idx]) {
676             reg_write[idx](s, val);
677         } else {
678             s->regs[idx] = val;
679         }
680     }
681 }
682 
683 static uint64_t open_eth_desc_read(void *opaque,
684         hwaddr addr, unsigned int size)
685 {
686     OpenEthState *s = opaque;
687     uint64_t v = 0;
688 
689     addr &= 0x3ff;
690     memcpy(&v, (uint8_t *)s->desc + addr, size);
691     trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v);
692     return v;
693 }
694 
695 static void open_eth_desc_write(void *opaque,
696         hwaddr addr, uint64_t val, unsigned int size)
697 {
698     OpenEthState *s = opaque;
699 
700     addr &= 0x3ff;
701     trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val);
702     memcpy((uint8_t *)s->desc + addr, &val, size);
703     open_eth_check_start_xmit(s);
704 }
705 
706 
707 static const MemoryRegionOps open_eth_reg_ops = {
708     .read = open_eth_reg_read,
709     .write = open_eth_reg_write,
710 };
711 
712 static const MemoryRegionOps open_eth_desc_ops = {
713     .read = open_eth_desc_read,
714     .write = open_eth_desc_write,
715 };
716 
717 static int sysbus_open_eth_init(SysBusDevice *sbd)
718 {
719     DeviceState *dev = DEVICE(sbd);
720     OpenEthState *s = OPEN_ETH(dev);
721 
722     memory_region_init_io(&s->reg_io, OBJECT(dev), &open_eth_reg_ops, s,
723             "open_eth.regs", 0x54);
724     sysbus_init_mmio(sbd, &s->reg_io);
725 
726     memory_region_init_io(&s->desc_io, OBJECT(dev), &open_eth_desc_ops, s,
727             "open_eth.desc", 0x400);
728     sysbus_init_mmio(sbd, &s->desc_io);
729 
730     sysbus_init_irq(sbd, &s->irq);
731 
732     s->nic = qemu_new_nic(&net_open_eth_info, &s->conf,
733                           object_get_typename(OBJECT(s)), dev->id, s);
734     return 0;
735 }
736 
737 static void qdev_open_eth_reset(DeviceState *dev)
738 {
739     OpenEthState *d = OPEN_ETH(dev);
740 
741     open_eth_reset(d);
742 }
743 
744 static Property open_eth_properties[] = {
745     DEFINE_NIC_PROPERTIES(OpenEthState, conf),
746     DEFINE_PROP_END_OF_LIST(),
747 };
748 
749 static void open_eth_class_init(ObjectClass *klass, void *data)
750 {
751     DeviceClass *dc = DEVICE_CLASS(klass);
752     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
753 
754     k->init = sysbus_open_eth_init;
755     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
756     dc->desc = "Opencores 10/100 Mbit Ethernet";
757     dc->reset = qdev_open_eth_reset;
758     dc->props = open_eth_properties;
759 }
760 
761 static const TypeInfo open_eth_info = {
762     .name          = TYPE_OPEN_ETH,
763     .parent        = TYPE_SYS_BUS_DEVICE,
764     .instance_size = sizeof(OpenEthState),
765     .class_init    = open_eth_class_init,
766 };
767 
768 static void open_eth_register_types(void)
769 {
770     type_register_static(&open_eth_info);
771 }
772 
773 type_init(open_eth_register_types)
774