1 /* 2 * Nuvoton NPCM7xx EMC Module 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * Unsupported/unimplemented features: 17 * - MCMDR.FDUP (full duplex) is ignored, half duplex is not supported 18 * - Only CAM0 is supported, CAM[1-15] are not 19 * - writes to CAMEN.[1-15] are ignored, these bits always read as zeroes 20 * - MII is not implemented, MIIDA.BUSY and MIID always return zero 21 * - MCMDR.LBK is not implemented 22 * - MCMDR.{OPMOD,ENSQE,AEP,ARP} are not supported 23 * - H/W FIFOs are not supported, MCMDR.FFTCR is ignored 24 * - MGSTA.SQE is not supported 25 * - pause and control frames are not implemented 26 * - MGSTA.CCNT is not supported 27 * - MPCNT, DMARFS are not implemented 28 */ 29 30 #include "qemu/osdep.h" 31 32 /* For crc32 */ 33 #include <zlib.h> 34 35 #include "qemu-common.h" 36 #include "hw/irq.h" 37 #include "hw/qdev-clock.h" 38 #include "hw/qdev-properties.h" 39 #include "hw/net/npcm7xx_emc.h" 40 #include "net/eth.h" 41 #include "migration/vmstate.h" 42 #include "qemu/bitops.h" 43 #include "qemu/error-report.h" 44 #include "qemu/log.h" 45 #include "qemu/module.h" 46 #include "qemu/units.h" 47 #include "sysemu/dma.h" 48 #include "trace.h" 49 50 #define CRC_LENGTH 4 51 52 /* 53 * The maximum size of a (layer 2) ethernet frame as defined by 802.3. 54 * 1518 = 6(dest macaddr) + 6(src macaddr) + 2(proto) + 4(crc) + 1500(payload) 55 * This does not include an additional 4 for the vlan field (802.1q). 56 */ 57 #define MAX_ETH_FRAME_SIZE 1518 58 59 static const char *emc_reg_name(int regno) 60 { 61 #define REG(name) case REG_ ## name: return #name; 62 switch (regno) { 63 REG(CAMCMR) 64 REG(CAMEN) 65 REG(TXDLSA) 66 REG(RXDLSA) 67 REG(MCMDR) 68 REG(MIID) 69 REG(MIIDA) 70 REG(FFTCR) 71 REG(TSDR) 72 REG(RSDR) 73 REG(DMARFC) 74 REG(MIEN) 75 REG(MISTA) 76 REG(MGSTA) 77 REG(MPCNT) 78 REG(MRPC) 79 REG(MRPCC) 80 REG(MREPC) 81 REG(DMARFS) 82 REG(CTXDSA) 83 REG(CTXBSA) 84 REG(CRXDSA) 85 REG(CRXBSA) 86 case REG_CAMM_BASE + 0: return "CAM0M"; 87 case REG_CAML_BASE + 0: return "CAM0L"; 88 case REG_CAMM_BASE + 2 ... REG_CAMML_LAST: 89 /* Only CAM0 is supported, fold the others into something simple. */ 90 if (regno & 1) { 91 return "CAM<n>L"; 92 } else { 93 return "CAM<n>M"; 94 } 95 default: return "UNKNOWN"; 96 } 97 #undef REG 98 } 99 100 static void emc_reset(NPCM7xxEMCState *emc) 101 { 102 trace_npcm7xx_emc_reset(emc->emc_num); 103 104 memset(&emc->regs[0], 0, sizeof(emc->regs)); 105 106 /* These regs have non-zero reset values. */ 107 emc->regs[REG_TXDLSA] = 0xfffffffc; 108 emc->regs[REG_RXDLSA] = 0xfffffffc; 109 emc->regs[REG_MIIDA] = 0x00900000; 110 emc->regs[REG_FFTCR] = 0x0101; 111 emc->regs[REG_DMARFC] = 0x0800; 112 emc->regs[REG_MPCNT] = 0x7fff; 113 114 emc->tx_active = false; 115 emc->rx_active = false; 116 } 117 118 static void npcm7xx_emc_reset(DeviceState *dev) 119 { 120 NPCM7xxEMCState *emc = NPCM7XX_EMC(dev); 121 emc_reset(emc); 122 } 123 124 static void emc_soft_reset(NPCM7xxEMCState *emc) 125 { 126 /* 127 * The docs say at least MCMDR.{LBK,OPMOD} bits are not changed during a 128 * soft reset, but does not go into further detail. For now, KISS. 129 */ 130 uint32_t mcmdr = emc->regs[REG_MCMDR]; 131 emc_reset(emc); 132 emc->regs[REG_MCMDR] = mcmdr & (REG_MCMDR_LBK | REG_MCMDR_OPMOD); 133 134 qemu_set_irq(emc->tx_irq, 0); 135 qemu_set_irq(emc->rx_irq, 0); 136 } 137 138 static void emc_set_link(NetClientState *nc) 139 { 140 /* Nothing to do yet. */ 141 } 142 143 /* MISTA.TXINTR is the union of the individual bits with their enables. */ 144 static void emc_update_mista_txintr(NPCM7xxEMCState *emc) 145 { 146 /* Only look at the bits we support. */ 147 uint32_t mask = (REG_MISTA_TXBERR | 148 REG_MISTA_TDU | 149 REG_MISTA_TXCP); 150 if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { 151 emc->regs[REG_MISTA] |= REG_MISTA_TXINTR; 152 } else { 153 emc->regs[REG_MISTA] &= ~REG_MISTA_TXINTR; 154 } 155 } 156 157 /* MISTA.RXINTR is the union of the individual bits with their enables. */ 158 static void emc_update_mista_rxintr(NPCM7xxEMCState *emc) 159 { 160 /* Only look at the bits we support. */ 161 uint32_t mask = (REG_MISTA_RXBERR | 162 REG_MISTA_RDU | 163 REG_MISTA_RXGD); 164 if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { 165 emc->regs[REG_MISTA] |= REG_MISTA_RXINTR; 166 } else { 167 emc->regs[REG_MISTA] &= ~REG_MISTA_RXINTR; 168 } 169 } 170 171 /* N.B. emc_update_mista_txintr must have already been called. */ 172 static void emc_update_tx_irq(NPCM7xxEMCState *emc) 173 { 174 int level = !!(emc->regs[REG_MISTA] & 175 emc->regs[REG_MIEN] & 176 REG_MISTA_TXINTR); 177 trace_npcm7xx_emc_update_tx_irq(level); 178 qemu_set_irq(emc->tx_irq, level); 179 } 180 181 /* N.B. emc_update_mista_rxintr must have already been called. */ 182 static void emc_update_rx_irq(NPCM7xxEMCState *emc) 183 { 184 int level = !!(emc->regs[REG_MISTA] & 185 emc->regs[REG_MIEN] & 186 REG_MISTA_RXINTR); 187 trace_npcm7xx_emc_update_rx_irq(level); 188 qemu_set_irq(emc->rx_irq, level); 189 } 190 191 /* Update IRQ states due to changes in MIEN,MISTA. */ 192 static void emc_update_irq_from_reg_change(NPCM7xxEMCState *emc) 193 { 194 emc_update_mista_txintr(emc); 195 emc_update_tx_irq(emc); 196 197 emc_update_mista_rxintr(emc); 198 emc_update_rx_irq(emc); 199 } 200 201 static int emc_read_tx_desc(dma_addr_t addr, NPCM7xxEMCTxDesc *desc) 202 { 203 if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc))) { 204 qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%" 205 HWADDR_PRIx "\n", __func__, addr); 206 return -1; 207 } 208 desc->flags = le32_to_cpu(desc->flags); 209 desc->txbsa = le32_to_cpu(desc->txbsa); 210 desc->status_and_length = le32_to_cpu(desc->status_and_length); 211 desc->ntxdsa = le32_to_cpu(desc->ntxdsa); 212 return 0; 213 } 214 215 static int emc_write_tx_desc(const NPCM7xxEMCTxDesc *desc, dma_addr_t addr) 216 { 217 NPCM7xxEMCTxDesc le_desc; 218 219 le_desc.flags = cpu_to_le32(desc->flags); 220 le_desc.txbsa = cpu_to_le32(desc->txbsa); 221 le_desc.status_and_length = cpu_to_le32(desc->status_and_length); 222 le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa); 223 if (dma_memory_write(&address_space_memory, addr, &le_desc, 224 sizeof(le_desc))) { 225 qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%" 226 HWADDR_PRIx "\n", __func__, addr); 227 return -1; 228 } 229 return 0; 230 } 231 232 static int emc_read_rx_desc(dma_addr_t addr, NPCM7xxEMCRxDesc *desc) 233 { 234 if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc))) { 235 qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%" 236 HWADDR_PRIx "\n", __func__, addr); 237 return -1; 238 } 239 desc->status_and_length = le32_to_cpu(desc->status_and_length); 240 desc->rxbsa = le32_to_cpu(desc->rxbsa); 241 desc->reserved = le32_to_cpu(desc->reserved); 242 desc->nrxdsa = le32_to_cpu(desc->nrxdsa); 243 return 0; 244 } 245 246 static int emc_write_rx_desc(const NPCM7xxEMCRxDesc *desc, dma_addr_t addr) 247 { 248 NPCM7xxEMCRxDesc le_desc; 249 250 le_desc.status_and_length = cpu_to_le32(desc->status_and_length); 251 le_desc.rxbsa = cpu_to_le32(desc->rxbsa); 252 le_desc.reserved = cpu_to_le32(desc->reserved); 253 le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa); 254 if (dma_memory_write(&address_space_memory, addr, &le_desc, 255 sizeof(le_desc))) { 256 qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%" 257 HWADDR_PRIx "\n", __func__, addr); 258 return -1; 259 } 260 return 0; 261 } 262 263 static void emc_set_mista(NPCM7xxEMCState *emc, uint32_t flags) 264 { 265 trace_npcm7xx_emc_set_mista(flags); 266 emc->regs[REG_MISTA] |= flags; 267 if (extract32(flags, 16, 16)) { 268 emc_update_mista_txintr(emc); 269 } 270 if (extract32(flags, 0, 16)) { 271 emc_update_mista_rxintr(emc); 272 } 273 } 274 275 static void emc_halt_tx(NPCM7xxEMCState *emc, uint32_t mista_flag) 276 { 277 emc->tx_active = false; 278 emc_set_mista(emc, mista_flag); 279 } 280 281 static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) 282 { 283 emc->rx_active = false; 284 emc_set_mista(emc, mista_flag); 285 } 286 287 static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc) 288 { 289 emc->rx_active = true; 290 qemu_flush_queued_packets(qemu_get_queue(emc->nic)); 291 } 292 293 static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, 294 const NPCM7xxEMCTxDesc *tx_desc, 295 uint32_t desc_addr) 296 { 297 /* Update the current descriptor, if only to reset the owner flag. */ 298 if (emc_write_tx_desc(tx_desc, desc_addr)) { 299 /* 300 * We just read it so this shouldn't generally happen. 301 * Error already reported. 302 */ 303 emc_set_mista(emc, REG_MISTA_TXBERR); 304 } 305 emc->regs[REG_CTXDSA] = TX_DESC_NTXDSA(tx_desc->ntxdsa); 306 } 307 308 static void emc_set_next_rx_descriptor(NPCM7xxEMCState *emc, 309 const NPCM7xxEMCRxDesc *rx_desc, 310 uint32_t desc_addr) 311 { 312 /* Update the current descriptor, if only to reset the owner flag. */ 313 if (emc_write_rx_desc(rx_desc, desc_addr)) { 314 /* 315 * We just read it so this shouldn't generally happen. 316 * Error already reported. 317 */ 318 emc_set_mista(emc, REG_MISTA_RXBERR); 319 } 320 emc->regs[REG_CRXDSA] = RX_DESC_NRXDSA(rx_desc->nrxdsa); 321 } 322 323 static void emc_try_send_next_packet(NPCM7xxEMCState *emc) 324 { 325 /* Working buffer for sending out packets. Most packets fit in this. */ 326 #define TX_BUFFER_SIZE 2048 327 uint8_t tx_send_buffer[TX_BUFFER_SIZE]; 328 uint32_t desc_addr = TX_DESC_NTXDSA(emc->regs[REG_CTXDSA]); 329 NPCM7xxEMCTxDesc tx_desc; 330 uint32_t next_buf_addr, length; 331 uint8_t *buf; 332 g_autofree uint8_t *malloced_buf = NULL; 333 334 if (emc_read_tx_desc(desc_addr, &tx_desc)) { 335 /* Error reading descriptor, already reported. */ 336 emc_halt_tx(emc, REG_MISTA_TXBERR); 337 emc_update_tx_irq(emc); 338 return; 339 } 340 341 /* Nothing we can do if we don't own the descriptor. */ 342 if (!(tx_desc.flags & TX_DESC_FLAG_OWNER_MASK)) { 343 trace_npcm7xx_emc_cpu_owned_desc(desc_addr); 344 emc_halt_tx(emc, REG_MISTA_TDU); 345 emc_update_tx_irq(emc); 346 return; 347 } 348 349 /* Give the descriptor back regardless of what happens. */ 350 tx_desc.flags &= ~TX_DESC_FLAG_OWNER_MASK; 351 tx_desc.status_and_length &= 0xffff; 352 353 /* 354 * Despite the h/w documentation saying the tx buffer is word aligned, 355 * the linux driver does not word align the buffer. There is value in not 356 * aligning the buffer: See the description of NET_IP_ALIGN in linux 357 * kernel sources. 358 */ 359 next_buf_addr = tx_desc.txbsa; 360 emc->regs[REG_CTXBSA] = next_buf_addr; 361 length = TX_DESC_PKT_LEN(tx_desc.status_and_length); 362 buf = &tx_send_buffer[0]; 363 364 if (length > sizeof(tx_send_buffer)) { 365 malloced_buf = g_malloc(length); 366 buf = malloced_buf; 367 } 368 369 if (dma_memory_read(&address_space_memory, next_buf_addr, buf, length)) { 370 qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read packet @ 0x%x\n", 371 __func__, next_buf_addr); 372 emc_set_mista(emc, REG_MISTA_TXBERR); 373 emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr); 374 emc_update_tx_irq(emc); 375 trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); 376 return; 377 } 378 379 if ((tx_desc.flags & TX_DESC_FLAG_PADEN) && (length < MIN_PACKET_LENGTH)) { 380 memset(buf + length, 0, MIN_PACKET_LENGTH - length); 381 length = MIN_PACKET_LENGTH; 382 } 383 384 /* N.B. emc_receive can get called here. */ 385 qemu_send_packet(qemu_get_queue(emc->nic), buf, length); 386 trace_npcm7xx_emc_sent_packet(length); 387 388 tx_desc.status_and_length |= TX_DESC_STATUS_TXCP; 389 if (tx_desc.flags & TX_DESC_FLAG_INTEN) { 390 emc_set_mista(emc, REG_MISTA_TXCP); 391 } 392 if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_TXINTR) { 393 tx_desc.status_and_length |= TX_DESC_STATUS_TXINTR; 394 } 395 396 emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr); 397 emc_update_tx_irq(emc); 398 trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); 399 } 400 401 static bool emc_can_receive(NetClientState *nc) 402 { 403 NPCM7xxEMCState *emc = NPCM7XX_EMC(qemu_get_nic_opaque(nc)); 404 405 bool can_receive = emc->rx_active; 406 trace_npcm7xx_emc_can_receive(can_receive); 407 return can_receive; 408 } 409 410 /* If result is false then *fail_reason contains the reason. */ 411 static bool emc_receive_filter1(NPCM7xxEMCState *emc, const uint8_t *buf, 412 size_t len, const char **fail_reason) 413 { 414 eth_pkt_types_e pkt_type = get_eth_packet_type(PKT_GET_ETH_HDR(buf)); 415 416 switch (pkt_type) { 417 case ETH_PKT_BCAST: 418 if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { 419 return true; 420 } else { 421 *fail_reason = "Broadcast packet disabled"; 422 return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_ABP); 423 } 424 case ETH_PKT_MCAST: 425 if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { 426 return true; 427 } else { 428 *fail_reason = "Multicast packet disabled"; 429 return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_AMP); 430 } 431 case ETH_PKT_UCAST: { 432 bool matches; 433 if (emc->regs[REG_CAMCMR] & REG_CAMCMR_AUP) { 434 return true; 435 } 436 matches = ((emc->regs[REG_CAMCMR] & REG_CAMCMR_ECMP) && 437 /* We only support one CAM register, CAM0. */ 438 (emc->regs[REG_CAMEN] & (1 << 0)) && 439 memcmp(buf, emc->conf.macaddr.a, ETH_ALEN) == 0); 440 if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { 441 *fail_reason = "MACADDR matched, comparison complemented"; 442 return !matches; 443 } else { 444 *fail_reason = "MACADDR didn't match"; 445 return matches; 446 } 447 } 448 default: 449 g_assert_not_reached(); 450 } 451 } 452 453 static bool emc_receive_filter(NPCM7xxEMCState *emc, const uint8_t *buf, 454 size_t len) 455 { 456 const char *fail_reason = NULL; 457 bool ok = emc_receive_filter1(emc, buf, len, &fail_reason); 458 if (!ok) { 459 trace_npcm7xx_emc_packet_filtered_out(fail_reason); 460 } 461 return ok; 462 } 463 464 static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1) 465 { 466 NPCM7xxEMCState *emc = NPCM7XX_EMC(qemu_get_nic_opaque(nc)); 467 const uint32_t len = len1; 468 size_t max_frame_len; 469 bool long_frame; 470 uint32_t desc_addr; 471 NPCM7xxEMCRxDesc rx_desc; 472 uint32_t crc; 473 uint8_t *crc_ptr; 474 uint32_t buf_addr; 475 476 trace_npcm7xx_emc_receiving_packet(len); 477 478 if (!emc_can_receive(nc)) { 479 qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__); 480 return -1; 481 } 482 483 if (len < ETH_HLEN || 484 /* Defensive programming: drop unsupportable large packets. */ 485 len > 0xffff - CRC_LENGTH) { 486 qemu_log_mask(LOG_GUEST_ERROR, "%s: Dropped frame of %u bytes\n", 487 __func__, len); 488 return len; 489 } 490 491 /* 492 * DENI is set if EMC received the Length/Type field of the incoming 493 * packet, so it will be set regardless of what happens next. 494 */ 495 emc_set_mista(emc, REG_MISTA_DENI); 496 497 if (!emc_receive_filter(emc, buf, len)) { 498 emc_update_rx_irq(emc); 499 return len; 500 } 501 502 /* Huge frames (> DMARFC) are dropped. */ 503 max_frame_len = REG_DMARFC_RXMS(emc->regs[REG_DMARFC]); 504 if (len + CRC_LENGTH > max_frame_len) { 505 trace_npcm7xx_emc_packet_dropped(len); 506 emc_set_mista(emc, REG_MISTA_DFOI); 507 emc_update_rx_irq(emc); 508 return len; 509 } 510 511 /* 512 * Long Frames (> MAX_ETH_FRAME_SIZE) are also dropped, unless MCMDR.ALP 513 * is set. 514 */ 515 long_frame = false; 516 if (len + CRC_LENGTH > MAX_ETH_FRAME_SIZE) { 517 if (emc->regs[REG_MCMDR] & REG_MCMDR_ALP) { 518 long_frame = true; 519 } else { 520 trace_npcm7xx_emc_packet_dropped(len); 521 emc_set_mista(emc, REG_MISTA_PTLE); 522 emc_update_rx_irq(emc); 523 return len; 524 } 525 } 526 527 desc_addr = RX_DESC_NRXDSA(emc->regs[REG_CRXDSA]); 528 if (emc_read_rx_desc(desc_addr, &rx_desc)) { 529 /* Error reading descriptor, already reported. */ 530 emc_halt_rx(emc, REG_MISTA_RXBERR); 531 emc_update_rx_irq(emc); 532 return len; 533 } 534 535 /* Nothing we can do if we don't own the descriptor. */ 536 if (!(rx_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK)) { 537 trace_npcm7xx_emc_cpu_owned_desc(desc_addr); 538 emc_halt_rx(emc, REG_MISTA_RDU); 539 emc_update_rx_irq(emc); 540 return len; 541 } 542 543 crc = 0; 544 crc_ptr = (uint8_t *) &crc; 545 if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { 546 crc = cpu_to_be32(crc32(~0, buf, len)); 547 } 548 549 /* Give the descriptor back regardless of what happens. */ 550 rx_desc.status_and_length &= ~RX_DESC_STATUS_OWNER_MASK; 551 552 buf_addr = rx_desc.rxbsa; 553 emc->regs[REG_CRXBSA] = buf_addr; 554 if (dma_memory_write(&address_space_memory, buf_addr, buf, len) || 555 (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC) && 556 dma_memory_write(&address_space_memory, buf_addr + len, crc_ptr, 557 4))) { 558 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bus error writing packet\n", 559 __func__); 560 emc_set_mista(emc, REG_MISTA_RXBERR); 561 emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr); 562 emc_update_rx_irq(emc); 563 trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); 564 return len; 565 } 566 567 trace_npcm7xx_emc_received_packet(len); 568 569 /* Note: We've already verified len+4 <= 0xffff. */ 570 rx_desc.status_and_length = len; 571 if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { 572 rx_desc.status_and_length += 4; 573 } 574 rx_desc.status_and_length |= RX_DESC_STATUS_RXGD; 575 emc_set_mista(emc, REG_MISTA_RXGD); 576 577 if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_RXINTR) { 578 rx_desc.status_and_length |= RX_DESC_STATUS_RXINTR; 579 } 580 if (long_frame) { 581 rx_desc.status_and_length |= RX_DESC_STATUS_PTLE; 582 } 583 584 emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr); 585 emc_update_rx_irq(emc); 586 trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); 587 return len; 588 } 589 590 static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size) 591 { 592 NPCM7xxEMCState *emc = opaque; 593 uint32_t reg = offset / sizeof(uint32_t); 594 uint32_t result; 595 596 if (reg >= NPCM7XX_NUM_EMC_REGS) { 597 qemu_log_mask(LOG_GUEST_ERROR, 598 "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", 599 __func__, offset); 600 return 0; 601 } 602 603 switch (reg) { 604 case REG_MIID: 605 /* 606 * We don't implement MII. For determinism, always return zero as 607 * writes record the last value written for debugging purposes. 608 */ 609 qemu_log_mask(LOG_UNIMP, "%s: Read of MIID, returning 0\n", __func__); 610 result = 0; 611 break; 612 case REG_TSDR: 613 case REG_RSDR: 614 qemu_log_mask(LOG_GUEST_ERROR, 615 "%s: Read of write-only reg, %s/%d\n", 616 __func__, emc_reg_name(reg), reg); 617 return 0; 618 default: 619 result = emc->regs[reg]; 620 break; 621 } 622 623 trace_npcm7xx_emc_reg_read(emc->emc_num, result, emc_reg_name(reg), reg); 624 return result; 625 } 626 627 static void npcm7xx_emc_write(void *opaque, hwaddr offset, 628 uint64_t v, unsigned size) 629 { 630 NPCM7xxEMCState *emc = opaque; 631 uint32_t reg = offset / sizeof(uint32_t); 632 uint32_t value = v; 633 634 g_assert(size == sizeof(uint32_t)); 635 636 if (reg >= NPCM7XX_NUM_EMC_REGS) { 637 qemu_log_mask(LOG_GUEST_ERROR, 638 "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", 639 __func__, offset); 640 return; 641 } 642 643 trace_npcm7xx_emc_reg_write(emc->emc_num, emc_reg_name(reg), reg, value); 644 645 switch (reg) { 646 case REG_CAMCMR: 647 emc->regs[reg] = value; 648 break; 649 case REG_CAMEN: 650 /* Only CAM0 is supported, don't pretend otherwise. */ 651 if (value & ~1) { 652 qemu_log_mask(LOG_GUEST_ERROR, 653 "%s: Only CAM0 is supported, cannot enable others" 654 ": 0x%x\n", 655 __func__, value); 656 } 657 emc->regs[reg] = value & 1; 658 break; 659 case REG_CAMM_BASE + 0: 660 emc->regs[reg] = value; 661 emc->conf.macaddr.a[0] = value >> 24; 662 emc->conf.macaddr.a[1] = value >> 16; 663 emc->conf.macaddr.a[2] = value >> 8; 664 emc->conf.macaddr.a[3] = value >> 0; 665 break; 666 case REG_CAML_BASE + 0: 667 emc->regs[reg] = value; 668 emc->conf.macaddr.a[4] = value >> 24; 669 emc->conf.macaddr.a[5] = value >> 16; 670 break; 671 case REG_MCMDR: { 672 uint32_t prev; 673 if (value & REG_MCMDR_SWR) { 674 emc_soft_reset(emc); 675 /* On h/w the reset happens over multiple cycles. For now KISS. */ 676 break; 677 } 678 prev = emc->regs[reg]; 679 emc->regs[reg] = value; 680 /* Update tx state. */ 681 if (!(prev & REG_MCMDR_TXON) && 682 (value & REG_MCMDR_TXON)) { 683 emc->regs[REG_CTXDSA] = emc->regs[REG_TXDLSA]; 684 /* 685 * Linux kernel turns TX on with CPU still holding descriptor, 686 * which suggests we should wait for a write to TSDR before trying 687 * to send a packet: so we don't send one here. 688 */ 689 } else if ((prev & REG_MCMDR_TXON) && 690 !(value & REG_MCMDR_TXON)) { 691 emc->regs[REG_MGSTA] |= REG_MGSTA_TXHA; 692 } 693 if (!(value & REG_MCMDR_TXON)) { 694 emc_halt_tx(emc, 0); 695 } 696 /* Update rx state. */ 697 if (!(prev & REG_MCMDR_RXON) && 698 (value & REG_MCMDR_RXON)) { 699 emc->regs[REG_CRXDSA] = emc->regs[REG_RXDLSA]; 700 } else if ((prev & REG_MCMDR_RXON) && 701 !(value & REG_MCMDR_RXON)) { 702 emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA; 703 } 704 if (value & REG_MCMDR_RXON) { 705 emc_enable_rx_and_flush(emc); 706 } else { 707 emc_halt_rx(emc, 0); 708 } 709 break; 710 } 711 case REG_TXDLSA: 712 case REG_RXDLSA: 713 case REG_DMARFC: 714 case REG_MIID: 715 emc->regs[reg] = value; 716 break; 717 case REG_MIEN: 718 emc->regs[reg] = value; 719 emc_update_irq_from_reg_change(emc); 720 break; 721 case REG_MISTA: 722 /* Clear the bits that have 1 in "value". */ 723 emc->regs[reg] &= ~value; 724 emc_update_irq_from_reg_change(emc); 725 break; 726 case REG_MGSTA: 727 /* Clear the bits that have 1 in "value". */ 728 emc->regs[reg] &= ~value; 729 break; 730 case REG_TSDR: 731 if (emc->regs[REG_MCMDR] & REG_MCMDR_TXON) { 732 emc->tx_active = true; 733 /* Keep trying to send packets until we run out. */ 734 while (emc->tx_active) { 735 emc_try_send_next_packet(emc); 736 } 737 } 738 break; 739 case REG_RSDR: 740 if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { 741 emc_enable_rx_and_flush(emc); 742 } 743 break; 744 case REG_MIIDA: 745 emc->regs[reg] = value & ~REG_MIIDA_BUSY; 746 break; 747 case REG_MRPC: 748 case REG_MRPCC: 749 case REG_MREPC: 750 case REG_CTXDSA: 751 case REG_CTXBSA: 752 case REG_CRXDSA: 753 case REG_CRXBSA: 754 qemu_log_mask(LOG_GUEST_ERROR, 755 "%s: Write to read-only reg %s/%d\n", 756 __func__, emc_reg_name(reg), reg); 757 break; 758 default: 759 qemu_log_mask(LOG_UNIMP, "%s: Write to unimplemented reg %s/%d\n", 760 __func__, emc_reg_name(reg), reg); 761 break; 762 } 763 } 764 765 static const struct MemoryRegionOps npcm7xx_emc_ops = { 766 .read = npcm7xx_emc_read, 767 .write = npcm7xx_emc_write, 768 .endianness = DEVICE_LITTLE_ENDIAN, 769 .valid = { 770 .min_access_size = 4, 771 .max_access_size = 4, 772 .unaligned = false, 773 }, 774 }; 775 776 static void emc_cleanup(NetClientState *nc) 777 { 778 /* Nothing to do yet. */ 779 } 780 781 static NetClientInfo net_npcm7xx_emc_info = { 782 .type = NET_CLIENT_DRIVER_NIC, 783 .size = sizeof(NICState), 784 .can_receive = emc_can_receive, 785 .receive = emc_receive, 786 .cleanup = emc_cleanup, 787 .link_status_changed = emc_set_link, 788 }; 789 790 static void npcm7xx_emc_realize(DeviceState *dev, Error **errp) 791 { 792 NPCM7xxEMCState *emc = NPCM7XX_EMC(dev); 793 SysBusDevice *sbd = SYS_BUS_DEVICE(emc); 794 795 memory_region_init_io(&emc->iomem, OBJECT(emc), &npcm7xx_emc_ops, emc, 796 TYPE_NPCM7XX_EMC, 4 * KiB); 797 sysbus_init_mmio(sbd, &emc->iomem); 798 sysbus_init_irq(sbd, &emc->tx_irq); 799 sysbus_init_irq(sbd, &emc->rx_irq); 800 801 qemu_macaddr_default_if_unset(&emc->conf.macaddr); 802 emc->nic = qemu_new_nic(&net_npcm7xx_emc_info, &emc->conf, 803 object_get_typename(OBJECT(dev)), dev->id, emc); 804 qemu_format_nic_info_str(qemu_get_queue(emc->nic), emc->conf.macaddr.a); 805 } 806 807 static void npcm7xx_emc_unrealize(DeviceState *dev) 808 { 809 NPCM7xxEMCState *emc = NPCM7XX_EMC(dev); 810 811 qemu_del_nic(emc->nic); 812 } 813 814 static const VMStateDescription vmstate_npcm7xx_emc = { 815 .name = TYPE_NPCM7XX_EMC, 816 .version_id = 0, 817 .minimum_version_id = 0, 818 .fields = (VMStateField[]) { 819 VMSTATE_UINT8(emc_num, NPCM7xxEMCState), 820 VMSTATE_UINT32_ARRAY(regs, NPCM7xxEMCState, NPCM7XX_NUM_EMC_REGS), 821 VMSTATE_BOOL(tx_active, NPCM7xxEMCState), 822 VMSTATE_BOOL(rx_active, NPCM7xxEMCState), 823 VMSTATE_END_OF_LIST(), 824 }, 825 }; 826 827 static Property npcm7xx_emc_properties[] = { 828 DEFINE_NIC_PROPERTIES(NPCM7xxEMCState, conf), 829 DEFINE_PROP_END_OF_LIST(), 830 }; 831 832 static void npcm7xx_emc_class_init(ObjectClass *klass, void *data) 833 { 834 DeviceClass *dc = DEVICE_CLASS(klass); 835 836 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 837 dc->desc = "NPCM7xx EMC Controller"; 838 dc->realize = npcm7xx_emc_realize; 839 dc->unrealize = npcm7xx_emc_unrealize; 840 dc->reset = npcm7xx_emc_reset; 841 dc->vmsd = &vmstate_npcm7xx_emc; 842 device_class_set_props(dc, npcm7xx_emc_properties); 843 } 844 845 static const TypeInfo npcm7xx_emc_info = { 846 .name = TYPE_NPCM7XX_EMC, 847 .parent = TYPE_SYS_BUS_DEVICE, 848 .instance_size = sizeof(NPCM7xxEMCState), 849 .class_init = npcm7xx_emc_class_init, 850 }; 851 852 static void npcm7xx_emc_register_type(void) 853 { 854 type_register_static(&npcm7xx_emc_info); 855 } 856 857 type_init(npcm7xx_emc_register_type) 858