1 /* 2 * QEMU NE2000 emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "net/net.h" 27 #include "ne2000.h" 28 #include "hw/loader.h" 29 #include "sysemu/sysemu.h" 30 31 /* debug NE2000 card */ 32 //#define DEBUG_NE2000 33 34 #define MAX_ETH_FRAME_SIZE 1514 35 36 #define E8390_CMD 0x00 /* The command register (for all pages) */ 37 /* Page 0 register offsets. */ 38 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ 39 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ 40 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ 41 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ 42 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ 43 #define EN0_TSR 0x04 /* Transmit status reg RD */ 44 #define EN0_TPSR 0x04 /* Transmit starting page WR */ 45 #define EN0_NCR 0x05 /* Number of collision reg RD */ 46 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ 47 #define EN0_FIFO 0x06 /* FIFO RD */ 48 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ 49 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ 50 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ 51 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ 52 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ 53 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ 54 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ 55 #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ 56 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ 57 #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ 58 #define EN0_RSR 0x0c /* rx status reg RD */ 59 #define EN0_RXCR 0x0c /* RX configuration reg WR */ 60 #define EN0_TXCR 0x0d /* TX configuration reg WR */ 61 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ 62 #define EN0_DCFG 0x0e /* Data configuration reg WR */ 63 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ 64 #define EN0_IMR 0x0f /* Interrupt mask reg WR */ 65 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ 66 67 #define EN1_PHYS 0x11 68 #define EN1_CURPAG 0x17 69 #define EN1_MULT 0x18 70 71 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ 72 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ 73 74 #define EN3_CONFIG0 0x33 75 #define EN3_CONFIG1 0x34 76 #define EN3_CONFIG2 0x35 77 #define EN3_CONFIG3 0x36 78 79 /* Register accessed at EN_CMD, the 8390 base addr. */ 80 #define E8390_STOP 0x01 /* Stop and reset the chip */ 81 #define E8390_START 0x02 /* Start the chip, clear reset */ 82 #define E8390_TRANS 0x04 /* Transmit a frame */ 83 #define E8390_RREAD 0x08 /* Remote read */ 84 #define E8390_RWRITE 0x10 /* Remote write */ 85 #define E8390_NODMA 0x20 /* Remote DMA */ 86 #define E8390_PAGE0 0x00 /* Select page chip registers */ 87 #define E8390_PAGE1 0x40 /* using the two high-order bits */ 88 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ 89 90 /* Bits in EN0_ISR - Interrupt status register */ 91 #define ENISR_RX 0x01 /* Receiver, no error */ 92 #define ENISR_TX 0x02 /* Transmitter, no error */ 93 #define ENISR_RX_ERR 0x04 /* Receiver, with error */ 94 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ 95 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ 96 #define ENISR_COUNTERS 0x20 /* Counters need emptying */ 97 #define ENISR_RDC 0x40 /* remote dma complete */ 98 #define ENISR_RESET 0x80 /* Reset completed */ 99 #define ENISR_ALL 0x3f /* Interrupts we will enable */ 100 101 /* Bits in received packet status byte and EN0_RSR*/ 102 #define ENRSR_RXOK 0x01 /* Received a good packet */ 103 #define ENRSR_CRC 0x02 /* CRC error */ 104 #define ENRSR_FAE 0x04 /* frame alignment error */ 105 #define ENRSR_FO 0x08 /* FIFO overrun */ 106 #define ENRSR_MPA 0x10 /* missed pkt */ 107 #define ENRSR_PHY 0x20 /* physical/multicast address */ 108 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ 109 #define ENRSR_DEF 0x80 /* deferring */ 110 111 /* Transmitted packet status, EN0_TSR. */ 112 #define ENTSR_PTX 0x01 /* Packet transmitted without error */ 113 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ 114 #define ENTSR_COL 0x04 /* The transmit collided at least once. */ 115 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ 116 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ 117 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ 118 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ 119 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ 120 121 typedef struct PCINE2000State { 122 PCIDevice dev; 123 NE2000State ne2000; 124 } PCINE2000State; 125 126 void ne2000_reset(NE2000State *s) 127 { 128 int i; 129 130 s->isr = ENISR_RESET; 131 memcpy(s->mem, &s->c.macaddr, 6); 132 s->mem[14] = 0x57; 133 s->mem[15] = 0x57; 134 135 /* duplicate prom data */ 136 for(i = 15;i >= 0; i--) { 137 s->mem[2 * i] = s->mem[i]; 138 s->mem[2 * i + 1] = s->mem[i]; 139 } 140 } 141 142 static void ne2000_update_irq(NE2000State *s) 143 { 144 int isr; 145 isr = (s->isr & s->imr) & 0x7f; 146 #if defined(DEBUG_NE2000) 147 printf("NE2000: Set IRQ to %d (%02x %02x)\n", 148 isr ? 1 : 0, s->isr, s->imr); 149 #endif 150 qemu_set_irq(s->irq, (isr != 0)); 151 } 152 153 static int ne2000_buffer_full(NE2000State *s) 154 { 155 int avail, index, boundary; 156 157 index = s->curpag << 8; 158 boundary = s->boundary << 8; 159 if (index < boundary) 160 avail = boundary - index; 161 else 162 avail = (s->stop - s->start) - (index - boundary); 163 if (avail < (MAX_ETH_FRAME_SIZE + 4)) 164 return 1; 165 return 0; 166 } 167 168 #define MIN_BUF_SIZE 60 169 170 ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_) 171 { 172 NE2000State *s = qemu_get_nic_opaque(nc); 173 int size = size_; 174 uint8_t *p; 175 unsigned int total_len, next, avail, len, index, mcast_idx; 176 uint8_t buf1[60]; 177 static const uint8_t broadcast_macaddr[6] = 178 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 179 180 #if defined(DEBUG_NE2000) 181 printf("NE2000: received len=%d\n", size); 182 #endif 183 184 if (s->cmd & E8390_STOP || ne2000_buffer_full(s)) 185 return -1; 186 187 /* XXX: check this */ 188 if (s->rxcr & 0x10) { 189 /* promiscuous: receive all */ 190 } else { 191 if (!memcmp(buf, broadcast_macaddr, 6)) { 192 /* broadcast address */ 193 if (!(s->rxcr & 0x04)) 194 return size; 195 } else if (buf[0] & 0x01) { 196 /* multicast */ 197 if (!(s->rxcr & 0x08)) 198 return size; 199 mcast_idx = compute_mcast_idx(buf); 200 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) 201 return size; 202 } else if (s->mem[0] == buf[0] && 203 s->mem[2] == buf[1] && 204 s->mem[4] == buf[2] && 205 s->mem[6] == buf[3] && 206 s->mem[8] == buf[4] && 207 s->mem[10] == buf[5]) { 208 /* match */ 209 } else { 210 return size; 211 } 212 } 213 214 215 /* if too small buffer, then expand it */ 216 if (size < MIN_BUF_SIZE) { 217 memcpy(buf1, buf, size); 218 memset(buf1 + size, 0, MIN_BUF_SIZE - size); 219 buf = buf1; 220 size = MIN_BUF_SIZE; 221 } 222 223 index = s->curpag << 8; 224 /* 4 bytes for header */ 225 total_len = size + 4; 226 /* address for next packet (4 bytes for CRC) */ 227 next = index + ((total_len + 4 + 255) & ~0xff); 228 if (next >= s->stop) 229 next -= (s->stop - s->start); 230 /* prepare packet header */ 231 p = s->mem + index; 232 s->rsr = ENRSR_RXOK; /* receive status */ 233 /* XXX: check this */ 234 if (buf[0] & 0x01) 235 s->rsr |= ENRSR_PHY; 236 p[0] = s->rsr; 237 p[1] = next >> 8; 238 p[2] = total_len; 239 p[3] = total_len >> 8; 240 index += 4; 241 242 /* write packet data */ 243 while (size > 0) { 244 if (index <= s->stop) 245 avail = s->stop - index; 246 else 247 avail = 0; 248 len = size; 249 if (len > avail) 250 len = avail; 251 memcpy(s->mem + index, buf, len); 252 buf += len; 253 index += len; 254 if (index == s->stop) 255 index = s->start; 256 size -= len; 257 } 258 s->curpag = next >> 8; 259 260 /* now we can signal we have received something */ 261 s->isr |= ENISR_RX; 262 ne2000_update_irq(s); 263 264 return size_; 265 } 266 267 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) 268 { 269 NE2000State *s = opaque; 270 int offset, page, index; 271 272 addr &= 0xf; 273 #ifdef DEBUG_NE2000 274 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val); 275 #endif 276 if (addr == E8390_CMD) { 277 /* control register */ 278 s->cmd = val; 279 if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ 280 s->isr &= ~ENISR_RESET; 281 /* test specific case: zero length transfer */ 282 if ((val & (E8390_RREAD | E8390_RWRITE)) && 283 s->rcnt == 0) { 284 s->isr |= ENISR_RDC; 285 ne2000_update_irq(s); 286 } 287 if (val & E8390_TRANS) { 288 index = (s->tpsr << 8); 289 /* XXX: next 2 lines are a hack to make netware 3.11 work */ 290 if (index >= NE2000_PMEM_END) 291 index -= NE2000_PMEM_SIZE; 292 /* fail safe: check range on the transmitted length */ 293 if (index + s->tcnt <= NE2000_PMEM_END) { 294 qemu_send_packet(qemu_get_queue(s->nic), s->mem + index, 295 s->tcnt); 296 } 297 /* signal end of transfer */ 298 s->tsr = ENTSR_PTX; 299 s->isr |= ENISR_TX; 300 s->cmd &= ~E8390_TRANS; 301 ne2000_update_irq(s); 302 } 303 } 304 } else { 305 page = s->cmd >> 6; 306 offset = addr | (page << 4); 307 switch(offset) { 308 case EN0_STARTPG: 309 s->start = val << 8; 310 break; 311 case EN0_STOPPG: 312 s->stop = val << 8; 313 break; 314 case EN0_BOUNDARY: 315 s->boundary = val; 316 break; 317 case EN0_IMR: 318 s->imr = val; 319 ne2000_update_irq(s); 320 break; 321 case EN0_TPSR: 322 s->tpsr = val; 323 break; 324 case EN0_TCNTLO: 325 s->tcnt = (s->tcnt & 0xff00) | val; 326 break; 327 case EN0_TCNTHI: 328 s->tcnt = (s->tcnt & 0x00ff) | (val << 8); 329 break; 330 case EN0_RSARLO: 331 s->rsar = (s->rsar & 0xff00) | val; 332 break; 333 case EN0_RSARHI: 334 s->rsar = (s->rsar & 0x00ff) | (val << 8); 335 break; 336 case EN0_RCNTLO: 337 s->rcnt = (s->rcnt & 0xff00) | val; 338 break; 339 case EN0_RCNTHI: 340 s->rcnt = (s->rcnt & 0x00ff) | (val << 8); 341 break; 342 case EN0_RXCR: 343 s->rxcr = val; 344 break; 345 case EN0_DCFG: 346 s->dcfg = val; 347 break; 348 case EN0_ISR: 349 s->isr &= ~(val & 0x7f); 350 ne2000_update_irq(s); 351 break; 352 case EN1_PHYS ... EN1_PHYS + 5: 353 s->phys[offset - EN1_PHYS] = val; 354 break; 355 case EN1_CURPAG: 356 s->curpag = val; 357 break; 358 case EN1_MULT ... EN1_MULT + 7: 359 s->mult[offset - EN1_MULT] = val; 360 break; 361 } 362 } 363 } 364 365 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) 366 { 367 NE2000State *s = opaque; 368 int offset, page, ret; 369 370 addr &= 0xf; 371 if (addr == E8390_CMD) { 372 ret = s->cmd; 373 } else { 374 page = s->cmd >> 6; 375 offset = addr | (page << 4); 376 switch(offset) { 377 case EN0_TSR: 378 ret = s->tsr; 379 break; 380 case EN0_BOUNDARY: 381 ret = s->boundary; 382 break; 383 case EN0_ISR: 384 ret = s->isr; 385 break; 386 case EN0_RSARLO: 387 ret = s->rsar & 0x00ff; 388 break; 389 case EN0_RSARHI: 390 ret = s->rsar >> 8; 391 break; 392 case EN1_PHYS ... EN1_PHYS + 5: 393 ret = s->phys[offset - EN1_PHYS]; 394 break; 395 case EN1_CURPAG: 396 ret = s->curpag; 397 break; 398 case EN1_MULT ... EN1_MULT + 7: 399 ret = s->mult[offset - EN1_MULT]; 400 break; 401 case EN0_RSR: 402 ret = s->rsr; 403 break; 404 case EN2_STARTPG: 405 ret = s->start >> 8; 406 break; 407 case EN2_STOPPG: 408 ret = s->stop >> 8; 409 break; 410 case EN0_RTL8029ID0: 411 ret = 0x50; 412 break; 413 case EN0_RTL8029ID1: 414 ret = 0x43; 415 break; 416 case EN3_CONFIG0: 417 ret = 0; /* 10baseT media */ 418 break; 419 case EN3_CONFIG2: 420 ret = 0x40; /* 10baseT active */ 421 break; 422 case EN3_CONFIG3: 423 ret = 0x40; /* Full duplex */ 424 break; 425 default: 426 ret = 0x00; 427 break; 428 } 429 } 430 #ifdef DEBUG_NE2000 431 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret); 432 #endif 433 return ret; 434 } 435 436 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, 437 uint32_t val) 438 { 439 if (addr < 32 || 440 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 441 s->mem[addr] = val; 442 } 443 } 444 445 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, 446 uint32_t val) 447 { 448 addr &= ~1; /* XXX: check exact behaviour if not even */ 449 if (addr < 32 || 450 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 451 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val); 452 } 453 } 454 455 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, 456 uint32_t val) 457 { 458 addr &= ~1; /* XXX: check exact behaviour if not even */ 459 if (addr < 32 || 460 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 461 stl_le_p(s->mem + addr, val); 462 } 463 } 464 465 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) 466 { 467 if (addr < 32 || 468 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 469 return s->mem[addr]; 470 } else { 471 return 0xff; 472 } 473 } 474 475 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) 476 { 477 addr &= ~1; /* XXX: check exact behaviour if not even */ 478 if (addr < 32 || 479 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 480 return le16_to_cpu(*(uint16_t *)(s->mem + addr)); 481 } else { 482 return 0xffff; 483 } 484 } 485 486 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) 487 { 488 addr &= ~1; /* XXX: check exact behaviour if not even */ 489 if (addr < 32 || 490 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 491 return ldl_le_p(s->mem + addr); 492 } else { 493 return 0xffffffff; 494 } 495 } 496 497 static inline void ne2000_dma_update(NE2000State *s, int len) 498 { 499 s->rsar += len; 500 /* wrap */ 501 /* XXX: check what to do if rsar > stop */ 502 if (s->rsar == s->stop) 503 s->rsar = s->start; 504 505 if (s->rcnt <= len) { 506 s->rcnt = 0; 507 /* signal end of transfer */ 508 s->isr |= ENISR_RDC; 509 ne2000_update_irq(s); 510 } else { 511 s->rcnt -= len; 512 } 513 } 514 515 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) 516 { 517 NE2000State *s = opaque; 518 519 #ifdef DEBUG_NE2000 520 printf("NE2000: asic write val=0x%04x\n", val); 521 #endif 522 if (s->rcnt == 0) 523 return; 524 if (s->dcfg & 0x01) { 525 /* 16 bit access */ 526 ne2000_mem_writew(s, s->rsar, val); 527 ne2000_dma_update(s, 2); 528 } else { 529 /* 8 bit access */ 530 ne2000_mem_writeb(s, s->rsar, val); 531 ne2000_dma_update(s, 1); 532 } 533 } 534 535 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) 536 { 537 NE2000State *s = opaque; 538 int ret; 539 540 if (s->dcfg & 0x01) { 541 /* 16 bit access */ 542 ret = ne2000_mem_readw(s, s->rsar); 543 ne2000_dma_update(s, 2); 544 } else { 545 /* 8 bit access */ 546 ret = ne2000_mem_readb(s, s->rsar); 547 ne2000_dma_update(s, 1); 548 } 549 #ifdef DEBUG_NE2000 550 printf("NE2000: asic read val=0x%04x\n", ret); 551 #endif 552 return ret; 553 } 554 555 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) 556 { 557 NE2000State *s = opaque; 558 559 #ifdef DEBUG_NE2000 560 printf("NE2000: asic writel val=0x%04x\n", val); 561 #endif 562 if (s->rcnt == 0) 563 return; 564 /* 32 bit access */ 565 ne2000_mem_writel(s, s->rsar, val); 566 ne2000_dma_update(s, 4); 567 } 568 569 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) 570 { 571 NE2000State *s = opaque; 572 int ret; 573 574 /* 32 bit access */ 575 ret = ne2000_mem_readl(s, s->rsar); 576 ne2000_dma_update(s, 4); 577 #ifdef DEBUG_NE2000 578 printf("NE2000: asic readl val=0x%04x\n", ret); 579 #endif 580 return ret; 581 } 582 583 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) 584 { 585 /* nothing to do (end of reset pulse) */ 586 } 587 588 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) 589 { 590 NE2000State *s = opaque; 591 ne2000_reset(s); 592 return 0; 593 } 594 595 static int ne2000_post_load(void* opaque, int version_id) 596 { 597 NE2000State* s = opaque; 598 599 if (version_id < 2) { 600 s->rxcr = 0x0c; 601 } 602 return 0; 603 } 604 605 const VMStateDescription vmstate_ne2000 = { 606 .name = "ne2000", 607 .version_id = 2, 608 .minimum_version_id = 0, 609 .post_load = ne2000_post_load, 610 .fields = (VMStateField[]) { 611 VMSTATE_UINT8_V(rxcr, NE2000State, 2), 612 VMSTATE_UINT8(cmd, NE2000State), 613 VMSTATE_UINT32(start, NE2000State), 614 VMSTATE_UINT32(stop, NE2000State), 615 VMSTATE_UINT8(boundary, NE2000State), 616 VMSTATE_UINT8(tsr, NE2000State), 617 VMSTATE_UINT8(tpsr, NE2000State), 618 VMSTATE_UINT16(tcnt, NE2000State), 619 VMSTATE_UINT16(rcnt, NE2000State), 620 VMSTATE_UINT32(rsar, NE2000State), 621 VMSTATE_UINT8(rsr, NE2000State), 622 VMSTATE_UINT8(isr, NE2000State), 623 VMSTATE_UINT8(dcfg, NE2000State), 624 VMSTATE_UINT8(imr, NE2000State), 625 VMSTATE_BUFFER(phys, NE2000State), 626 VMSTATE_UINT8(curpag, NE2000State), 627 VMSTATE_BUFFER(mult, NE2000State), 628 VMSTATE_UNUSED(4), /* was irq */ 629 VMSTATE_BUFFER(mem, NE2000State), 630 VMSTATE_END_OF_LIST() 631 } 632 }; 633 634 static const VMStateDescription vmstate_pci_ne2000 = { 635 .name = "ne2000", 636 .version_id = 3, 637 .minimum_version_id = 3, 638 .fields = (VMStateField[]) { 639 VMSTATE_PCI_DEVICE(dev, PCINE2000State), 640 VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State), 641 VMSTATE_END_OF_LIST() 642 } 643 }; 644 645 static uint64_t ne2000_read(void *opaque, hwaddr addr, 646 unsigned size) 647 { 648 NE2000State *s = opaque; 649 650 if (addr < 0x10 && size == 1) { 651 return ne2000_ioport_read(s, addr); 652 } else if (addr == 0x10) { 653 if (size <= 2) { 654 return ne2000_asic_ioport_read(s, addr); 655 } else { 656 return ne2000_asic_ioport_readl(s, addr); 657 } 658 } else if (addr == 0x1f && size == 1) { 659 return ne2000_reset_ioport_read(s, addr); 660 } 661 return ((uint64_t)1 << (size * 8)) - 1; 662 } 663 664 static void ne2000_write(void *opaque, hwaddr addr, 665 uint64_t data, unsigned size) 666 { 667 NE2000State *s = opaque; 668 669 if (addr < 0x10 && size == 1) { 670 ne2000_ioport_write(s, addr, data); 671 } else if (addr == 0x10) { 672 if (size <= 2) { 673 ne2000_asic_ioport_write(s, addr, data); 674 } else { 675 ne2000_asic_ioport_writel(s, addr, data); 676 } 677 } else if (addr == 0x1f && size == 1) { 678 ne2000_reset_ioport_write(s, addr, data); 679 } 680 } 681 682 static const MemoryRegionOps ne2000_ops = { 683 .read = ne2000_read, 684 .write = ne2000_write, 685 .endianness = DEVICE_LITTLE_ENDIAN, 686 }; 687 688 /***********************************************************/ 689 /* PCI NE2000 definitions */ 690 691 void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size) 692 { 693 memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size); 694 } 695 696 static NetClientInfo net_ne2000_info = { 697 .type = NET_CLIENT_OPTIONS_KIND_NIC, 698 .size = sizeof(NICState), 699 .receive = ne2000_receive, 700 }; 701 702 static void pci_ne2000_realize(PCIDevice *pci_dev, Error **errp) 703 { 704 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); 705 NE2000State *s; 706 uint8_t *pci_conf; 707 708 pci_conf = d->dev.config; 709 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 710 711 s = &d->ne2000; 712 ne2000_setup_io(s, DEVICE(pci_dev), 0x100); 713 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io); 714 s->irq = pci_allocate_irq(&d->dev); 715 716 qemu_macaddr_default_if_unset(&s->c.macaddr); 717 ne2000_reset(s); 718 719 s->nic = qemu_new_nic(&net_ne2000_info, &s->c, 720 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s); 721 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a); 722 } 723 724 static void pci_ne2000_exit(PCIDevice *pci_dev) 725 { 726 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); 727 NE2000State *s = &d->ne2000; 728 729 qemu_del_nic(s->nic); 730 qemu_free_irq(s->irq); 731 } 732 733 static void ne2000_instance_init(Object *obj) 734 { 735 PCIDevice *pci_dev = PCI_DEVICE(obj); 736 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); 737 NE2000State *s = &d->ne2000; 738 739 device_add_bootindex_property(obj, &s->c.bootindex, 740 "bootindex", "/ethernet-phy@0", 741 &pci_dev->qdev, NULL); 742 } 743 744 static Property ne2000_properties[] = { 745 DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c), 746 DEFINE_PROP_END_OF_LIST(), 747 }; 748 749 static void ne2000_class_init(ObjectClass *klass, void *data) 750 { 751 DeviceClass *dc = DEVICE_CLASS(klass); 752 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 753 754 k->realize = pci_ne2000_realize; 755 k->exit = pci_ne2000_exit; 756 k->romfile = "efi-ne2k_pci.rom", 757 k->vendor_id = PCI_VENDOR_ID_REALTEK; 758 k->device_id = PCI_DEVICE_ID_REALTEK_8029; 759 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 760 dc->vmsd = &vmstate_pci_ne2000; 761 dc->props = ne2000_properties; 762 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 763 } 764 765 static const TypeInfo ne2000_info = { 766 .name = "ne2k_pci", 767 .parent = TYPE_PCI_DEVICE, 768 .instance_size = sizeof(PCINE2000State), 769 .class_init = ne2000_class_init, 770 .instance_init = ne2000_instance_init, 771 }; 772 773 static void ne2000_register_types(void) 774 { 775 type_register_static(&ne2000_info); 776 } 777 778 type_init(ne2000_register_types) 779