xref: /openbmc/qemu/hw/net/ne2000.c (revision 64552b6b)
1 /*
2  * QEMU NE2000 emulation
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "net/eth.h"
27 #include "qemu/module.h"
28 #include "hw/irq.h"
29 #include "ne2000.h"
30 #include "sysemu/sysemu.h"
31 #include "trace.h"
32 
33 /* debug NE2000 card */
34 //#define DEBUG_NE2000
35 
36 #define MAX_ETH_FRAME_SIZE 1514
37 
38 #define E8390_CMD	0x00  /* The command register (for all pages) */
39 /* Page 0 register offsets. */
40 #define EN0_CLDALO	0x01	/* Low byte of current local dma addr  RD */
41 #define EN0_STARTPG	0x01	/* Starting page of ring bfr WR */
42 #define EN0_CLDAHI	0x02	/* High byte of current local dma addr  RD */
43 #define EN0_STOPPG	0x02	/* Ending page +1 of ring bfr WR */
44 #define EN0_BOUNDARY	0x03	/* Boundary page of ring bfr RD WR */
45 #define EN0_TSR		0x04	/* Transmit status reg RD */
46 #define EN0_TPSR	0x04	/* Transmit starting page WR */
47 #define EN0_NCR		0x05	/* Number of collision reg RD */
48 #define EN0_TCNTLO	0x05	/* Low  byte of tx byte count WR */
49 #define EN0_FIFO	0x06	/* FIFO RD */
50 #define EN0_TCNTHI	0x06	/* High byte of tx byte count WR */
51 #define EN0_ISR		0x07	/* Interrupt status reg RD WR */
52 #define EN0_CRDALO	0x08	/* low byte of current remote dma address RD */
53 #define EN0_RSARLO	0x08	/* Remote start address reg 0 */
54 #define EN0_CRDAHI	0x09	/* high byte, current remote dma address RD */
55 #define EN0_RSARHI	0x09	/* Remote start address reg 1 */
56 #define EN0_RCNTLO	0x0a	/* Remote byte count reg WR */
57 #define EN0_RTL8029ID0	0x0a	/* Realtek ID byte #1 RD */
58 #define EN0_RCNTHI	0x0b	/* Remote byte count reg WR */
59 #define EN0_RTL8029ID1	0x0b	/* Realtek ID byte #2 RD */
60 #define EN0_RSR		0x0c	/* rx status reg RD */
61 #define EN0_RXCR	0x0c	/* RX configuration reg WR */
62 #define EN0_TXCR	0x0d	/* TX configuration reg WR */
63 #define EN0_COUNTER0	0x0d	/* Rcv alignment error counter RD */
64 #define EN0_DCFG	0x0e	/* Data configuration reg WR */
65 #define EN0_COUNTER1	0x0e	/* Rcv CRC error counter RD */
66 #define EN0_IMR		0x0f	/* Interrupt mask reg WR */
67 #define EN0_COUNTER2	0x0f	/* Rcv missed frame error counter RD */
68 
69 #define EN1_PHYS        0x11
70 #define EN1_CURPAG      0x17
71 #define EN1_MULT        0x18
72 
73 #define EN2_STARTPG	0x21	/* Starting page of ring bfr RD */
74 #define EN2_STOPPG	0x22	/* Ending page +1 of ring bfr RD */
75 
76 #define EN3_CONFIG0	0x33
77 #define EN3_CONFIG1	0x34
78 #define EN3_CONFIG2	0x35
79 #define EN3_CONFIG3	0x36
80 
81 /*  Register accessed at EN_CMD, the 8390 base addr.  */
82 #define E8390_STOP	0x01	/* Stop and reset the chip */
83 #define E8390_START	0x02	/* Start the chip, clear reset */
84 #define E8390_TRANS	0x04	/* Transmit a frame */
85 #define E8390_RREAD	0x08	/* Remote read */
86 #define E8390_RWRITE	0x10	/* Remote write  */
87 #define E8390_NODMA	0x20	/* Remote DMA */
88 #define E8390_PAGE0	0x00	/* Select page chip registers */
89 #define E8390_PAGE1	0x40	/* using the two high-order bits */
90 #define E8390_PAGE2	0x80	/* Page 3 is invalid. */
91 
92 /* Bits in EN0_ISR - Interrupt status register */
93 #define ENISR_RX	0x01	/* Receiver, no error */
94 #define ENISR_TX	0x02	/* Transmitter, no error */
95 #define ENISR_RX_ERR	0x04	/* Receiver, with error */
96 #define ENISR_TX_ERR	0x08	/* Transmitter, with error */
97 #define ENISR_OVER	0x10	/* Receiver overwrote the ring */
98 #define ENISR_COUNTERS	0x20	/* Counters need emptying */
99 #define ENISR_RDC	0x40	/* remote dma complete */
100 #define ENISR_RESET	0x80	/* Reset completed */
101 #define ENISR_ALL	0x3f	/* Interrupts we will enable */
102 
103 /* Bits in received packet status byte and EN0_RSR*/
104 #define ENRSR_RXOK	0x01	/* Received a good packet */
105 #define ENRSR_CRC	0x02	/* CRC error */
106 #define ENRSR_FAE	0x04	/* frame alignment error */
107 #define ENRSR_FO	0x08	/* FIFO overrun */
108 #define ENRSR_MPA	0x10	/* missed pkt */
109 #define ENRSR_PHY	0x20	/* physical/multicast address */
110 #define ENRSR_DIS	0x40	/* receiver disable. set in monitor mode */
111 #define ENRSR_DEF	0x80	/* deferring */
112 
113 /* Transmitted packet status, EN0_TSR. */
114 #define ENTSR_PTX 0x01	/* Packet transmitted without error */
115 #define ENTSR_ND  0x02	/* The transmit wasn't deferred. */
116 #define ENTSR_COL 0x04	/* The transmit collided at least once. */
117 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
118 #define ENTSR_CRS 0x10	/* The carrier sense was lost. */
119 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
120 #define ENTSR_CDH 0x40	/* The collision detect "heartbeat" signal was lost. */
121 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
122 
123 void ne2000_reset(NE2000State *s)
124 {
125     int i;
126 
127     s->isr = ENISR_RESET;
128     memcpy(s->mem, &s->c.macaddr, 6);
129     s->mem[14] = 0x57;
130     s->mem[15] = 0x57;
131 
132     /* duplicate prom data */
133     for(i = 15;i >= 0; i--) {
134         s->mem[2 * i] = s->mem[i];
135         s->mem[2 * i + 1] = s->mem[i];
136     }
137 }
138 
139 static void ne2000_update_irq(NE2000State *s)
140 {
141     int isr;
142     isr = (s->isr & s->imr) & 0x7f;
143 #if defined(DEBUG_NE2000)
144     printf("NE2000: Set IRQ to %d (%02x %02x)\n",
145            isr ? 1 : 0, s->isr, s->imr);
146 #endif
147     qemu_set_irq(s->irq, (isr != 0));
148 }
149 
150 static int ne2000_buffer_full(NE2000State *s)
151 {
152     int avail, index, boundary;
153 
154     if (s->stop <= s->start) {
155         return 1;
156     }
157 
158     index = s->curpag << 8;
159     boundary = s->boundary << 8;
160     if (index < boundary)
161         avail = boundary - index;
162     else
163         avail = (s->stop - s->start) - (index - boundary);
164     if (avail < (MAX_ETH_FRAME_SIZE + 4))
165         return 1;
166     return 0;
167 }
168 
169 #define MIN_BUF_SIZE 60
170 
171 ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
172 {
173     NE2000State *s = qemu_get_nic_opaque(nc);
174     size_t size = size_;
175     uint8_t *p;
176     unsigned int total_len, next, avail, len, index, mcast_idx;
177     uint8_t buf1[60];
178     static const uint8_t broadcast_macaddr[6] =
179         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
180 
181 #if defined(DEBUG_NE2000)
182     printf("NE2000: received len=%zu\n", size);
183 #endif
184 
185     if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
186         return -1;
187 
188     /* XXX: check this */
189     if (s->rxcr & 0x10) {
190         /* promiscuous: receive all */
191     } else {
192         if (!memcmp(buf,  broadcast_macaddr, 6)) {
193             /* broadcast address */
194             if (!(s->rxcr & 0x04))
195                 return size;
196         } else if (buf[0] & 0x01) {
197             /* multicast */
198             if (!(s->rxcr & 0x08))
199                 return size;
200             mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
201             if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
202                 return size;
203         } else if (s->mem[0] == buf[0] &&
204                    s->mem[2] == buf[1] &&
205                    s->mem[4] == buf[2] &&
206                    s->mem[6] == buf[3] &&
207                    s->mem[8] == buf[4] &&
208                    s->mem[10] == buf[5]) {
209             /* match */
210         } else {
211             return size;
212         }
213     }
214 
215 
216     /* if too small buffer, then expand it */
217     if (size < MIN_BUF_SIZE) {
218         memcpy(buf1, buf, size);
219         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
220         buf = buf1;
221         size = MIN_BUF_SIZE;
222     }
223 
224     index = s->curpag << 8;
225     if (index >= NE2000_PMEM_END) {
226         index = s->start;
227     }
228     /* 4 bytes for header */
229     total_len = size + 4;
230     /* address for next packet (4 bytes for CRC) */
231     next = index + ((total_len + 4 + 255) & ~0xff);
232     if (next >= s->stop)
233         next -= (s->stop - s->start);
234     /* prepare packet header */
235     p = s->mem + index;
236     s->rsr = ENRSR_RXOK; /* receive status */
237     /* XXX: check this */
238     if (buf[0] & 0x01)
239         s->rsr |= ENRSR_PHY;
240     p[0] = s->rsr;
241     p[1] = next >> 8;
242     p[2] = total_len;
243     p[3] = total_len >> 8;
244     index += 4;
245 
246     /* write packet data */
247     while (size > 0) {
248         if (index <= s->stop)
249             avail = s->stop - index;
250         else
251             break;
252         len = size;
253         if (len > avail)
254             len = avail;
255         memcpy(s->mem + index, buf, len);
256         buf += len;
257         index += len;
258         if (index == s->stop)
259             index = s->start;
260         size -= len;
261     }
262     s->curpag = next >> 8;
263 
264     /* now we can signal we have received something */
265     s->isr |= ENISR_RX;
266     ne2000_update_irq(s);
267 
268     return size_;
269 }
270 
271 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
272 {
273     NE2000State *s = opaque;
274     int offset, page, index;
275 
276     addr &= 0xf;
277     trace_ne2000_ioport_write(addr, val);
278     if (addr == E8390_CMD) {
279         /* control register */
280         s->cmd = val;
281         if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
282             s->isr &= ~ENISR_RESET;
283             /* test specific case: zero length transfer */
284             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
285                 s->rcnt == 0) {
286                 s->isr |= ENISR_RDC;
287                 ne2000_update_irq(s);
288             }
289             if (val & E8390_TRANS) {
290                 index = (s->tpsr << 8);
291                 /* XXX: next 2 lines are a hack to make netware 3.11 work */
292                 if (index >= NE2000_PMEM_END)
293                     index -= NE2000_PMEM_SIZE;
294                 /* fail safe: check range on the transmitted length  */
295                 if (index + s->tcnt <= NE2000_PMEM_END) {
296                     qemu_send_packet(qemu_get_queue(s->nic), s->mem + index,
297                                      s->tcnt);
298                 }
299                 /* signal end of transfer */
300                 s->tsr = ENTSR_PTX;
301                 s->isr |= ENISR_TX;
302                 s->cmd &= ~E8390_TRANS;
303                 ne2000_update_irq(s);
304             }
305         }
306     } else {
307         page = s->cmd >> 6;
308         offset = addr | (page << 4);
309         switch(offset) {
310         case EN0_STARTPG:
311             if (val << 8 <= NE2000_PMEM_END) {
312                 s->start = val << 8;
313             }
314             break;
315         case EN0_STOPPG:
316             if (val << 8 <= NE2000_PMEM_END) {
317                 s->stop = val << 8;
318             }
319             break;
320         case EN0_BOUNDARY:
321             if (val << 8 < NE2000_PMEM_END) {
322                 s->boundary = val;
323             }
324             break;
325         case EN0_IMR:
326             s->imr = val;
327             ne2000_update_irq(s);
328             break;
329         case EN0_TPSR:
330             s->tpsr = val;
331             break;
332         case EN0_TCNTLO:
333             s->tcnt = (s->tcnt & 0xff00) | val;
334             break;
335         case EN0_TCNTHI:
336             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
337             break;
338         case EN0_RSARLO:
339             s->rsar = (s->rsar & 0xff00) | val;
340             break;
341         case EN0_RSARHI:
342             s->rsar = (s->rsar & 0x00ff) | (val << 8);
343             break;
344         case EN0_RCNTLO:
345             s->rcnt = (s->rcnt & 0xff00) | val;
346             break;
347         case EN0_RCNTHI:
348             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
349             break;
350         case EN0_RXCR:
351             s->rxcr = val;
352             break;
353         case EN0_DCFG:
354             s->dcfg = val;
355             break;
356         case EN0_ISR:
357             s->isr &= ~(val & 0x7f);
358             ne2000_update_irq(s);
359             break;
360         case EN1_PHYS ... EN1_PHYS + 5:
361             s->phys[offset - EN1_PHYS] = val;
362             break;
363         case EN1_CURPAG:
364             if (val << 8 < NE2000_PMEM_END) {
365                 s->curpag = val;
366             }
367             break;
368         case EN1_MULT ... EN1_MULT + 7:
369             s->mult[offset - EN1_MULT] = val;
370             break;
371         }
372     }
373 }
374 
375 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
376 {
377     NE2000State *s = opaque;
378     int offset, page, ret;
379 
380     addr &= 0xf;
381     if (addr == E8390_CMD) {
382         ret = s->cmd;
383     } else {
384         page = s->cmd >> 6;
385         offset = addr | (page << 4);
386         switch(offset) {
387         case EN0_TSR:
388             ret = s->tsr;
389             break;
390         case EN0_BOUNDARY:
391             ret = s->boundary;
392             break;
393         case EN0_ISR:
394             ret = s->isr;
395             break;
396         case EN0_RSARLO:
397             ret = s->rsar & 0x00ff;
398             break;
399         case EN0_RSARHI:
400             ret = s->rsar >> 8;
401             break;
402         case EN1_PHYS ... EN1_PHYS + 5:
403             ret = s->phys[offset - EN1_PHYS];
404             break;
405         case EN1_CURPAG:
406             ret = s->curpag;
407             break;
408         case EN1_MULT ... EN1_MULT + 7:
409             ret = s->mult[offset - EN1_MULT];
410             break;
411         case EN0_RSR:
412             ret = s->rsr;
413             break;
414         case EN2_STARTPG:
415             ret = s->start >> 8;
416             break;
417         case EN2_STOPPG:
418             ret = s->stop >> 8;
419             break;
420         case EN0_RTL8029ID0:
421             ret = 0x50;
422             break;
423         case EN0_RTL8029ID1:
424             ret = 0x43;
425             break;
426         case EN3_CONFIG0:
427             ret = 0;		/* 10baseT media */
428             break;
429         case EN3_CONFIG2:
430             ret = 0x40;		/* 10baseT active */
431             break;
432         case EN3_CONFIG3:
433             ret = 0x40;		/* Full duplex */
434             break;
435         default:
436             ret = 0x00;
437             break;
438         }
439     }
440     trace_ne2000_ioport_read(addr, ret);
441     return ret;
442 }
443 
444 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
445                                      uint32_t val)
446 {
447     if (addr < 32 ||
448         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
449         s->mem[addr] = val;
450     }
451 }
452 
453 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
454                                      uint32_t val)
455 {
456     addr &= ~1; /* XXX: check exact behaviour if not even */
457     if (addr < 32 ||
458         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
459         *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
460     }
461 }
462 
463 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
464                                      uint32_t val)
465 {
466     addr &= ~1; /* XXX: check exact behaviour if not even */
467     if (addr < 32
468         || (addr >= NE2000_PMEM_START
469             && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
470         stl_le_p(s->mem + addr, val);
471     }
472 }
473 
474 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
475 {
476     if (addr < 32 ||
477         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
478         return s->mem[addr];
479     } else {
480         return 0xff;
481     }
482 }
483 
484 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
485 {
486     addr &= ~1; /* XXX: check exact behaviour if not even */
487     if (addr < 32 ||
488         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
489         return le16_to_cpu(*(uint16_t *)(s->mem + addr));
490     } else {
491         return 0xffff;
492     }
493 }
494 
495 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
496 {
497     addr &= ~1; /* XXX: check exact behaviour if not even */
498     if (addr < 32
499         || (addr >= NE2000_PMEM_START
500             && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
501         return ldl_le_p(s->mem + addr);
502     } else {
503         return 0xffffffff;
504     }
505 }
506 
507 static inline void ne2000_dma_update(NE2000State *s, int len)
508 {
509     s->rsar += len;
510     /* wrap */
511     /* XXX: check what to do if rsar > stop */
512     if (s->rsar == s->stop)
513         s->rsar = s->start;
514 
515     if (s->rcnt <= len) {
516         s->rcnt = 0;
517         /* signal end of transfer */
518         s->isr |= ENISR_RDC;
519         ne2000_update_irq(s);
520     } else {
521         s->rcnt -= len;
522     }
523 }
524 
525 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
526 {
527     NE2000State *s = opaque;
528 
529 #ifdef DEBUG_NE2000
530     printf("NE2000: asic write val=0x%04x\n", val);
531 #endif
532     if (s->rcnt == 0)
533         return;
534     if (s->dcfg & 0x01) {
535         /* 16 bit access */
536         ne2000_mem_writew(s, s->rsar, val);
537         ne2000_dma_update(s, 2);
538     } else {
539         /* 8 bit access */
540         ne2000_mem_writeb(s, s->rsar, val);
541         ne2000_dma_update(s, 1);
542     }
543 }
544 
545 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
546 {
547     NE2000State *s = opaque;
548     int ret;
549 
550     if (s->dcfg & 0x01) {
551         /* 16 bit access */
552         ret = ne2000_mem_readw(s, s->rsar);
553         ne2000_dma_update(s, 2);
554     } else {
555         /* 8 bit access */
556         ret = ne2000_mem_readb(s, s->rsar);
557         ne2000_dma_update(s, 1);
558     }
559 #ifdef DEBUG_NE2000
560     printf("NE2000: asic read val=0x%04x\n", ret);
561 #endif
562     return ret;
563 }
564 
565 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
566 {
567     NE2000State *s = opaque;
568 
569 #ifdef DEBUG_NE2000
570     printf("NE2000: asic writel val=0x%04x\n", val);
571 #endif
572     if (s->rcnt == 0)
573         return;
574     /* 32 bit access */
575     ne2000_mem_writel(s, s->rsar, val);
576     ne2000_dma_update(s, 4);
577 }
578 
579 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
580 {
581     NE2000State *s = opaque;
582     int ret;
583 
584     /* 32 bit access */
585     ret = ne2000_mem_readl(s, s->rsar);
586     ne2000_dma_update(s, 4);
587 #ifdef DEBUG_NE2000
588     printf("NE2000: asic readl val=0x%04x\n", ret);
589 #endif
590     return ret;
591 }
592 
593 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
594 {
595     /* nothing to do (end of reset pulse) */
596 }
597 
598 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
599 {
600     NE2000State *s = opaque;
601     ne2000_reset(s);
602     return 0;
603 }
604 
605 static int ne2000_post_load(void* opaque, int version_id)
606 {
607     NE2000State* s = opaque;
608 
609     if (version_id < 2) {
610         s->rxcr = 0x0c;
611     }
612     return 0;
613 }
614 
615 const VMStateDescription vmstate_ne2000 = {
616     .name = "ne2000",
617     .version_id = 2,
618     .minimum_version_id = 0,
619     .post_load = ne2000_post_load,
620     .fields = (VMStateField[]) {
621         VMSTATE_UINT8_V(rxcr, NE2000State, 2),
622         VMSTATE_UINT8(cmd, NE2000State),
623         VMSTATE_UINT32(start, NE2000State),
624         VMSTATE_UINT32(stop, NE2000State),
625         VMSTATE_UINT8(boundary, NE2000State),
626         VMSTATE_UINT8(tsr, NE2000State),
627         VMSTATE_UINT8(tpsr, NE2000State),
628         VMSTATE_UINT16(tcnt, NE2000State),
629         VMSTATE_UINT16(rcnt, NE2000State),
630         VMSTATE_UINT32(rsar, NE2000State),
631         VMSTATE_UINT8(rsr, NE2000State),
632         VMSTATE_UINT8(isr, NE2000State),
633         VMSTATE_UINT8(dcfg, NE2000State),
634         VMSTATE_UINT8(imr, NE2000State),
635         VMSTATE_BUFFER(phys, NE2000State),
636         VMSTATE_UINT8(curpag, NE2000State),
637         VMSTATE_BUFFER(mult, NE2000State),
638         VMSTATE_UNUSED(4), /* was irq */
639         VMSTATE_BUFFER(mem, NE2000State),
640         VMSTATE_END_OF_LIST()
641     }
642 };
643 
644 static uint64_t ne2000_read(void *opaque, hwaddr addr,
645                             unsigned size)
646 {
647     NE2000State *s = opaque;
648     uint64_t val;
649 
650     if (addr < 0x10 && size == 1) {
651         val = ne2000_ioport_read(s, addr);
652     } else if (addr == 0x10) {
653         if (size <= 2) {
654             val = ne2000_asic_ioport_read(s, addr);
655         } else {
656             val = ne2000_asic_ioport_readl(s, addr);
657         }
658     } else if (addr == 0x1f && size == 1) {
659         val = ne2000_reset_ioport_read(s, addr);
660     } else {
661         val = ((uint64_t)1 << (size * 8)) - 1;
662     }
663     trace_ne2000_read(addr, val);
664 
665     return val;
666 }
667 
668 static void ne2000_write(void *opaque, hwaddr addr,
669                          uint64_t data, unsigned size)
670 {
671     NE2000State *s = opaque;
672 
673     trace_ne2000_write(addr, data);
674     if (addr < 0x10 && size == 1) {
675         ne2000_ioport_write(s, addr, data);
676     } else if (addr == 0x10) {
677         if (size <= 2) {
678             ne2000_asic_ioport_write(s, addr, data);
679         } else {
680             ne2000_asic_ioport_writel(s, addr, data);
681         }
682     } else if (addr == 0x1f && size == 1) {
683         ne2000_reset_ioport_write(s, addr, data);
684     }
685 }
686 
687 static const MemoryRegionOps ne2000_ops = {
688     .read = ne2000_read,
689     .write = ne2000_write,
690     .endianness = DEVICE_LITTLE_ENDIAN,
691 };
692 
693 /***********************************************************/
694 /* PCI NE2000 definitions */
695 
696 void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size)
697 {
698     memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size);
699 }
700