1 /* 2 * QEMU NE2000 emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "net/eth.h" 26 #include "ne2000.h" 27 #include "sysemu/sysemu.h" 28 #include "trace.h" 29 30 /* debug NE2000 card */ 31 //#define DEBUG_NE2000 32 33 #define MAX_ETH_FRAME_SIZE 1514 34 35 #define E8390_CMD 0x00 /* The command register (for all pages) */ 36 /* Page 0 register offsets. */ 37 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ 38 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ 39 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ 40 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ 41 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ 42 #define EN0_TSR 0x04 /* Transmit status reg RD */ 43 #define EN0_TPSR 0x04 /* Transmit starting page WR */ 44 #define EN0_NCR 0x05 /* Number of collision reg RD */ 45 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ 46 #define EN0_FIFO 0x06 /* FIFO RD */ 47 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ 48 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ 49 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ 50 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ 51 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ 52 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ 53 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ 54 #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ 55 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ 56 #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ 57 #define EN0_RSR 0x0c /* rx status reg RD */ 58 #define EN0_RXCR 0x0c /* RX configuration reg WR */ 59 #define EN0_TXCR 0x0d /* TX configuration reg WR */ 60 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ 61 #define EN0_DCFG 0x0e /* Data configuration reg WR */ 62 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ 63 #define EN0_IMR 0x0f /* Interrupt mask reg WR */ 64 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ 65 66 #define EN1_PHYS 0x11 67 #define EN1_CURPAG 0x17 68 #define EN1_MULT 0x18 69 70 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ 71 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ 72 73 #define EN3_CONFIG0 0x33 74 #define EN3_CONFIG1 0x34 75 #define EN3_CONFIG2 0x35 76 #define EN3_CONFIG3 0x36 77 78 /* Register accessed at EN_CMD, the 8390 base addr. */ 79 #define E8390_STOP 0x01 /* Stop and reset the chip */ 80 #define E8390_START 0x02 /* Start the chip, clear reset */ 81 #define E8390_TRANS 0x04 /* Transmit a frame */ 82 #define E8390_RREAD 0x08 /* Remote read */ 83 #define E8390_RWRITE 0x10 /* Remote write */ 84 #define E8390_NODMA 0x20 /* Remote DMA */ 85 #define E8390_PAGE0 0x00 /* Select page chip registers */ 86 #define E8390_PAGE1 0x40 /* using the two high-order bits */ 87 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ 88 89 /* Bits in EN0_ISR - Interrupt status register */ 90 #define ENISR_RX 0x01 /* Receiver, no error */ 91 #define ENISR_TX 0x02 /* Transmitter, no error */ 92 #define ENISR_RX_ERR 0x04 /* Receiver, with error */ 93 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ 94 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ 95 #define ENISR_COUNTERS 0x20 /* Counters need emptying */ 96 #define ENISR_RDC 0x40 /* remote dma complete */ 97 #define ENISR_RESET 0x80 /* Reset completed */ 98 #define ENISR_ALL 0x3f /* Interrupts we will enable */ 99 100 /* Bits in received packet status byte and EN0_RSR*/ 101 #define ENRSR_RXOK 0x01 /* Received a good packet */ 102 #define ENRSR_CRC 0x02 /* CRC error */ 103 #define ENRSR_FAE 0x04 /* frame alignment error */ 104 #define ENRSR_FO 0x08 /* FIFO overrun */ 105 #define ENRSR_MPA 0x10 /* missed pkt */ 106 #define ENRSR_PHY 0x20 /* physical/multicast address */ 107 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ 108 #define ENRSR_DEF 0x80 /* deferring */ 109 110 /* Transmitted packet status, EN0_TSR. */ 111 #define ENTSR_PTX 0x01 /* Packet transmitted without error */ 112 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ 113 #define ENTSR_COL 0x04 /* The transmit collided at least once. */ 114 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ 115 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ 116 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ 117 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ 118 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ 119 120 void ne2000_reset(NE2000State *s) 121 { 122 int i; 123 124 s->isr = ENISR_RESET; 125 memcpy(s->mem, &s->c.macaddr, 6); 126 s->mem[14] = 0x57; 127 s->mem[15] = 0x57; 128 129 /* duplicate prom data */ 130 for(i = 15;i >= 0; i--) { 131 s->mem[2 * i] = s->mem[i]; 132 s->mem[2 * i + 1] = s->mem[i]; 133 } 134 } 135 136 static void ne2000_update_irq(NE2000State *s) 137 { 138 int isr; 139 isr = (s->isr & s->imr) & 0x7f; 140 #if defined(DEBUG_NE2000) 141 printf("NE2000: Set IRQ to %d (%02x %02x)\n", 142 isr ? 1 : 0, s->isr, s->imr); 143 #endif 144 qemu_set_irq(s->irq, (isr != 0)); 145 } 146 147 static int ne2000_buffer_full(NE2000State *s) 148 { 149 int avail, index, boundary; 150 151 if (s->stop <= s->start) { 152 return 1; 153 } 154 155 index = s->curpag << 8; 156 boundary = s->boundary << 8; 157 if (index < boundary) 158 avail = boundary - index; 159 else 160 avail = (s->stop - s->start) - (index - boundary); 161 if (avail < (MAX_ETH_FRAME_SIZE + 4)) 162 return 1; 163 return 0; 164 } 165 166 #define MIN_BUF_SIZE 60 167 168 ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_) 169 { 170 NE2000State *s = qemu_get_nic_opaque(nc); 171 size_t size = size_; 172 uint8_t *p; 173 unsigned int total_len, next, avail, len, index, mcast_idx; 174 uint8_t buf1[60]; 175 static const uint8_t broadcast_macaddr[6] = 176 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 177 178 #if defined(DEBUG_NE2000) 179 printf("NE2000: received len=%zu\n", size); 180 #endif 181 182 if (s->cmd & E8390_STOP || ne2000_buffer_full(s)) 183 return -1; 184 185 /* XXX: check this */ 186 if (s->rxcr & 0x10) { 187 /* promiscuous: receive all */ 188 } else { 189 if (!memcmp(buf, broadcast_macaddr, 6)) { 190 /* broadcast address */ 191 if (!(s->rxcr & 0x04)) 192 return size; 193 } else if (buf[0] & 0x01) { 194 /* multicast */ 195 if (!(s->rxcr & 0x08)) 196 return size; 197 mcast_idx = net_crc32(buf, ETH_ALEN) >> 26; 198 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) 199 return size; 200 } else if (s->mem[0] == buf[0] && 201 s->mem[2] == buf[1] && 202 s->mem[4] == buf[2] && 203 s->mem[6] == buf[3] && 204 s->mem[8] == buf[4] && 205 s->mem[10] == buf[5]) { 206 /* match */ 207 } else { 208 return size; 209 } 210 } 211 212 213 /* if too small buffer, then expand it */ 214 if (size < MIN_BUF_SIZE) { 215 memcpy(buf1, buf, size); 216 memset(buf1 + size, 0, MIN_BUF_SIZE - size); 217 buf = buf1; 218 size = MIN_BUF_SIZE; 219 } 220 221 index = s->curpag << 8; 222 if (index >= NE2000_PMEM_END) { 223 index = s->start; 224 } 225 /* 4 bytes for header */ 226 total_len = size + 4; 227 /* address for next packet (4 bytes for CRC) */ 228 next = index + ((total_len + 4 + 255) & ~0xff); 229 if (next >= s->stop) 230 next -= (s->stop - s->start); 231 /* prepare packet header */ 232 p = s->mem + index; 233 s->rsr = ENRSR_RXOK; /* receive status */ 234 /* XXX: check this */ 235 if (buf[0] & 0x01) 236 s->rsr |= ENRSR_PHY; 237 p[0] = s->rsr; 238 p[1] = next >> 8; 239 p[2] = total_len; 240 p[3] = total_len >> 8; 241 index += 4; 242 243 /* write packet data */ 244 while (size > 0) { 245 if (index <= s->stop) 246 avail = s->stop - index; 247 else 248 break; 249 len = size; 250 if (len > avail) 251 len = avail; 252 memcpy(s->mem + index, buf, len); 253 buf += len; 254 index += len; 255 if (index == s->stop) 256 index = s->start; 257 size -= len; 258 } 259 s->curpag = next >> 8; 260 261 /* now we can signal we have received something */ 262 s->isr |= ENISR_RX; 263 ne2000_update_irq(s); 264 265 return size_; 266 } 267 268 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) 269 { 270 NE2000State *s = opaque; 271 int offset, page, index; 272 273 addr &= 0xf; 274 trace_ne2000_ioport_write(addr, val); 275 if (addr == E8390_CMD) { 276 /* control register */ 277 s->cmd = val; 278 if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ 279 s->isr &= ~ENISR_RESET; 280 /* test specific case: zero length transfer */ 281 if ((val & (E8390_RREAD | E8390_RWRITE)) && 282 s->rcnt == 0) { 283 s->isr |= ENISR_RDC; 284 ne2000_update_irq(s); 285 } 286 if (val & E8390_TRANS) { 287 index = (s->tpsr << 8); 288 /* XXX: next 2 lines are a hack to make netware 3.11 work */ 289 if (index >= NE2000_PMEM_END) 290 index -= NE2000_PMEM_SIZE; 291 /* fail safe: check range on the transmitted length */ 292 if (index + s->tcnt <= NE2000_PMEM_END) { 293 qemu_send_packet(qemu_get_queue(s->nic), s->mem + index, 294 s->tcnt); 295 } 296 /* signal end of transfer */ 297 s->tsr = ENTSR_PTX; 298 s->isr |= ENISR_TX; 299 s->cmd &= ~E8390_TRANS; 300 ne2000_update_irq(s); 301 } 302 } 303 } else { 304 page = s->cmd >> 6; 305 offset = addr | (page << 4); 306 switch(offset) { 307 case EN0_STARTPG: 308 if (val << 8 <= NE2000_PMEM_END) { 309 s->start = val << 8; 310 } 311 break; 312 case EN0_STOPPG: 313 if (val << 8 <= NE2000_PMEM_END) { 314 s->stop = val << 8; 315 } 316 break; 317 case EN0_BOUNDARY: 318 if (val << 8 < NE2000_PMEM_END) { 319 s->boundary = val; 320 } 321 break; 322 case EN0_IMR: 323 s->imr = val; 324 ne2000_update_irq(s); 325 break; 326 case EN0_TPSR: 327 s->tpsr = val; 328 break; 329 case EN0_TCNTLO: 330 s->tcnt = (s->tcnt & 0xff00) | val; 331 break; 332 case EN0_TCNTHI: 333 s->tcnt = (s->tcnt & 0x00ff) | (val << 8); 334 break; 335 case EN0_RSARLO: 336 s->rsar = (s->rsar & 0xff00) | val; 337 break; 338 case EN0_RSARHI: 339 s->rsar = (s->rsar & 0x00ff) | (val << 8); 340 break; 341 case EN0_RCNTLO: 342 s->rcnt = (s->rcnt & 0xff00) | val; 343 break; 344 case EN0_RCNTHI: 345 s->rcnt = (s->rcnt & 0x00ff) | (val << 8); 346 break; 347 case EN0_RXCR: 348 s->rxcr = val; 349 break; 350 case EN0_DCFG: 351 s->dcfg = val; 352 break; 353 case EN0_ISR: 354 s->isr &= ~(val & 0x7f); 355 ne2000_update_irq(s); 356 break; 357 case EN1_PHYS ... EN1_PHYS + 5: 358 s->phys[offset - EN1_PHYS] = val; 359 break; 360 case EN1_CURPAG: 361 if (val << 8 < NE2000_PMEM_END) { 362 s->curpag = val; 363 } 364 break; 365 case EN1_MULT ... EN1_MULT + 7: 366 s->mult[offset - EN1_MULT] = val; 367 break; 368 } 369 } 370 } 371 372 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) 373 { 374 NE2000State *s = opaque; 375 int offset, page, ret; 376 377 addr &= 0xf; 378 if (addr == E8390_CMD) { 379 ret = s->cmd; 380 } else { 381 page = s->cmd >> 6; 382 offset = addr | (page << 4); 383 switch(offset) { 384 case EN0_TSR: 385 ret = s->tsr; 386 break; 387 case EN0_BOUNDARY: 388 ret = s->boundary; 389 break; 390 case EN0_ISR: 391 ret = s->isr; 392 break; 393 case EN0_RSARLO: 394 ret = s->rsar & 0x00ff; 395 break; 396 case EN0_RSARHI: 397 ret = s->rsar >> 8; 398 break; 399 case EN1_PHYS ... EN1_PHYS + 5: 400 ret = s->phys[offset - EN1_PHYS]; 401 break; 402 case EN1_CURPAG: 403 ret = s->curpag; 404 break; 405 case EN1_MULT ... EN1_MULT + 7: 406 ret = s->mult[offset - EN1_MULT]; 407 break; 408 case EN0_RSR: 409 ret = s->rsr; 410 break; 411 case EN2_STARTPG: 412 ret = s->start >> 8; 413 break; 414 case EN2_STOPPG: 415 ret = s->stop >> 8; 416 break; 417 case EN0_RTL8029ID0: 418 ret = 0x50; 419 break; 420 case EN0_RTL8029ID1: 421 ret = 0x43; 422 break; 423 case EN3_CONFIG0: 424 ret = 0; /* 10baseT media */ 425 break; 426 case EN3_CONFIG2: 427 ret = 0x40; /* 10baseT active */ 428 break; 429 case EN3_CONFIG3: 430 ret = 0x40; /* Full duplex */ 431 break; 432 default: 433 ret = 0x00; 434 break; 435 } 436 } 437 trace_ne2000_ioport_read(addr, ret); 438 return ret; 439 } 440 441 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, 442 uint32_t val) 443 { 444 if (addr < 32 || 445 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 446 s->mem[addr] = val; 447 } 448 } 449 450 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, 451 uint32_t val) 452 { 453 addr &= ~1; /* XXX: check exact behaviour if not even */ 454 if (addr < 32 || 455 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 456 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val); 457 } 458 } 459 460 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, 461 uint32_t val) 462 { 463 addr &= ~1; /* XXX: check exact behaviour if not even */ 464 if (addr < 32 465 || (addr >= NE2000_PMEM_START 466 && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) { 467 stl_le_p(s->mem + addr, val); 468 } 469 } 470 471 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) 472 { 473 if (addr < 32 || 474 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 475 return s->mem[addr]; 476 } else { 477 return 0xff; 478 } 479 } 480 481 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) 482 { 483 addr &= ~1; /* XXX: check exact behaviour if not even */ 484 if (addr < 32 || 485 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { 486 return le16_to_cpu(*(uint16_t *)(s->mem + addr)); 487 } else { 488 return 0xffff; 489 } 490 } 491 492 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) 493 { 494 addr &= ~1; /* XXX: check exact behaviour if not even */ 495 if (addr < 32 496 || (addr >= NE2000_PMEM_START 497 && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) { 498 return ldl_le_p(s->mem + addr); 499 } else { 500 return 0xffffffff; 501 } 502 } 503 504 static inline void ne2000_dma_update(NE2000State *s, int len) 505 { 506 s->rsar += len; 507 /* wrap */ 508 /* XXX: check what to do if rsar > stop */ 509 if (s->rsar == s->stop) 510 s->rsar = s->start; 511 512 if (s->rcnt <= len) { 513 s->rcnt = 0; 514 /* signal end of transfer */ 515 s->isr |= ENISR_RDC; 516 ne2000_update_irq(s); 517 } else { 518 s->rcnt -= len; 519 } 520 } 521 522 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) 523 { 524 NE2000State *s = opaque; 525 526 #ifdef DEBUG_NE2000 527 printf("NE2000: asic write val=0x%04x\n", val); 528 #endif 529 if (s->rcnt == 0) 530 return; 531 if (s->dcfg & 0x01) { 532 /* 16 bit access */ 533 ne2000_mem_writew(s, s->rsar, val); 534 ne2000_dma_update(s, 2); 535 } else { 536 /* 8 bit access */ 537 ne2000_mem_writeb(s, s->rsar, val); 538 ne2000_dma_update(s, 1); 539 } 540 } 541 542 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) 543 { 544 NE2000State *s = opaque; 545 int ret; 546 547 if (s->dcfg & 0x01) { 548 /* 16 bit access */ 549 ret = ne2000_mem_readw(s, s->rsar); 550 ne2000_dma_update(s, 2); 551 } else { 552 /* 8 bit access */ 553 ret = ne2000_mem_readb(s, s->rsar); 554 ne2000_dma_update(s, 1); 555 } 556 #ifdef DEBUG_NE2000 557 printf("NE2000: asic read val=0x%04x\n", ret); 558 #endif 559 return ret; 560 } 561 562 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) 563 { 564 NE2000State *s = opaque; 565 566 #ifdef DEBUG_NE2000 567 printf("NE2000: asic writel val=0x%04x\n", val); 568 #endif 569 if (s->rcnt == 0) 570 return; 571 /* 32 bit access */ 572 ne2000_mem_writel(s, s->rsar, val); 573 ne2000_dma_update(s, 4); 574 } 575 576 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) 577 { 578 NE2000State *s = opaque; 579 int ret; 580 581 /* 32 bit access */ 582 ret = ne2000_mem_readl(s, s->rsar); 583 ne2000_dma_update(s, 4); 584 #ifdef DEBUG_NE2000 585 printf("NE2000: asic readl val=0x%04x\n", ret); 586 #endif 587 return ret; 588 } 589 590 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) 591 { 592 /* nothing to do (end of reset pulse) */ 593 } 594 595 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) 596 { 597 NE2000State *s = opaque; 598 ne2000_reset(s); 599 return 0; 600 } 601 602 static int ne2000_post_load(void* opaque, int version_id) 603 { 604 NE2000State* s = opaque; 605 606 if (version_id < 2) { 607 s->rxcr = 0x0c; 608 } 609 return 0; 610 } 611 612 const VMStateDescription vmstate_ne2000 = { 613 .name = "ne2000", 614 .version_id = 2, 615 .minimum_version_id = 0, 616 .post_load = ne2000_post_load, 617 .fields = (VMStateField[]) { 618 VMSTATE_UINT8_V(rxcr, NE2000State, 2), 619 VMSTATE_UINT8(cmd, NE2000State), 620 VMSTATE_UINT32(start, NE2000State), 621 VMSTATE_UINT32(stop, NE2000State), 622 VMSTATE_UINT8(boundary, NE2000State), 623 VMSTATE_UINT8(tsr, NE2000State), 624 VMSTATE_UINT8(tpsr, NE2000State), 625 VMSTATE_UINT16(tcnt, NE2000State), 626 VMSTATE_UINT16(rcnt, NE2000State), 627 VMSTATE_UINT32(rsar, NE2000State), 628 VMSTATE_UINT8(rsr, NE2000State), 629 VMSTATE_UINT8(isr, NE2000State), 630 VMSTATE_UINT8(dcfg, NE2000State), 631 VMSTATE_UINT8(imr, NE2000State), 632 VMSTATE_BUFFER(phys, NE2000State), 633 VMSTATE_UINT8(curpag, NE2000State), 634 VMSTATE_BUFFER(mult, NE2000State), 635 VMSTATE_UNUSED(4), /* was irq */ 636 VMSTATE_BUFFER(mem, NE2000State), 637 VMSTATE_END_OF_LIST() 638 } 639 }; 640 641 static uint64_t ne2000_read(void *opaque, hwaddr addr, 642 unsigned size) 643 { 644 NE2000State *s = opaque; 645 uint64_t val; 646 647 if (addr < 0x10 && size == 1) { 648 val = ne2000_ioport_read(s, addr); 649 } else if (addr == 0x10) { 650 if (size <= 2) { 651 val = ne2000_asic_ioport_read(s, addr); 652 } else { 653 val = ne2000_asic_ioport_readl(s, addr); 654 } 655 } else if (addr == 0x1f && size == 1) { 656 val = ne2000_reset_ioport_read(s, addr); 657 } else { 658 val = ((uint64_t)1 << (size * 8)) - 1; 659 } 660 trace_ne2000_read(addr, val); 661 662 return val; 663 } 664 665 static void ne2000_write(void *opaque, hwaddr addr, 666 uint64_t data, unsigned size) 667 { 668 NE2000State *s = opaque; 669 670 trace_ne2000_write(addr, data); 671 if (addr < 0x10 && size == 1) { 672 ne2000_ioport_write(s, addr, data); 673 } else if (addr == 0x10) { 674 if (size <= 2) { 675 ne2000_asic_ioport_write(s, addr, data); 676 } else { 677 ne2000_asic_ioport_writel(s, addr, data); 678 } 679 } else if (addr == 0x1f && size == 1) { 680 ne2000_reset_ioport_write(s, addr, data); 681 } 682 } 683 684 static const MemoryRegionOps ne2000_ops = { 685 .read = ne2000_read, 686 .write = ne2000_write, 687 .endianness = DEVICE_LITTLE_ENDIAN, 688 }; 689 690 /***********************************************************/ 691 /* PCI NE2000 definitions */ 692 693 void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size) 694 { 695 memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size); 696 } 697