1 #include "qemu/osdep.h" 2 #include "hw/irq.h" 3 #include "hw/qdev-properties.h" 4 #include "net/net.h" 5 #include "qemu/module.h" 6 #include "trace.h" 7 #include "hw/sysbus.h" 8 #include "migration/vmstate.h" 9 10 /* MIPSnet register offsets */ 11 12 #define MIPSNET_DEV_ID 0x00 13 #define MIPSNET_BUSY 0x08 14 #define MIPSNET_RX_DATA_COUNT 0x0c 15 #define MIPSNET_TX_DATA_COUNT 0x10 16 #define MIPSNET_INT_CTL 0x14 17 # define MIPSNET_INTCTL_TXDONE 0x00000001 18 # define MIPSNET_INTCTL_RXDONE 0x00000002 19 # define MIPSNET_INTCTL_TESTBIT 0x80000000 20 #define MIPSNET_INTERRUPT_INFO 0x18 21 #define MIPSNET_RX_DATA_BUFFER 0x1c 22 #define MIPSNET_TX_DATA_BUFFER 0x20 23 24 #define MAX_ETH_FRAME_SIZE 1514 25 26 #define TYPE_MIPS_NET "mipsnet" 27 #define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET) 28 29 typedef struct MIPSnetState { 30 SysBusDevice parent_obj; 31 32 uint32_t busy; 33 uint32_t rx_count; 34 uint32_t rx_read; 35 uint32_t tx_count; 36 uint32_t tx_written; 37 uint32_t intctl; 38 uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; 39 uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; 40 MemoryRegion io; 41 qemu_irq irq; 42 NICState *nic; 43 NICConf conf; 44 } MIPSnetState; 45 46 static void mipsnet_reset(MIPSnetState *s) 47 { 48 s->busy = 1; 49 s->rx_count = 0; 50 s->rx_read = 0; 51 s->tx_count = 0; 52 s->tx_written = 0; 53 s->intctl = 0; 54 memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE); 55 memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE); 56 } 57 58 static void mipsnet_update_irq(MIPSnetState *s) 59 { 60 int isr = !!s->intctl; 61 trace_mipsnet_irq(isr, s->intctl); 62 qemu_set_irq(s->irq, isr); 63 } 64 65 static int mipsnet_buffer_full(MIPSnetState *s) 66 { 67 if (s->rx_count >= MAX_ETH_FRAME_SIZE) 68 return 1; 69 return 0; 70 } 71 72 static int mipsnet_can_receive(NetClientState *nc) 73 { 74 MIPSnetState *s = qemu_get_nic_opaque(nc); 75 76 if (s->busy) 77 return 0; 78 return !mipsnet_buffer_full(s); 79 } 80 81 static ssize_t mipsnet_receive(NetClientState *nc, const uint8_t *buf, size_t size) 82 { 83 MIPSnetState *s = qemu_get_nic_opaque(nc); 84 85 trace_mipsnet_receive(size); 86 if (!mipsnet_can_receive(nc)) 87 return 0; 88 89 if (size >= sizeof(s->rx_buffer)) { 90 return 0; 91 } 92 s->busy = 1; 93 94 /* Just accept everything. */ 95 96 /* Write packet data. */ 97 memcpy(s->rx_buffer, buf, size); 98 99 s->rx_count = size; 100 s->rx_read = 0; 101 102 /* Now we can signal we have received something. */ 103 s->intctl |= MIPSNET_INTCTL_RXDONE; 104 mipsnet_update_irq(s); 105 106 return size; 107 } 108 109 static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr, 110 unsigned int size) 111 { 112 MIPSnetState *s = opaque; 113 int ret = 0; 114 115 addr &= 0x3f; 116 switch (addr) { 117 case MIPSNET_DEV_ID: 118 ret = be32_to_cpu(0x4d495053); /* MIPS */ 119 break; 120 case MIPSNET_DEV_ID + 4: 121 ret = be32_to_cpu(0x4e455430); /* NET0 */ 122 break; 123 case MIPSNET_BUSY: 124 ret = s->busy; 125 break; 126 case MIPSNET_RX_DATA_COUNT: 127 ret = s->rx_count; 128 break; 129 case MIPSNET_TX_DATA_COUNT: 130 ret = s->tx_count; 131 break; 132 case MIPSNET_INT_CTL: 133 ret = s->intctl; 134 s->intctl &= ~MIPSNET_INTCTL_TESTBIT; 135 break; 136 case MIPSNET_INTERRUPT_INFO: 137 /* XXX: This seems to be a per-VPE interrupt number. */ 138 ret = 0; 139 break; 140 case MIPSNET_RX_DATA_BUFFER: 141 if (s->rx_count) { 142 s->rx_count--; 143 ret = s->rx_buffer[s->rx_read++]; 144 if (mipsnet_can_receive(s->nic->ncs)) { 145 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 146 } 147 } 148 break; 149 /* Reads as zero. */ 150 case MIPSNET_TX_DATA_BUFFER: 151 default: 152 break; 153 } 154 trace_mipsnet_read(addr, ret); 155 return ret; 156 } 157 158 static void mipsnet_ioport_write(void *opaque, hwaddr addr, 159 uint64_t val, unsigned int size) 160 { 161 MIPSnetState *s = opaque; 162 163 addr &= 0x3f; 164 trace_mipsnet_write(addr, val); 165 switch (addr) { 166 case MIPSNET_TX_DATA_COUNT: 167 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; 168 s->tx_written = 0; 169 break; 170 case MIPSNET_INT_CTL: 171 if (val & MIPSNET_INTCTL_TXDONE) { 172 s->intctl &= ~MIPSNET_INTCTL_TXDONE; 173 } else if (val & MIPSNET_INTCTL_RXDONE) { 174 s->intctl &= ~MIPSNET_INTCTL_RXDONE; 175 } else if (val & MIPSNET_INTCTL_TESTBIT) { 176 mipsnet_reset(s); 177 s->intctl |= MIPSNET_INTCTL_TESTBIT; 178 } else if (!val) { 179 /* ACK testbit interrupt, flag was cleared on read. */ 180 } 181 s->busy = !!s->intctl; 182 mipsnet_update_irq(s); 183 if (mipsnet_can_receive(s->nic->ncs)) { 184 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 185 } 186 break; 187 case MIPSNET_TX_DATA_BUFFER: 188 s->tx_buffer[s->tx_written++] = val; 189 if ((s->tx_written >= MAX_ETH_FRAME_SIZE) 190 || (s->tx_written == s->tx_count)) { 191 /* Send buffer. */ 192 trace_mipsnet_send(s->tx_written); 193 qemu_send_packet(qemu_get_queue(s->nic), 194 s->tx_buffer, s->tx_written); 195 s->tx_count = s->tx_written = 0; 196 s->intctl |= MIPSNET_INTCTL_TXDONE; 197 s->busy = 1; 198 mipsnet_update_irq(s); 199 } 200 break; 201 /* Read-only registers */ 202 case MIPSNET_DEV_ID: 203 case MIPSNET_BUSY: 204 case MIPSNET_RX_DATA_COUNT: 205 case MIPSNET_INTERRUPT_INFO: 206 case MIPSNET_RX_DATA_BUFFER: 207 default: 208 break; 209 } 210 } 211 212 static const VMStateDescription vmstate_mipsnet = { 213 .name = "mipsnet", 214 .version_id = 0, 215 .minimum_version_id = 0, 216 .fields = (VMStateField[]) { 217 VMSTATE_UINT32(busy, MIPSnetState), 218 VMSTATE_UINT32(rx_count, MIPSnetState), 219 VMSTATE_UINT32(rx_read, MIPSnetState), 220 VMSTATE_UINT32(tx_count, MIPSnetState), 221 VMSTATE_UINT32(tx_written, MIPSnetState), 222 VMSTATE_UINT32(intctl, MIPSnetState), 223 VMSTATE_BUFFER(rx_buffer, MIPSnetState), 224 VMSTATE_BUFFER(tx_buffer, MIPSnetState), 225 VMSTATE_END_OF_LIST() 226 } 227 }; 228 229 static NetClientInfo net_mipsnet_info = { 230 .type = NET_CLIENT_DRIVER_NIC, 231 .size = sizeof(NICState), 232 .receive = mipsnet_receive, 233 }; 234 235 static const MemoryRegionOps mipsnet_ioport_ops = { 236 .read = mipsnet_ioport_read, 237 .write = mipsnet_ioport_write, 238 .impl.min_access_size = 1, 239 .impl.max_access_size = 4, 240 }; 241 242 static void mipsnet_realize(DeviceState *dev, Error **errp) 243 { 244 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 245 MIPSnetState *s = MIPS_NET(dev); 246 247 memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s, 248 "mipsnet-io", 36); 249 sysbus_init_mmio(sbd, &s->io); 250 sysbus_init_irq(sbd, &s->irq); 251 252 s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf, 253 object_get_typename(OBJECT(dev)), dev->id, s); 254 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 255 } 256 257 static void mipsnet_sysbus_reset(DeviceState *dev) 258 { 259 MIPSnetState *s = MIPS_NET(dev); 260 mipsnet_reset(s); 261 } 262 263 static Property mipsnet_properties[] = { 264 DEFINE_NIC_PROPERTIES(MIPSnetState, conf), 265 DEFINE_PROP_END_OF_LIST(), 266 }; 267 268 static void mipsnet_class_init(ObjectClass *klass, void *data) 269 { 270 DeviceClass *dc = DEVICE_CLASS(klass); 271 272 dc->realize = mipsnet_realize; 273 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 274 dc->desc = "MIPS Simulator network device"; 275 dc->reset = mipsnet_sysbus_reset; 276 dc->vmsd = &vmstate_mipsnet; 277 dc->props = mipsnet_properties; 278 } 279 280 static const TypeInfo mipsnet_info = { 281 .name = TYPE_MIPS_NET, 282 .parent = TYPE_SYS_BUS_DEVICE, 283 .instance_size = sizeof(MIPSnetState), 284 .class_init = mipsnet_class_init, 285 }; 286 287 static void mipsnet_register_types(void) 288 { 289 type_register_static(&mipsnet_info); 290 } 291 292 type_init(mipsnet_register_types) 293