1 #include "qemu/osdep.h" 2 #include "hw/irq.h" 3 #include "hw/qdev-properties.h" 4 #include "net/net.h" 5 #include "qemu/module.h" 6 #include "trace.h" 7 #include "hw/sysbus.h" 8 #include "migration/vmstate.h" 9 #include "qom/object.h" 10 11 /* MIPSnet register offsets */ 12 13 #define MIPSNET_DEV_ID 0x00 14 #define MIPSNET_BUSY 0x08 15 #define MIPSNET_RX_DATA_COUNT 0x0c 16 #define MIPSNET_TX_DATA_COUNT 0x10 17 #define MIPSNET_INT_CTL 0x14 18 # define MIPSNET_INTCTL_TXDONE 0x00000001 19 # define MIPSNET_INTCTL_RXDONE 0x00000002 20 # define MIPSNET_INTCTL_TESTBIT 0x80000000 21 #define MIPSNET_INTERRUPT_INFO 0x18 22 #define MIPSNET_RX_DATA_BUFFER 0x1c 23 #define MIPSNET_TX_DATA_BUFFER 0x20 24 25 #define MAX_ETH_FRAME_SIZE 1514 26 27 #define TYPE_MIPS_NET "mipsnet" 28 typedef struct MIPSnetState MIPSnetState; 29 DECLARE_INSTANCE_CHECKER(MIPSnetState, MIPS_NET, 30 TYPE_MIPS_NET) 31 32 struct MIPSnetState { 33 SysBusDevice parent_obj; 34 35 uint32_t busy; 36 uint32_t rx_count; 37 uint32_t rx_read; 38 uint32_t tx_count; 39 uint32_t tx_written; 40 uint32_t intctl; 41 uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; 42 uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; 43 MemoryRegion io; 44 qemu_irq irq; 45 NICState *nic; 46 NICConf conf; 47 }; 48 49 static void mipsnet_reset(MIPSnetState *s) 50 { 51 s->busy = 1; 52 s->rx_count = 0; 53 s->rx_read = 0; 54 s->tx_count = 0; 55 s->tx_written = 0; 56 s->intctl = 0; 57 memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE); 58 memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE); 59 } 60 61 static void mipsnet_update_irq(MIPSnetState *s) 62 { 63 int isr = !!s->intctl; 64 trace_mipsnet_irq(isr, s->intctl); 65 qemu_set_irq(s->irq, isr); 66 } 67 68 static int mipsnet_buffer_full(MIPSnetState *s) 69 { 70 if (s->rx_count >= MAX_ETH_FRAME_SIZE) { 71 return 1; 72 } 73 return 0; 74 } 75 76 static int mipsnet_can_receive(NetClientState *nc) 77 { 78 MIPSnetState *s = qemu_get_nic_opaque(nc); 79 80 if (s->busy) { 81 return 0; 82 } 83 return !mipsnet_buffer_full(s); 84 } 85 86 static ssize_t mipsnet_receive(NetClientState *nc, 87 const uint8_t *buf, size_t size) 88 { 89 MIPSnetState *s = qemu_get_nic_opaque(nc); 90 91 trace_mipsnet_receive(size); 92 if (!mipsnet_can_receive(nc)) { 93 return 0; 94 } 95 96 if (size >= sizeof(s->rx_buffer)) { 97 return 0; 98 } 99 s->busy = 1; 100 101 /* Just accept everything. */ 102 103 /* Write packet data. */ 104 memcpy(s->rx_buffer, buf, size); 105 106 s->rx_count = size; 107 s->rx_read = 0; 108 109 /* Now we can signal we have received something. */ 110 s->intctl |= MIPSNET_INTCTL_RXDONE; 111 mipsnet_update_irq(s); 112 113 return size; 114 } 115 116 static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr, 117 unsigned int size) 118 { 119 MIPSnetState *s = opaque; 120 int ret = 0; 121 122 addr &= 0x3f; 123 switch (addr) { 124 case MIPSNET_DEV_ID: 125 ret = be32_to_cpu(0x4d495053); /* MIPS */ 126 break; 127 case MIPSNET_DEV_ID + 4: 128 ret = be32_to_cpu(0x4e455430); /* NET0 */ 129 break; 130 case MIPSNET_BUSY: 131 ret = s->busy; 132 break; 133 case MIPSNET_RX_DATA_COUNT: 134 ret = s->rx_count; 135 break; 136 case MIPSNET_TX_DATA_COUNT: 137 ret = s->tx_count; 138 break; 139 case MIPSNET_INT_CTL: 140 ret = s->intctl; 141 s->intctl &= ~MIPSNET_INTCTL_TESTBIT; 142 break; 143 case MIPSNET_INTERRUPT_INFO: 144 /* XXX: This seems to be a per-VPE interrupt number. */ 145 ret = 0; 146 break; 147 case MIPSNET_RX_DATA_BUFFER: 148 if (s->rx_count) { 149 s->rx_count--; 150 ret = s->rx_buffer[s->rx_read++]; 151 if (mipsnet_can_receive(s->nic->ncs)) { 152 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 153 } 154 } 155 break; 156 /* Reads as zero. */ 157 case MIPSNET_TX_DATA_BUFFER: 158 default: 159 break; 160 } 161 trace_mipsnet_read(addr, ret); 162 return ret; 163 } 164 165 static void mipsnet_ioport_write(void *opaque, hwaddr addr, 166 uint64_t val, unsigned int size) 167 { 168 MIPSnetState *s = opaque; 169 170 addr &= 0x3f; 171 trace_mipsnet_write(addr, val); 172 switch (addr) { 173 case MIPSNET_TX_DATA_COUNT: 174 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; 175 s->tx_written = 0; 176 break; 177 case MIPSNET_INT_CTL: 178 if (val & MIPSNET_INTCTL_TXDONE) { 179 s->intctl &= ~MIPSNET_INTCTL_TXDONE; 180 } else if (val & MIPSNET_INTCTL_RXDONE) { 181 s->intctl &= ~MIPSNET_INTCTL_RXDONE; 182 } else if (val & MIPSNET_INTCTL_TESTBIT) { 183 mipsnet_reset(s); 184 s->intctl |= MIPSNET_INTCTL_TESTBIT; 185 } else if (!val) { 186 /* ACK testbit interrupt, flag was cleared on read. */ 187 } 188 s->busy = !!s->intctl; 189 mipsnet_update_irq(s); 190 if (mipsnet_can_receive(s->nic->ncs)) { 191 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 192 } 193 break; 194 case MIPSNET_TX_DATA_BUFFER: 195 s->tx_buffer[s->tx_written++] = val; 196 if ((s->tx_written >= MAX_ETH_FRAME_SIZE) 197 || (s->tx_written == s->tx_count)) { 198 /* Send buffer. */ 199 trace_mipsnet_send(s->tx_written); 200 qemu_send_packet(qemu_get_queue(s->nic), 201 s->tx_buffer, s->tx_written); 202 s->tx_count = s->tx_written = 0; 203 s->intctl |= MIPSNET_INTCTL_TXDONE; 204 s->busy = 1; 205 mipsnet_update_irq(s); 206 } 207 break; 208 /* Read-only registers */ 209 case MIPSNET_DEV_ID: 210 case MIPSNET_BUSY: 211 case MIPSNET_RX_DATA_COUNT: 212 case MIPSNET_INTERRUPT_INFO: 213 case MIPSNET_RX_DATA_BUFFER: 214 default: 215 break; 216 } 217 } 218 219 static const VMStateDescription vmstate_mipsnet = { 220 .name = "mipsnet", 221 .version_id = 0, 222 .minimum_version_id = 0, 223 .fields = (VMStateField[]) { 224 VMSTATE_UINT32(busy, MIPSnetState), 225 VMSTATE_UINT32(rx_count, MIPSnetState), 226 VMSTATE_UINT32(rx_read, MIPSnetState), 227 VMSTATE_UINT32(tx_count, MIPSnetState), 228 VMSTATE_UINT32(tx_written, MIPSnetState), 229 VMSTATE_UINT32(intctl, MIPSnetState), 230 VMSTATE_BUFFER(rx_buffer, MIPSnetState), 231 VMSTATE_BUFFER(tx_buffer, MIPSnetState), 232 VMSTATE_END_OF_LIST() 233 } 234 }; 235 236 static NetClientInfo net_mipsnet_info = { 237 .type = NET_CLIENT_DRIVER_NIC, 238 .size = sizeof(NICState), 239 .receive = mipsnet_receive, 240 }; 241 242 static const MemoryRegionOps mipsnet_ioport_ops = { 243 .read = mipsnet_ioport_read, 244 .write = mipsnet_ioport_write, 245 .impl.min_access_size = 1, 246 .impl.max_access_size = 4, 247 }; 248 249 static void mipsnet_realize(DeviceState *dev, Error **errp) 250 { 251 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 252 MIPSnetState *s = MIPS_NET(dev); 253 254 memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s, 255 "mipsnet-io", 36); 256 sysbus_init_mmio(sbd, &s->io); 257 sysbus_init_irq(sbd, &s->irq); 258 259 s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf, 260 object_get_typename(OBJECT(dev)), dev->id, s); 261 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 262 } 263 264 static void mipsnet_sysbus_reset(DeviceState *dev) 265 { 266 MIPSnetState *s = MIPS_NET(dev); 267 mipsnet_reset(s); 268 } 269 270 static Property mipsnet_properties[] = { 271 DEFINE_NIC_PROPERTIES(MIPSnetState, conf), 272 DEFINE_PROP_END_OF_LIST(), 273 }; 274 275 static void mipsnet_class_init(ObjectClass *klass, void *data) 276 { 277 DeviceClass *dc = DEVICE_CLASS(klass); 278 279 dc->realize = mipsnet_realize; 280 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 281 dc->desc = "MIPS Simulator network device"; 282 dc->reset = mipsnet_sysbus_reset; 283 dc->vmsd = &vmstate_mipsnet; 284 device_class_set_props(dc, mipsnet_properties); 285 } 286 287 static const TypeInfo mipsnet_info = { 288 .name = TYPE_MIPS_NET, 289 .parent = TYPE_SYS_BUS_DEVICE, 290 .instance_size = sizeof(MIPSnetState), 291 .class_init = mipsnet_class_init, 292 }; 293 294 static void mipsnet_register_types(void) 295 { 296 type_register_static(&mipsnet_info); 297 } 298 299 type_init(mipsnet_register_types) 300