1 #include "qemu/osdep.h" 2 #include "hw/hw.h" 3 #include "net/net.h" 4 #include "qemu/module.h" 5 #include "trace.h" 6 #include "hw/sysbus.h" 7 8 /* MIPSnet register offsets */ 9 10 #define MIPSNET_DEV_ID 0x00 11 #define MIPSNET_BUSY 0x08 12 #define MIPSNET_RX_DATA_COUNT 0x0c 13 #define MIPSNET_TX_DATA_COUNT 0x10 14 #define MIPSNET_INT_CTL 0x14 15 # define MIPSNET_INTCTL_TXDONE 0x00000001 16 # define MIPSNET_INTCTL_RXDONE 0x00000002 17 # define MIPSNET_INTCTL_TESTBIT 0x80000000 18 #define MIPSNET_INTERRUPT_INFO 0x18 19 #define MIPSNET_RX_DATA_BUFFER 0x1c 20 #define MIPSNET_TX_DATA_BUFFER 0x20 21 22 #define MAX_ETH_FRAME_SIZE 1514 23 24 #define TYPE_MIPS_NET "mipsnet" 25 #define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET) 26 27 typedef struct MIPSnetState { 28 SysBusDevice parent_obj; 29 30 uint32_t busy; 31 uint32_t rx_count; 32 uint32_t rx_read; 33 uint32_t tx_count; 34 uint32_t tx_written; 35 uint32_t intctl; 36 uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; 37 uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; 38 MemoryRegion io; 39 qemu_irq irq; 40 NICState *nic; 41 NICConf conf; 42 } MIPSnetState; 43 44 static void mipsnet_reset(MIPSnetState *s) 45 { 46 s->busy = 1; 47 s->rx_count = 0; 48 s->rx_read = 0; 49 s->tx_count = 0; 50 s->tx_written = 0; 51 s->intctl = 0; 52 memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE); 53 memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE); 54 } 55 56 static void mipsnet_update_irq(MIPSnetState *s) 57 { 58 int isr = !!s->intctl; 59 trace_mipsnet_irq(isr, s->intctl); 60 qemu_set_irq(s->irq, isr); 61 } 62 63 static int mipsnet_buffer_full(MIPSnetState *s) 64 { 65 if (s->rx_count >= MAX_ETH_FRAME_SIZE) 66 return 1; 67 return 0; 68 } 69 70 static int mipsnet_can_receive(NetClientState *nc) 71 { 72 MIPSnetState *s = qemu_get_nic_opaque(nc); 73 74 if (s->busy) 75 return 0; 76 return !mipsnet_buffer_full(s); 77 } 78 79 static ssize_t mipsnet_receive(NetClientState *nc, const uint8_t *buf, size_t size) 80 { 81 MIPSnetState *s = qemu_get_nic_opaque(nc); 82 83 trace_mipsnet_receive(size); 84 if (!mipsnet_can_receive(nc)) 85 return 0; 86 87 if (size >= sizeof(s->rx_buffer)) { 88 return 0; 89 } 90 s->busy = 1; 91 92 /* Just accept everything. */ 93 94 /* Write packet data. */ 95 memcpy(s->rx_buffer, buf, size); 96 97 s->rx_count = size; 98 s->rx_read = 0; 99 100 /* Now we can signal we have received something. */ 101 s->intctl |= MIPSNET_INTCTL_RXDONE; 102 mipsnet_update_irq(s); 103 104 return size; 105 } 106 107 static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr, 108 unsigned int size) 109 { 110 MIPSnetState *s = opaque; 111 int ret = 0; 112 113 addr &= 0x3f; 114 switch (addr) { 115 case MIPSNET_DEV_ID: 116 ret = be32_to_cpu(0x4d495053); /* MIPS */ 117 break; 118 case MIPSNET_DEV_ID + 4: 119 ret = be32_to_cpu(0x4e455430); /* NET0 */ 120 break; 121 case MIPSNET_BUSY: 122 ret = s->busy; 123 break; 124 case MIPSNET_RX_DATA_COUNT: 125 ret = s->rx_count; 126 break; 127 case MIPSNET_TX_DATA_COUNT: 128 ret = s->tx_count; 129 break; 130 case MIPSNET_INT_CTL: 131 ret = s->intctl; 132 s->intctl &= ~MIPSNET_INTCTL_TESTBIT; 133 break; 134 case MIPSNET_INTERRUPT_INFO: 135 /* XXX: This seems to be a per-VPE interrupt number. */ 136 ret = 0; 137 break; 138 case MIPSNET_RX_DATA_BUFFER: 139 if (s->rx_count) { 140 s->rx_count--; 141 ret = s->rx_buffer[s->rx_read++]; 142 if (mipsnet_can_receive(s->nic->ncs)) { 143 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 144 } 145 } 146 break; 147 /* Reads as zero. */ 148 case MIPSNET_TX_DATA_BUFFER: 149 default: 150 break; 151 } 152 trace_mipsnet_read(addr, ret); 153 return ret; 154 } 155 156 static void mipsnet_ioport_write(void *opaque, hwaddr addr, 157 uint64_t val, unsigned int size) 158 { 159 MIPSnetState *s = opaque; 160 161 addr &= 0x3f; 162 trace_mipsnet_write(addr, val); 163 switch (addr) { 164 case MIPSNET_TX_DATA_COUNT: 165 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; 166 s->tx_written = 0; 167 break; 168 case MIPSNET_INT_CTL: 169 if (val & MIPSNET_INTCTL_TXDONE) { 170 s->intctl &= ~MIPSNET_INTCTL_TXDONE; 171 } else if (val & MIPSNET_INTCTL_RXDONE) { 172 s->intctl &= ~MIPSNET_INTCTL_RXDONE; 173 } else if (val & MIPSNET_INTCTL_TESTBIT) { 174 mipsnet_reset(s); 175 s->intctl |= MIPSNET_INTCTL_TESTBIT; 176 } else if (!val) { 177 /* ACK testbit interrupt, flag was cleared on read. */ 178 } 179 s->busy = !!s->intctl; 180 mipsnet_update_irq(s); 181 if (mipsnet_can_receive(s->nic->ncs)) { 182 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 183 } 184 break; 185 case MIPSNET_TX_DATA_BUFFER: 186 s->tx_buffer[s->tx_written++] = val; 187 if ((s->tx_written >= MAX_ETH_FRAME_SIZE) 188 || (s->tx_written == s->tx_count)) { 189 /* Send buffer. */ 190 trace_mipsnet_send(s->tx_written); 191 qemu_send_packet(qemu_get_queue(s->nic), 192 s->tx_buffer, s->tx_written); 193 s->tx_count = s->tx_written = 0; 194 s->intctl |= MIPSNET_INTCTL_TXDONE; 195 s->busy = 1; 196 mipsnet_update_irq(s); 197 } 198 break; 199 /* Read-only registers */ 200 case MIPSNET_DEV_ID: 201 case MIPSNET_BUSY: 202 case MIPSNET_RX_DATA_COUNT: 203 case MIPSNET_INTERRUPT_INFO: 204 case MIPSNET_RX_DATA_BUFFER: 205 default: 206 break; 207 } 208 } 209 210 static const VMStateDescription vmstate_mipsnet = { 211 .name = "mipsnet", 212 .version_id = 0, 213 .minimum_version_id = 0, 214 .fields = (VMStateField[]) { 215 VMSTATE_UINT32(busy, MIPSnetState), 216 VMSTATE_UINT32(rx_count, MIPSnetState), 217 VMSTATE_UINT32(rx_read, MIPSnetState), 218 VMSTATE_UINT32(tx_count, MIPSnetState), 219 VMSTATE_UINT32(tx_written, MIPSnetState), 220 VMSTATE_UINT32(intctl, MIPSnetState), 221 VMSTATE_BUFFER(rx_buffer, MIPSnetState), 222 VMSTATE_BUFFER(tx_buffer, MIPSnetState), 223 VMSTATE_END_OF_LIST() 224 } 225 }; 226 227 static NetClientInfo net_mipsnet_info = { 228 .type = NET_CLIENT_DRIVER_NIC, 229 .size = sizeof(NICState), 230 .receive = mipsnet_receive, 231 }; 232 233 static const MemoryRegionOps mipsnet_ioport_ops = { 234 .read = mipsnet_ioport_read, 235 .write = mipsnet_ioport_write, 236 .impl.min_access_size = 1, 237 .impl.max_access_size = 4, 238 }; 239 240 static void mipsnet_realize(DeviceState *dev, Error **errp) 241 { 242 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 243 MIPSnetState *s = MIPS_NET(dev); 244 245 memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s, 246 "mipsnet-io", 36); 247 sysbus_init_mmio(sbd, &s->io); 248 sysbus_init_irq(sbd, &s->irq); 249 250 s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf, 251 object_get_typename(OBJECT(dev)), dev->id, s); 252 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 253 } 254 255 static void mipsnet_sysbus_reset(DeviceState *dev) 256 { 257 MIPSnetState *s = MIPS_NET(dev); 258 mipsnet_reset(s); 259 } 260 261 static Property mipsnet_properties[] = { 262 DEFINE_NIC_PROPERTIES(MIPSnetState, conf), 263 DEFINE_PROP_END_OF_LIST(), 264 }; 265 266 static void mipsnet_class_init(ObjectClass *klass, void *data) 267 { 268 DeviceClass *dc = DEVICE_CLASS(klass); 269 270 dc->realize = mipsnet_realize; 271 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 272 dc->desc = "MIPS Simulator network device"; 273 dc->reset = mipsnet_sysbus_reset; 274 dc->vmsd = &vmstate_mipsnet; 275 dc->props = mipsnet_properties; 276 } 277 278 static const TypeInfo mipsnet_info = { 279 .name = TYPE_MIPS_NET, 280 .parent = TYPE_SYS_BUS_DEVICE, 281 .instance_size = sizeof(MIPSnetState), 282 .class_init = mipsnet_class_init, 283 }; 284 285 static void mipsnet_register_types(void) 286 { 287 type_register_static(&mipsnet_info); 288 } 289 290 type_init(mipsnet_register_types) 291