1 /* 2 * QEMU AMD PC-Net II (Am79C970A) emulation 3 * 4 * Copyright (c) 2004 Antony T Curtis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* This software was written to be compatible with the specification: 26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet 27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 28 */ 29 30 /* 31 * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also 32 * produced as NCR89C100. See 33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 34 * and 35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt 36 */ 37 38 #include "qemu/osdep.h" 39 #include "qemu/module.h" 40 #include "qemu/timer.h" 41 #include "hw/sparc/sparc32_dma.h" 42 #include "migration/vmstate.h" 43 #include "hw/net/lance.h" 44 #include "trace.h" 45 #include "sysemu/sysemu.h" 46 47 48 static void parent_lance_reset(void *opaque, int irq, int level) 49 { 50 SysBusPCNetState *d = opaque; 51 if (level) 52 pcnet_h_reset(&d->state); 53 } 54 55 static void lance_mem_write(void *opaque, hwaddr addr, 56 uint64_t val, unsigned size) 57 { 58 SysBusPCNetState *d = opaque; 59 60 trace_lance_mem_writew(addr, val & 0xffff); 61 pcnet_ioport_writew(&d->state, addr, val & 0xffff); 62 } 63 64 static uint64_t lance_mem_read(void *opaque, hwaddr addr, 65 unsigned size) 66 { 67 SysBusPCNetState *d = opaque; 68 uint32_t val; 69 70 val = pcnet_ioport_readw(&d->state, addr); 71 trace_lance_mem_readw(addr, val & 0xffff); 72 return val & 0xffff; 73 } 74 75 static const MemoryRegionOps lance_mem_ops = { 76 .read = lance_mem_read, 77 .write = lance_mem_write, 78 .endianness = DEVICE_NATIVE_ENDIAN, 79 .valid = { 80 .min_access_size = 2, 81 .max_access_size = 2, 82 }, 83 }; 84 85 static NetClientInfo net_lance_info = { 86 .type = NET_CLIENT_DRIVER_NIC, 87 .size = sizeof(NICState), 88 .receive = pcnet_receive, 89 .link_status_changed = pcnet_set_link_status, 90 }; 91 92 static const VMStateDescription vmstate_lance = { 93 .name = "pcnet", 94 .version_id = 3, 95 .minimum_version_id = 2, 96 .fields = (VMStateField[]) { 97 VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState), 98 VMSTATE_END_OF_LIST() 99 } 100 }; 101 102 static void lance_realize(DeviceState *dev, Error **errp) 103 { 104 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 105 SysBusPCNetState *d = SYSBUS_PCNET(dev); 106 PCNetState *s = &d->state; 107 108 memory_region_init_io(&s->mmio, OBJECT(d), &lance_mem_ops, d, 109 "lance-mmio", 4); 110 111 qdev_init_gpio_in(dev, parent_lance_reset, 1); 112 113 sysbus_init_mmio(sbd, &s->mmio); 114 115 sysbus_init_irq(sbd, &s->irq); 116 117 s->phys_mem_read = ledma_memory_read; 118 s->phys_mem_write = ledma_memory_write; 119 pcnet_common_init(dev, s, &net_lance_info); 120 } 121 122 static void lance_reset(DeviceState *dev) 123 { 124 SysBusPCNetState *d = SYSBUS_PCNET(dev); 125 126 pcnet_h_reset(&d->state); 127 } 128 129 static void lance_instance_init(Object *obj) 130 { 131 SysBusPCNetState *d = SYSBUS_PCNET(obj); 132 PCNetState *s = &d->state; 133 134 device_add_bootindex_property(obj, &s->conf.bootindex, 135 "bootindex", "/ethernet-phy@0", 136 DEVICE(obj), NULL); 137 } 138 139 static Property lance_properties[] = { 140 DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque), 141 DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf), 142 DEFINE_PROP_END_OF_LIST(), 143 }; 144 145 static void lance_class_init(ObjectClass *klass, void *data) 146 { 147 DeviceClass *dc = DEVICE_CLASS(klass); 148 149 dc->realize = lance_realize; 150 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 151 dc->fw_name = "ethernet"; 152 dc->reset = lance_reset; 153 dc->vmsd = &vmstate_lance; 154 dc->props = lance_properties; 155 /* Reason: pointer property "dma" */ 156 dc->user_creatable = false; 157 } 158 159 static const TypeInfo lance_info = { 160 .name = TYPE_LANCE, 161 .parent = TYPE_SYS_BUS_DEVICE, 162 .instance_size = sizeof(SysBusPCNetState), 163 .class_init = lance_class_init, 164 .instance_init = lance_instance_init, 165 }; 166 167 static void lance_register_types(void) 168 { 169 type_register_static(&lance_info); 170 } 171 172 type_init(lance_register_types) 173