1 /* 2 * QEMU AMD PC-Net II (Am79C970A) emulation 3 * 4 * Copyright (c) 2004 Antony T Curtis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* This software was written to be compatible with the specification: 26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet 27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 28 */ 29 30 /* 31 * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also 32 * produced as NCR89C100. See 33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 34 * and 35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt 36 */ 37 38 #include "hw/sysbus.h" 39 #include "net/net.h" 40 #include "qemu/timer.h" 41 #include "qemu/sockets.h" 42 #include "hw/sparc/sun4m.h" 43 #include "pcnet.h" 44 #include "trace.h" 45 46 #define TYPE_LANCE "lance" 47 #define SYSBUS_PCNET(obj) \ 48 OBJECT_CHECK(SysBusPCNetState, (obj), TYPE_LANCE) 49 50 typedef struct { 51 SysBusDevice parent_obj; 52 53 PCNetState state; 54 } SysBusPCNetState; 55 56 static void parent_lance_reset(void *opaque, int irq, int level) 57 { 58 SysBusPCNetState *d = opaque; 59 if (level) 60 pcnet_h_reset(&d->state); 61 } 62 63 static void lance_mem_write(void *opaque, hwaddr addr, 64 uint64_t val, unsigned size) 65 { 66 SysBusPCNetState *d = opaque; 67 68 trace_lance_mem_writew(addr, val & 0xffff); 69 pcnet_ioport_writew(&d->state, addr, val & 0xffff); 70 } 71 72 static uint64_t lance_mem_read(void *opaque, hwaddr addr, 73 unsigned size) 74 { 75 SysBusPCNetState *d = opaque; 76 uint32_t val; 77 78 val = pcnet_ioport_readw(&d->state, addr); 79 trace_lance_mem_readw(addr, val & 0xffff); 80 return val & 0xffff; 81 } 82 83 static const MemoryRegionOps lance_mem_ops = { 84 .read = lance_mem_read, 85 .write = lance_mem_write, 86 .endianness = DEVICE_NATIVE_ENDIAN, 87 .valid = { 88 .min_access_size = 2, 89 .max_access_size = 2, 90 }, 91 }; 92 93 static void lance_cleanup(NetClientState *nc) 94 { 95 PCNetState *d = qemu_get_nic_opaque(nc); 96 97 pcnet_common_cleanup(d); 98 } 99 100 static NetClientInfo net_lance_info = { 101 .type = NET_CLIENT_OPTIONS_KIND_NIC, 102 .size = sizeof(NICState), 103 .can_receive = pcnet_can_receive, 104 .receive = pcnet_receive, 105 .link_status_changed = pcnet_set_link_status, 106 .cleanup = lance_cleanup, 107 }; 108 109 static const VMStateDescription vmstate_lance = { 110 .name = "pcnet", 111 .version_id = 3, 112 .minimum_version_id = 2, 113 .fields = (VMStateField[]) { 114 VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState), 115 VMSTATE_END_OF_LIST() 116 } 117 }; 118 119 static int lance_init(SysBusDevice *sbd) 120 { 121 DeviceState *dev = DEVICE(sbd); 122 SysBusPCNetState *d = SYSBUS_PCNET(dev); 123 PCNetState *s = &d->state; 124 125 memory_region_init_io(&s->mmio, OBJECT(d), &lance_mem_ops, d, 126 "lance-mmio", 4); 127 128 qdev_init_gpio_in(dev, parent_lance_reset, 1); 129 130 sysbus_init_mmio(sbd, &s->mmio); 131 132 sysbus_init_irq(sbd, &s->irq); 133 134 s->phys_mem_read = ledma_memory_read; 135 s->phys_mem_write = ledma_memory_write; 136 return pcnet_common_init(dev, s, &net_lance_info); 137 } 138 139 static void lance_reset(DeviceState *dev) 140 { 141 SysBusPCNetState *d = SYSBUS_PCNET(dev); 142 143 pcnet_h_reset(&d->state); 144 } 145 146 static Property lance_properties[] = { 147 DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque), 148 DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf), 149 DEFINE_PROP_END_OF_LIST(), 150 }; 151 152 static void lance_class_init(ObjectClass *klass, void *data) 153 { 154 DeviceClass *dc = DEVICE_CLASS(klass); 155 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 156 157 k->init = lance_init; 158 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 159 dc->fw_name = "ethernet"; 160 dc->reset = lance_reset; 161 dc->vmsd = &vmstate_lance; 162 dc->props = lance_properties; 163 /* Reason: pointer property "dma" */ 164 dc->cannot_instantiate_with_device_add_yet = true; 165 } 166 167 static const TypeInfo lance_info = { 168 .name = TYPE_LANCE, 169 .parent = TYPE_SYS_BUS_DEVICE, 170 .instance_size = sizeof(SysBusPCNetState), 171 .class_init = lance_class_init, 172 }; 173 174 static void lance_register_types(void) 175 { 176 type_register_static(&lance_info); 177 } 178 179 type_init(lance_register_types) 180